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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: interrupt_pci_dup_intx.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | ||
40 | #define ENABLE_PCIE_LINK_TRAINING | |
41 | ||
42 | #define ENABLE_INTR0x60 1 | |
43 | ||
44 | #define INTR0x60_MONDO_IV 63 | |
45 | ||
46 | #define INTR0x60_MONDO_20_V 1 | |
47 | #define INTR0x60_MONDO_20_THREAD 1 | |
48 | #define INTR0x60_MONDO_20_CNTRL 0 | |
49 | ||
50 | #define INTR0x60_MONDO_21_V 1 | |
51 | #define INTR0x60_MONDO_21_THREAD 2 | |
52 | #define INTR0x60_MONDO_21_CNTRL 1 | |
53 | ||
54 | #define INTR0x60_MONDO_22_V 1 | |
55 | #define INTR0x60_MONDO_22_THREAD 4 | |
56 | #define INTR0x60_MONDO_22_CNTRL 2 | |
57 | ||
58 | #define INTR0x60_MONDO_23_V 1 | |
59 | #define INTR0x60_MONDO_23_THREAD 6 | |
60 | #define INTR0x60_MONDO_23_CNTRL 3 | |
61 | ||
62 | ||
63 | #define INTR0x60_INTA_EXTRA_HANDLER \ | |
64 | setx intr_count, %g4, %g3; \ | |
65 | add %g3, %g1, %g3; \ | |
66 | ldub [%g3], %g4; \ | |
67 | inc %g4; \ | |
68 | stb %g4, [%g3] | |
69 | #define INTR0x60_INTB_EXTRA_HANDLER INTR0x60_INTA_EXTRA_HANDLER | |
70 | #define INTR0x60_INTC_EXTRA_HANDLER INTR0x60_INTA_EXTRA_HANDLER | |
71 | #define INTR0x60_INTD_EXTRA_HANDLER INTR0x60_INTA_EXTRA_HANDLER | |
72 | ||
73 | #include "interrupt0x60_defines.h" | |
74 | ||
75 | ||
76 | #define SYNC_THREADS 1 | |
77 | ||
78 | #include "hboot.s" | |
79 | #include "peu_defines.h" | |
80 | #include "ncu_defines.h" | |
81 | #include "cmp_macros.h" | |
82 | ||
83 | #include "interrupt0x60_handler.s" | |
84 | ||
85 | ||
86 | /* Extra user events that happen inside the trap handler code */ | |
87 | ! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_inta)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT", 1, *, 1 ) | |
88 | ! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intb)) -> EnablePCIeIgCmd ("INTB", 0, 0, "DEASSERT", 1, *, 1 ) | |
89 | ! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intc)) -> EnablePCIeIgCmd ("INTC", 0, 0, "DEASSERT", 1, *, 1 ) | |
90 | ! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intd)) -> EnablePCIeIgCmd ("INTD", 0, 0, "DEASSERT", 1, *, 1 ) | |
91 | ||
92 | ||
93 | /************************************************************************ | |
94 | Test case code start | |
95 | ************************************************************************/ | |
96 | SECTION .MAIN | |
97 | .text | |
98 | .global main | |
99 | ||
100 | main: | |
101 | ta T_CHANGE_HPRIV | |
102 | nop | |
103 | ||
104 | ldxa [%g0] ASI_INTR_ID, %g1 ! Get the thread number | |
105 | brnz %g1, main_target | |
106 | nop | |
107 | ||
108 | ||
109 | /**************************************************************/ | |
110 | /* We are the "source" thread that sends interrupts */ | |
111 | main_source: | |
112 | /* Kick off the interrupts */ | |
113 | ||
114 | send_inta_intr1: | |
115 | ! user event to generate ASSERT_INTA msg. | |
116 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_inta_intr1)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1, *, 1 ) | |
117 | nop | |
118 | ||
119 | send_inta_intr2: | |
120 | ! user event to generate ASSERT_INTA msg. | |
121 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_inta_intr2)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1, *, 1 ) | |
122 | nop | |
123 | ||
124 | send_intd_intr1: | |
125 | ! user event to generate ASSERT_INTD msg. | |
126 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_intd_intr1)) -> EnablePCIeIgCmd ("INTD", 0, 0, "ASSERT", 1, *, 1 ) | |
127 | nop | |
128 | ||
129 | send_intd_intr2: | |
130 | ! user event to generate ASSERT_INTD msg. | |
131 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_intd_intr2)) -> EnablePCIeIgCmd ("INTD", 0, 0, "ASSERT", 1, *, 1 ) | |
132 | nop | |
133 | ||
134 | send_intb_intr1: | |
135 | ! user event to generate ASSERT_INTB msg. | |
136 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_intb_intr1)) -> EnablePCIeIgCmd ("INTB", 0, 0, "ASSERT", 1, *, 1 ) | |
137 | nop | |
138 | ||
139 | send_intb_intr2: | |
140 | ! user event to generate ASSERT_INTB msg. | |
141 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_intb_intr2)) -> EnablePCIeIgCmd ("INTB", 0, 0, "ASSERT", 1, *, 1 ) | |
142 | nop | |
143 | ||
144 | send_intc_intr1: | |
145 | ! user event to generate ASSERT_INTC msg. | |
146 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_intc_intr1)) -> EnablePCIeIgCmd ("INTC", 0, 0, "ASSERT", 1, *, 1 ) | |
147 | nop | |
148 | ||
149 | send_intc_intr2: | |
150 | ! user event to generate ASSERT_INTC msg. | |
151 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_intc_intr2)) -> EnablePCIeIgCmd ("INTC", 0, 0, "ASSERT", 1, *, 1 ) | |
152 | nop | |
153 | ||
154 | /* We are all done sending interrupts, to go to good trap */ | |
155 | /* EXIT_GOOD */ | |
156 | ||
157 | /**************************************************************/ | |
158 | /* Code for target threads */ | |
159 | main_target: | |
160 | intr_wait_2: | |
161 | setx intr_expect, %l1, %g4 | |
162 | add %g4, %g1, %g4 ! address of expected interrupt count for this thread | |
163 | ldub [%g4], %g4 | |
164 | ||
165 | setx intr_count, %l1, %g3 | |
166 | add %g3, %g1, %g3 ! address of interrupt count for this thread | |
167 | ||
168 | best_set_reg(0x200, %l1, %g2) ! timeout count | |
169 | ||
170 | intr_wait_loop_top_2: | |
171 | ldub [%g3], %g5 | |
172 | cmp %g5, %g4 | |
173 | be thread_got_expected_intr_count | |
174 | dec %g2 | |
175 | ||
176 | cmp %g2, 0 | |
177 | bne intr_wait_loop_top_2 | |
178 | nop | |
179 | ||
180 | intr_timeout: | |
181 | !$EV trig_pc_d(1, @VA(.MAIN.intr_timeout)) -> printf("ERROR: Timeout waiting for interrupt",*,1) | |
182 | EXIT_BAD | |
183 | ||
184 | thread_got_expected_intr_count: | |
185 | setx num_threads_waiting_for_expected_intr_count, %l1, %l2 | |
186 | lduw [%l2], %l3 | |
187 | decrement_waiting_threads: | |
188 | sub %l3, 1, %l4 | |
189 | cas [%l2], %l3, %l4 | |
190 | cmp %l3, %l4 | |
191 | bne decrement_waiting_threads | |
192 | mov %l4, %l3 ! to avoid another lduw for the branching case | |
193 | ||
194 | wait_for_all_threads: | |
195 | lduw [%l2], %l3 | |
196 | brnz %l3, wait_for_all_threads | |
197 | mov 100, %l7 | |
198 | ||
199 | delay_before_final_check: ! allow time for unexpected interrupts | |
200 | dec %l7 | |
201 | brgz %l7, delay_before_final_check | |
202 | ||
203 | final_check: | |
204 | ldub [%g3], %g5 | |
205 | cmp %g5, %g4 | |
206 | bne local_test_failed | |
207 | nop | |
208 | ||
209 | thread_passed: | |
210 | EXIT_GOOD | |
211 | ||
212 | local_test_failed: | |
213 | EXIT_BAD | |
214 | ||
215 | ||
216 | ||
217 | /************************************************************************ | |
218 | Test case data start | |
219 | ************************************************************************/ | |
220 | ||
221 | .align 1024 | |
222 | .data | |
223 | user_data_start: | |
224 | num_threads_waiting_for_expected_intr_count: | |
225 | .word 8 | |
226 | intr_expect: | |
227 | .byte 0 ! expected interrupt count for thread 0 | |
228 | .byte 1 ! expected interrupt count for thread 1 | |
229 | .byte 1 ! expected interrupt count for thread 2 | |
230 | .byte 0 ! expected interrupt count for thread 3 | |
231 | .byte 1 ! expected interrupt count for thread 4 | |
232 | .byte 0 ! expected interrupt count for thread 5 | |
233 | .byte 1 ! expected interrupt count for thread 6 | |
234 | .byte 0 ! expected interrupt count for thread 7 | |
235 | user_data_end: | |
236 | ||
237 | ||
238 | SECTION .HTRAPS | |
239 | .data | |
240 | .global intr_count | |
241 | intr_count: | |
242 | .byte 0 ! interrupt count for thread 0 | |
243 | .byte 0 ! interrupt count for thread 1 | |
244 | .byte 0 ! interrupt count for thread 2 | |
245 | .byte 0 ! interrupt count for thread 3 | |
246 | .byte 0 ! interrupt count for thread 4 | |
247 | .byte 0 ! interrupt count for thread 5 | |
248 | .byte 0 ! interrupt count for thread 6 | |
249 | .byte 0 ! interrupt count for thread 7 | |
250 | ||
251 | .end | |
252 | ||
253 | /************************************************************************/ |