Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / l2 / allcores_allbanks_atomic.s
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: allcores_allbanks_atomic.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40#define TEST_DATA 0x5555555555555555
41#define L2_BANK0 0x3a000000
42#define L2_BANK1 0x3a000040
43#define L2_BANK2 0x3a000080
44#define L2_BANK3 0x3a0000c0
45#define L2_BANK4 0x3a000100
46#define L2_BANK5 0x3a000140
47#define L2_BANK6 0x3a000180
48#define L2_BANK7 0x3a0001c0
49
50#include "hboot.s"
51#include "asi_s.h"
52
53/************************************************************************
54 Test case code start
55 ************************************************************************/
56
57.text
58.global main
59
60main:
61 ta T_CHANGE_HPRIV
62
63!
64! Thread 0 Start
65!
66thread_0:
67 ta T_RD_THID
68 setx 256, %g1, %l7
69 umul %o1, %l7, %l7
70 setx user_data_start, %g1, %g3
71 add %l7, %g3, %l7
72
73 ! All threads executed same code, with different data areas
74
75
76
77casa_bank0:
78 setx L2_BANK0, %g1, %g2
79 setx TEST_DATA, %g1, %l4
80 setx 0xffffffffffffffff, %g1, %l0
81 stx %l4, [%g2]
82 membar #Sync
83 casa [%g2]ASI_PRIMARY, %l4, %l0
84 cmp %l0, %l4
85 bne test_failed
86 nop
87 setx 0xffffffff, %g1, %g4
88 ld [%g2], %l1
89 cmp %g4, %l1
90 bne test_failed
91 nop
92caxsa_Bank0:
93 setx 0xffffffffffffffff, %g1, %l0
94 casxa [%g2]ASI_PRIMARY, %l4, %l0
95 cmp %l0, %l4
96 bne test_failed
97 nop
98 setx 0xffffffffffffffff, %g1, %g4
99 ld [%g2], %l1
100 cmp %g4, %l1
101 bne test_failed
102 nop
103
104
105
106casa_bank1:
107 setx L2_BANK1, %g1, %g2
108 setx TEST_DATA, %g1, %l4
109 setx 0xffffffffffffffff, %g1, %l0
110 stx %l4, [%g2]
111 membar #Sync
112 casa [%g2]ASI_PRIMARY, %l4, %l0
113 cmp %l0, %l4
114 bne test_failed
115 nop
116 setx 0xffffffff, %g1, %g4
117 ld [%g2], %l1
118 cmp %g4, %l1
119 bne test_failed
120 nop
121caxsa_Bank1:
122 setx 0xffffffffffffffff, %g1, %l0
123 casxa [%g2]ASI_PRIMARY, %l4, %l0
124 cmp %l0, %l4
125 bne test_failed
126 nop
127 setx 0xffffffffffffffff, %g1, %g4
128 ld [%g2], %l1
129 cmp %g4, %l1
130 bne test_failed
131 nop
132
133
134casa_bank2:
135 setx L2_BANK2, %g1, %g2
136 setx TEST_DATA, %g1, %l4
137 setx 0xffffffffffffffff, %g1, %l0
138 stx %l4, [%g2]
139 membar #Sync
140 casa [%g2]ASI_PRIMARY, %l4, %l0
141 cmp %l0, %l4
142 bne test_failed
143 nop
144 setx 0xffffffff, %g1, %g4
145 ld [%g2], %l1
146 cmp %g4, %l1
147 bne test_failed
148 nop
149caxsa_Bank2:
150 setx 0xffffffffffffffff, %g1, %l0
151 casxa [%g2]ASI_PRIMARY, %l4, %l0
152 cmp %l0, %l4
153 bne test_failed
154 nop
155 setx 0xffffffffffffffff, %g1, %g4
156 ld [%g2], %l1
157 cmp %g4, %l1
158 bne test_failed
159 nop
160
161
162casa_bank3:
163 setx L2_BANK3, %g1, %g2
164 setx TEST_DATA, %g1, %l4
165 setx 0xffffffffffffffff, %g1, %l0
166 stx %l4, [%g2]
167 membar #Sync
168 casa [%g2]ASI_PRIMARY, %l4, %l0
169 cmp %l0, %l4
170 bne test_failed
171 nop
172 setx 0xffffffff, %g1, %g4
173 ld [%g2], %l1
174 cmp %g4, %l1
175 bne test_failed
176 nop
177caxsa_Bank3:
178 setx 0xffffffffffffffff, %g1, %l0
179 casxa [%g2]ASI_PRIMARY, %l4, %l0
180 cmp %l0, %l4
181 bne test_failed
182 nop
183 setx 0xffffffffffffffff, %g1, %g4
184 ld [%g2], %l1
185 cmp %g4, %l1
186 bne test_failed
187 nop
188
189
190casa_bank4:
191 setx L2_BANK4, %g1, %g2
192 setx TEST_DATA, %g1, %l4
193 setx 0xffffffffffffffff, %g1, %l0
194 stx %l4, [%g2]
195 membar #Sync
196 casa [%g2]ASI_PRIMARY, %l4, %l0
197 cmp %l0, %l4
198 bne test_failed
199 nop
200 setx 0xffffffff, %g1, %g4
201 ld [%g2], %l1
202 cmp %g4, %l1
203 bne test_failed
204 nop
205caxsa_Bank4:
206 setx 0xffffffffffffffff, %g1, %l0
207 casxa [%g2]ASI_PRIMARY, %l4, %l0
208 cmp %l0, %l4
209 bne test_failed
210 nop
211 setx 0xffffffffffffffff, %g1, %g4
212 ld [%g2], %l1
213 cmp %g4, %l1
214 bne test_failed
215 nop
216
217
218casa_bank5:
219 setx L2_BANK5, %g1, %g2
220 setx TEST_DATA, %g1, %l4
221 setx 0xffffffffffffffff, %g1, %l0
222 stx %l4, [%g2]
223 membar #Sync
224 casa [%g2]ASI_PRIMARY, %l4, %l0
225 cmp %l0, %l4
226 bne test_failed
227 nop
228 setx 0xffffffff, %g1, %g4
229 ld [%g2], %l1
230 cmp %g4, %l1
231 bne test_failed
232 nop
233caxsa_Bank5:
234 setx 0xffffffffffffffff, %g1, %l0
235 casxa [%g2]ASI_PRIMARY, %l4, %l0
236 cmp %l0, %l4
237 bne test_failed
238 nop
239 setx 0xffffffffffffffff, %g1, %g4
240 ld [%g2], %l1
241 cmp %g4, %l1
242 bne test_failed
243 nop
244
245
246casa_bank6:
247 setx L2_BANK6, %g1, %g2
248 setx TEST_DATA, %g1, %l4
249 setx 0xffffffffffffffff, %g1, %l0
250 stx %l4, [%g2]
251 membar #Sync
252 casa [%g2]ASI_PRIMARY, %l4, %l0
253 cmp %l0, %l4
254 bne test_failed
255 nop
256 setx 0xffffffff, %g1, %g4
257 ld [%g2], %l1
258 cmp %g4, %l1
259 bne test_failed
260 nop
261caxsa_Bank6:
262 setx 0xffffffffffffffff, %g1, %l0
263 casxa [%g2]ASI_PRIMARY, %l4, %l0
264 cmp %l0, %l4
265 bne test_failed
266 nop
267 setx 0xffffffffffffffff, %g1, %g4
268 ld [%g2], %l1
269 cmp %g4, %l1
270 bne test_failed
271 nop
272
273
274casa_bank7:
275 setx L2_BANK7, %g1, %g2
276 setx TEST_DATA, %g1, %l4
277 setx 0xffffffffffffffff, %g1, %l0
278 stx %l4, [%g2]
279 membar #Sync
280 casa [%g2]ASI_PRIMARY, %l4, %l0
281 cmp %l0, %l4
282 bne test_failed
283 nop
284 setx 0xffffffff, %g1, %g4
285 ld [%g2], %l1
286 cmp %g4, %l1
287 bne test_failed
288 nop
289caxsa_Bank7:
290 setx 0xffffffffffffffff, %g1, %l0
291 casxa [%g2]ASI_PRIMARY, %l4, %l0
292 cmp %l0, %l4
293 bne test_failed
294 nop
295 setx 0xffffffffffffffff, %g1, %g4
296 ld [%g2], %l1
297 cmp %g4, %l1
298 bne test_failed
299 nop
300
301
302
303test_passed:
304 EXIT_GOOD
305
306test_failed:
307 EXIT_BAD
308
309
310/************************************************************************
311 Test case data start
312 ************************************************************************/
313.data
314user_data_start:
315 .xword 0x0000000000000000
316 .xword 0x1111111111111111
317 .xword 0x2222222222222222
318 .xword 0x3333333333333333
319 .xword 0x4444444444444444
320 .xword 0x5555555555555555
321 .xword 0x6666666666666666
322 .xword 0x7777777777777777
323 .xword 0x8888888888888888
324 .xword 0x9999999999999999
325 .xword 0xaaaaaaaaaaaaaaaa
326 .xword 0xbbbbbbbbbbbbbbbb
327 .xword 0xcccccccccccccccc
328 .xword 0xdddddddddddddddd
329 .xword 0xeeeeeeeeeeeeeeee
330 .xword 0xffffffffffffffff
331.end
332
333
334