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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: tcu_csr_regs_rw.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define TEST_DATA0 0x4c3fdead4c3fbeef | |
42 | ||
43 | #include "hboot.s" | |
44 | #include "asi_s.h" | |
45 | #include "mcu_defines.h" | |
46 | #include "tcu_defines.h" | |
47 | ||
48 | /************************************************************************ | |
49 | Test case code start | |
50 | ************************************************************************/ | |
51 | ||
52 | .text | |
53 | .global main | |
54 | ||
55 | main: | |
56 | ta T_CHANGE_HPRIV | |
57 | ||
58 | ! DRAM_CAS_ADDR_WIDTH_REG | |
59 | L0: | |
60 | setx DRAM_CAS_ADDR_WIDTH_REG, %g1, %g2 | |
61 | setx DRAM_REG_STEP, %g1, %g3 | |
62 | ldx [%g2], %g7 | |
63 | stx %g7, [%g2] | |
64 | ||
65 | add %g2, %g3, %g2 | |
66 | ldx [%g2], %g7 | |
67 | stx %g7, [%g2] | |
68 | ||
69 | add %g2, %g3, %g2 | |
70 | ldx [%g2], %g7 | |
71 | stx %g7, [%g2] | |
72 | ||
73 | add %g2, %g3, %g2 | |
74 | ldx [%g2], %g7 | |
75 | stx %g7, [%g2] | |
76 | ||
77 | ! MBIST_MODE_REG | |
78 | L1: | |
79 | set 0xc, %i3 | |
80 | setx MBIST_MODE_REG, %g1, %g2 | |
81 | stx %i3, [%g2] | |
82 | membar #Sync | |
83 | ldx [%g2], %i7 | |
84 | membar #Sync | |
85 | cmp %i3, %i7 | |
86 | bne test_failed | |
87 | nop | |
88 | ||
89 | ||
90 | ! MBIST_BYPASS_REG | |
91 | L2: | |
92 | set 0xffffffff, %i3 | |
93 | setx MBIST_BYPASS_REG, %g1, %g2 | |
94 | stx %i3, [%g2] | |
95 | membar #Sync | |
96 | ldx [%g2], %i7 | |
97 | membar #Sync | |
98 | cmp %i3, %i7 | |
99 | bne test_failed | |
100 | nop | |
101 | ||
102 | ! MBIST_START_REG | |
103 | L3: | |
104 | setx MBIST_START_REG, %g1, %g2 | |
105 | ldx [%g2], %g7 | |
106 | membar #Sync | |
107 | stx %g7, [%g2] | |
108 | membar #Sync | |
109 | ||
110 | ! MBIST_ABORT_REG | |
111 | L4: | |
112 | setx MBIST_ABORT_REG, %g1, %g2 | |
113 | ldx [%g2], %g7 | |
114 | membar #Sync | |
115 | stx %g7, [%g2] | |
116 | membar #Sync | |
117 | ||
118 | ! MBIST_RESULT_REG | |
119 | L5: | |
120 | setx MBIST_RESULT_REG, %g1, %g2 | |
121 | ldx [%g2], %g7 | |
122 | membar #Sync | |
123 | stx %g7, [%g2] | |
124 | membar #Sync | |
125 | ||
126 | ! MBIST_DONE_REG | |
127 | L6: | |
128 | setx MBIST_DONE_REG, %g1, %g2 | |
129 | ldx [%g2], %g7 | |
130 | membar #Sync | |
131 | stx %g7, [%g2] | |
132 | membar #Sync | |
133 | ||
134 | ! MBIST_FAIL_REG | |
135 | L7: | |
136 | setx MBIST_FAIL_REG, %g1, %g2 | |
137 | ldx [%g2], %g7 | |
138 | membar #Sync | |
139 | stx %g7, [%g2] | |
140 | membar #Sync | |
141 | ||
142 | ! MBIST_START_WMR_REG | |
143 | L8: | |
144 | setx MBIST_START_WMR_REG, %g1, %g2 | |
145 | ldx [%g2], %g7 | |
146 | membar #Sync | |
147 | stx %g7, [%g2] | |
148 | membar #Sync | |
149 | ||
150 | ! LBIST_MODE_REG | |
151 | L9: | |
152 | set 0x3, %i3 | |
153 | setx LBIST_MODE_REG, %g1, %g2 | |
154 | stx %i3, [%g2] | |
155 | membar #Sync | |
156 | ldx [%g2], %i7 | |
157 | membar #Sync | |
158 | cmp %i3, %i7 | |
159 | bne test_failed | |
160 | nop | |
161 | ||
162 | ! LBIST_BYPASS_REG | |
163 | L10: | |
164 | set 0xab, %i3 | |
165 | setx LBIST_BYPASS_REG, %g1, %g2 | |
166 | stx %i3, [%g2] | |
167 | membar #Sync | |
168 | ldx [%g2], %i7 | |
169 | membar #Sync | |
170 | cmp %i3, %i7 | |
171 | bne test_failed | |
172 | nop | |
173 | ||
174 | ! LBIST_START_REG | |
175 | L11: | |
176 | setx LBIST_START_REG, %g1, %g2 | |
177 | ldx [%g2], %g7 | |
178 | membar #Sync | |
179 | stx %g7, [%g2] | |
180 | membar #Sync | |
181 | ||
182 | ! LBIST_DONE_REG | |
183 | L12: | |
184 | setx LBIST_DONE_REG, %g1, %g2 | |
185 | ldx [%g2], %g7 | |
186 | membar #Sync | |
187 | stx %g7, [%g2] | |
188 | membar #Sync | |
189 | ||
190 | ! TCU_DEBUG_EVENT_COUNTER_REG | |
191 | L13: | |
192 | setx TCU_DEBUG_EVENT_COUNTER_REG, %g1, %g2 | |
193 | ldx [%g2], %g7 | |
194 | membar #Sync | |
195 | stx %g7, [%g2] | |
196 | membar #Sync | |
197 | ||
198 | ! TCU_CYCLE_COUNTER_REG | |
199 | L14: | |
200 | set 0xffffffff, %i3 | |
201 | setx TCU_CYCLE_COUNTER_REG, %g1, %g2 | |
202 | stx %i3, [%g2] | |
203 | membar #Sync | |
204 | ldx [%g2], %i7 | |
205 | membar #Sync | |
206 | cmp %i3, %i7 | |
207 | bne test_failed | |
208 | nop | |
209 | ||
210 | ! TCU_CYCLE_COUNTER_REG - non-zero value w/r | |
211 | L15: | |
212 | setx TCU_CYCLE_COUNTER_REG, %g1, %g2 | |
213 | setx TEST_DATA0, %l0, %g3 | |
214 | stx %g3, [%g2] ! store a non-zero value | |
215 | membar #Sync | |
216 | setx MBIST_DONE_REG, %g1, %g4 | |
217 | ldx [%g4], %g5 ! read another register | |
218 | membar #Sync | |
219 | ldx [%g2], %g7 ! read the non-zero value | |
220 | membar #Sync | |
221 | cmp %g3,%g7 ! check the read value | |
222 | bne test_failed | |
223 | nop | |
224 | ||
225 | ! TCU_DEBUG_CONTROL_REG | |
226 | L16: | |
227 | set 0xa, %i3 | |
228 | setx TCU_DEBUG_CONTROL_REG, %g1, %g2 | |
229 | stx %i3, [%g2] | |
230 | membar #Sync | |
231 | ldx [%g2], %i7 | |
232 | membar #Sync | |
233 | cmp %i3, %i7 | |
234 | bne test_failed | |
235 | nop | |
236 | ||
237 | ! TCU_TRIGOUT_REG | |
238 | L17: | |
239 | setx TCU_TRIGOUT_REG, %g1, %g2 | |
240 | ldx [%g2], %g7 | |
241 | membar #Sync | |
242 | stx %g7, [%g2] | |
243 | membar #Sync | |
244 | ||
245 | ! CLKSTOP_DELAY_REG | |
246 | L18: | |
247 | setx CLKSTOP_DELAY_REG, %g1, %g2 | |
248 | ldx [%g2], %g7 | |
249 | membar #Sync | |
250 | stx %g7, [%g2] | |
251 | membar #Sync | |
252 | ||
253 | ! PEUTESTCONFIG_ENABLE_REG | |
254 | L19: | |
255 | setx PEUTESTCONFIG_ENABLE_REG, %g1, %g2 | |
256 | ldx [%g2], %g7 | |
257 | membar #Sync | |
258 | stx %g7, [%g2] | |
259 | membar #Sync | |
260 | ||
261 | ||
262 | test_passed: | |
263 | EXIT_GOOD | |
264 | ||
265 | test_failed: | |
266 | EXIT_BAD | |
267 | ||
268 | ||
269 | /************************************************************************ | |
270 | Test case data start | |
271 | ************************************************************************/ | |
272 | .data | |
273 | user_data_start: | |
274 | .end | |
275 |