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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tcu / tcu_l2_access_ld_st_allbanks.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tcu_l2_access_ld_st_allbanks.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39
40
41#define L2_ENTRY_PA 0xa000000000
42#define TEST_DATA0 0x5555555555555555
43#define TEST_DATA1 0xaaaaaaaaaaaaaaaa
44#define TEST_DATA2 0x4c3fdead4c3fbeef
45#define TEST_DATA3 0xdead4c3fbeef4c3f
46#define L2_ENTRY_PA0 0x2020000008
47#define L2_ES_W1C_VALUE 0xc03ffff800000000
48#define SPARC_ES_W1C_VALUE 0xefffffff
49#define TT_SW_Error 0x40
50
51#include "hboot.s"
52#include "asi_s.h"
53#include "err_defines.h"
54
55.text
56.global main
57
58main:
59
60 ! Boot code does not provide TLB translation for IO address space
61 ta T_CHANGE_HPRIV
62
63disable_l1_DCache:
64 ldxa [%g0] ASI_LSU_CONTROL, %l0
65 ! Remove bit 2
66 andn %l0, 0x2, %l0
67 stxa %l0, [%g0] ASI_LSU_CONTROL
68
69set_L2_Directly_Mapped_Mode:
70 setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
71 mov 0x2, %l0
72 stx %l0, [%g1]
73
74
75store_to_L2_bank0:
76 setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way
77 setx TEST_DATA0, %l0, %g3
78 stx %g3, [%g2]
79 membar #Sync
80 nop
81
82 setx 0x302000c0, %l0, %g4 ! Mask for extracting [21:3]
83 stx %g0, [%g4] ! initialize mem addr where JTAG writes back
84 membar #Sync
85 nop
86start_jtag_rd_bank0:
87 nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank0)) -> jtagRdWrL2(0x002000aa00, TEST_DATA0, 0x00302000c0, 0)
88
89chkJtagWrBank0:
90 nop
91 ldx [%g4], %g6
92 membar #Sync
93 cmp %g6, %g3
94 nop
95 nop
96 nop
97 nop
98 bne chkJtagWrBank0
99 nop
100 membar #Sync
101 nop
102
103
104store_to_L2_bank1:
105 setx 0x2000aa40, %l0, %g2 ! bits [21:18] select way
106 setx TEST_DATA1, %l0, %g3
107 stx %g3, [%g2]
108 membar #Sync
109 nop
110
111 setx 0x30200080, %l0, %g4 ! Mask for extracting [21:3]
112 stx %g0, [%g4] ! initialize mem addr where JTAG writes back
113 membar #Sync
114 nop
115start_jtag_rd_bank1:
116 nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank1)) -> jtagRdWrL2(0x002000aa40, TEST_DATA1, 0x0030200080, 0)
117
118chkJtagWrBank1:
119 nop
120 ldx [%g4], %g6
121 membar #Sync
122 cmp %g6, %g3
123 nop
124 nop
125 nop
126 nop
127 bne chkJtagWrBank1
128 nop
129 membar #Sync
130 nop
131
132
133store_to_L2_bank2:
134 setx 0x2000aa80, %l0, %g2 ! bits [21:18] select way
135 setx TEST_DATA2, %l0, %g3
136 stx %g3, [%g2]
137 membar #Sync
138 nop
139
140 setx 0x30200040, %l0, %g4 ! Mask for extracting [21:3]
141 stx %g0, [%g4] ! initialize mem addr where JTAG writes back
142 membar #Sync
143 nop
144start_jtag_rd_bank2:
145 nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank2)) -> jtagRdWrL2(0x002000aa80, TEST_DATA2, 0x0030200040, 0)
146
147chkJtagWrBank2:
148 nop
149 ldx [%g4], %g6
150 membar #Sync
151 cmp %g6, %g3
152 nop
153 nop
154 nop
155 nop
156 bne chkJtagWrBank2
157 nop
158 membar #Sync
159 nop
160
161
162store_to_L2_bank3:
163 setx 0x2000aac0, %l0, %g2 ! bits [21:18] select way
164 setx TEST_DATA3, %l0, %g3
165 stx %g3, [%g2]
166 membar #Sync
167 nop
168
169 setx 0x30200100, %l0, %g4 ! Mask for extracting [21:3]
170 stx %g0, [%g4] ! initialize mem addr where JTAG writes back
171 membar #Sync
172 nop
173start_jtag_rd_bank3:
174 nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank3)) -> jtagRdWrL2(0x002000aac0, TEST_DATA3, 0x0030200100, 0)
175
176chkJtagWrBank3:
177 nop
178 ldx [%g4], %g6
179 membar #Sync
180 cmp %g6, %g3
181 nop
182 nop
183 nop
184 nop
185 bne chkJtagWrBank3
186 nop
187 membar #Sync
188 nop
189
190
191store_to_L2_bank4:
192 setx 0x2000a100, %l0, %g2 ! bits [21:18] select way
193 setx TEST_DATA3, %l0, %g3
194 stx %g3, [%g2]
195 membar #Sync
196 nop
197
198 setx 0x302001c0, %l0, %g4 ! Mask for extracting [21:3]
199 stx %g0, [%g4] ! initialize mem addr where JTAG writes back
200 membar #Sync
201 nop
202start_jtag_rd_bank4:
203 nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank4)) -> jtagRdWrL2(0x002000a100, TEST_DATA3, 0x00302001c0, 0)
204
205chkJtagWrBank4:
206 nop
207 ldx [%g4], %g6
208 membar #Sync
209 cmp %g6, %g3
210 nop
211 nop
212 nop
213 nop
214 bne chkJtagWrBank4
215 nop
216 membar #Sync
217 nop
218
219
220store_to_L2_bank5:
221 setx 0x2000a140, %l0, %g2 ! bits [21:18] select way
222 setx TEST_DATA2, %l0, %g3
223 stx %g3, [%g2]
224 membar #Sync
225 nop
226
227 setx 0x30200180, %l0, %g4 ! Mask for extracting [21:3]
228 stx %g0, [%g4] ! initialize mem addr where JTAG writes back
229 membar #Sync
230 nop
231start_jtag_rd_bank5:
232 nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank5)) -> jtagRdWrL2(0x002000a140, TEST_DATA2, 0x0030200180, 0)
233
234chkJtagWrBank5:
235 nop
236 ldx [%g4], %g6
237 membar #Sync
238 cmp %g6, %g3
239 nop
240 nop
241 nop
242 nop
243 bne chkJtagWrBank5
244 nop
245 membar #Sync
246 nop
247
248
249store_to_L2_bank6:
250 setx 0x2000a180, %l0, %g2 ! bits [21:18] select way
251 setx TEST_DATA1, %l0, %g3
252 stx %g3, [%g2]
253 membar #Sync
254 nop
255
256 setx 0x30200140, %l0, %g4 ! Mask for extracting [21:3]
257 stx %g0, [%g4] ! initialize mem addr where JTAG writes back
258 membar #Sync
259 nop
260start_jtag_rd_bank6:
261 nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank6)) -> jtagRdWrL2(0x002000a180, TEST_DATA1, 0x0030200140, 0)
262
263chkJtagWrBank6:
264 nop
265 ldx [%g4], %g6
266 membar #Sync
267 cmp %g6, %g3
268 nop
269 nop
270 nop
271 nop
272 bne chkJtagWrBank6
273 nop
274 membar #Sync
275 nop
276
277
278store_to_L2_bank7:
279 setx 0x2000a1c0, %l0, %g2 ! bits [21:18] select way
280 setx TEST_DATA0, %l0, %g3
281 stx %g3, [%g2]
282 membar #Sync
283 nop
284
285 setx 0x30200200, %l0, %g4 ! Mask for extracting [21:3]
286 stx %g0, [%g4] ! initialize mem addr where JTAG writes back
287 membar #Sync
288 nop
289start_jtag_rd_bank7:
290 nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank7)) -> jtagRdWrL2(0x002000a1c0, TEST_DATA0, 0x0030200200, 0)
291
292chkJtagWrBank7:
293 nop
294 ldx [%g4], %g6
295 membar #Sync
296 cmp %g6, %g3
297 nop
298 nop
299 nop
300 nop
301 bne chkJtagWrBank7
302 nop
303 membar #Sync
304 nop
305
306
307enable_l1_DCache:
308 ldxa [%g0] ASI_LSU_CONTROL, %l0
309 or %l0, 0x2, %l0
310 stxa %l0, [%g0] ASI_LSU_CONTROL
311
312 ba test_pass
313 nop
314
315
316/*******************************************************
317 * Exit code
318 *******************************************************/
319
320test_pass:
321ta T_GOOD_TRAP
322
323test_fail:
324ta T_BAD_TRAP
325
326
Full OpenSPARC design & verification tarball including full HDL.