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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_dekker8.pal
CommitLineData
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AT		 1:
2:#define addrA_reg %l0
3:#define turn_reg %l1
4:#define alive_reg %l2
5:#define data_base_reg %l3
6:#define my_id_reg %l4
7:#define global_cnt_reg %l5
8:#define prot_area_reg %l6
9:
10:#define test_reg1 %i0
11:#define test_reg2 %i1
12:#define test_reg3 %i2
13:
14:#define TIMEOUT 0x1000
15:#define ITERATIONS 0x10
16:
17:#include "hboot.s"
18:
19:.global main
20:main:
21:
22: wr %g0, 0x4, %fprs ! make sure fef is 1 for FP ops
23:th_fork(th_main,test_reg1)
24:
25$proc_num = 8;
26if(scalar(@ARGV)){
27 $proc_num = $ARGV[0];
28 if($proc_num >8){
29:#define ITERATIONS 0x2
30 }
31}
32for ( $c = 0; $c < $proc_num; $c++ ){
33$offs = 4 * $c; # threads own offset
34
35:th_main_${c}:
36: setx addrA, test_reg1, addrA_reg
37: setx alive, test_reg1, alive_reg
38: setx turn, test_reg1, turn_reg
39: setx prot_area, test_reg1, prot_area_reg
40: set ITERATIONS, global_cnt_reg
41: set ${c}, my_id_reg ! my ID
42:
43:getlock${c}:
44: prefetch [addrA_reg], #n_writes
45: prefetch [prot_area_reg], #n_writes
46: prefetch [turn_reg], #n_writes
47: set 1, test_reg1 ! store 1 in lock area
48: st test_reg1, [alive_reg + ${offs}] !
49: st test_reg1, [addrA_reg + ${offs}] !
50: membar 0x40 ! IMPORTANT
51:
52: mov %g0, test_reg2
53for ( $k = 0; $k < ${proc_num} * 4; $k = $k + 4) {
54: ld [addrA_reg + ${k}], test_reg1 ! accumulate flags
55: add test_reg1, test_reg2, test_reg2 ! in test_reg2
56}
57:
58: subcc test_reg2, 0x1, %g0 ! if 1 -> gotlock
59: be gotlock${c}
60: nop
61:
62: st %g0, [addrA_reg + ${offs}] ! else release.
63: ! note alive stays on.
64:
65:wait_turn${c}: ! while turn not mine.
66: ld [turn_reg], test_reg3 ! read the turn reg.
67: subcc my_id_reg, test_reg3, %g0 ! and wait
68: bne wait_turn${c}
69: nop
70: ba getlock${c}
71: nop
72:gotlock${c}: ! do something
73: set 1, test_reg1 ! store 1 in lock area
74: st test_reg1, [addrA_reg + ${offs}]
75:
76: ld [prot_area_reg], test_reg1
77: inc test_reg1
78: st test_reg1, [prot_area_reg]
79: ldd [prot_area_reg], %f0 ! FP noise.
80: !faddd %f0, %f0, %f2
81: !fsubd %f2, %f0, %f0
82: std %f0, [prot_area_reg]
83:
84: ld [prot_area_reg + 0xc], test_reg1
85: inc test_reg1
86: st test_reg1, [prot_area_reg + 0xc]
87: ldd [prot_area_reg], %f0 ! FP noise.
88: !faddd %f0, %f0, %f2
89: !fsubd %f2, %f0, %f0
90: std %f0, [prot_area_reg]
91:
92:
93: ld [prot_area_reg + 0x10], test_reg1
94: inc test_reg1
95: st test_reg1, [prot_area_reg + 0x10]
96: ldd [prot_area_reg], %f0 ! FP noise.
97: !faddd %f0, %f0, %f2
98: !fsubd %f2, %f0, %f0
99: std %f0, [prot_area_reg]
100:
101: ld [prot_area_reg + 0x1c], test_reg1
102: inc test_reg1
103: st test_reg1, [prot_area_reg + 0x1c]
104: ldd [prot_area_reg], %f0 ! FP noise.
105: !faddd %f0, %f0, %f2
106: !fsubd %f2, %f0, %f0
107: std %f0, [prot_area_reg]
108:
109: ld [prot_area_reg + 0x20], test_reg1
110: inc test_reg1
111: st test_reg1, [prot_area_reg + 0x20]
112: ldd [prot_area_reg], %f0 ! FP noise.
113: !faddd %f0, %f0, %f2
114: !fsubd %f2, %f0, %f0
115: std %f0, [prot_area_reg]
116:
117:clearlock${c}: ! requires some work
118for($next = ($c+1) % ${proc_num}; $next != $c; $next = ($next+1) % ${proc_num}){
119$tempoffs = 4 * $next;
120: mov ${next}, test_reg2 ! find next living
121: ld [alive_reg + ${tempoffs}], test_reg1 ! process
122: brnz test_reg1, foundnext${c}
123: nop
124}
125:foundnext${c}: ! give it the turn
126: st test_reg2, [turn_reg]
127:
128:check_done${c}: ! check if I am done
129: deccc global_cnt_reg
130: be will_release${c}
131: nop
132: st %g0, [addrA_reg + ${offs}] ! release...
133: ba getlock${c} ! iterate
134: nop
135:will_release${c}:
136: st %g0, [alive_reg + ${offs}] ! I am out of the game
137: st %g0, [addrA_reg + ${offs}] ! release...
138: ba good_end
139: nop
140:
141}
142:!---------------------------------------------------------------------
143:
144:good_end:
145: ta T_GOOD_TRAP
146:bad_end:
147: ta T_BAD_TRAP
148:
149:!==========================
150:
151:
152:SECTION .MY_DATA0 TEXT_VA=0xf0100000, DATA_VA=0xd0100000
153:attr_data {
154: Name = .MY_DATA0,
155: VA= 0x0d0100000
156: RA= 0x1d0100000
157: PA= ra2pa(0x1d0100000,0),
158: part_0_ctx_nonzero_tsb_config_0,
159: TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
160: TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
161: TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
162: }
163:
164:attr_text {
165: Name = .MY_DATA0,
166: VA= 0x0f0100000
167: RA= 0x1f0100000
168: PA= ra2pa(0x1f0100000,0),
169: part_0_ctx_nonzero_tsb_config_0,
170: TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
171: TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
172: TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
173: }
174:
175: .data
176:
177:.global addrA
178:.global turn
179:.align 0x4
180:addrA:
181for ( $k = 0; $k < 32; $k++) {
182: .word 0x0
183: .word 0x0
184}
185:
186:.skip 0x1000
187:.align 0x4
188:turn:
189: .word 0x0
190: .word 0x0
191: .word 0x0
192:
193:SECTION .MY_DATA1 TEXT_VA=0xf1110000, DATA_VA=0xd1110000
194:attr_data {
195: Name = .MY_DATA1,
196: VA= 0x0d1110000,
197: RA= 0x1d1110000,
198: PA= ra2pa(0x1d1110000,0),
199: part_0_ctx_nonzero_tsb_config_0,
200: TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
201: TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
202: TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
203: }
204:
205:attr_text {
206: Name = .MY_DATA1,
207: VA= 0x0f1110000,
208: RA= 0x1f1110000,
209: PA= ra2pa(0x1f1110000,0),
210: part_0_ctx_nonzero_tsb_config_0,
211: TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
212: TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
213: TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
214: }
215:
216: .data
217:.global prot_area
218:prot_area:
219: .word 0xbeef
220: .skip 0x1000
221: .word 0xbeef
222:.global alive
223:alive:
224: .word 0x0
225: .word 0x0
226: .word 0x0
227: .word 0x0
228: .word 0x0
229: .word 0x0
230: .word 0x0
231:
232:.end
Full OpenSPARC design & verification tarball including full HDL.