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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_evict_fanout_dc2_8c.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tso_n1_evict_fanout_dc2_8c.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_BASE_DATA_ADDR 0x160000
39#define MAIN_BASE_TEXT_ADDR 0x150000
40#define MAIN_BASE_DATA_ADDR_RA 0x100160000
41#define MAIN_BASE_TEXT_ADDR_RA 0x100150000
42
43#define DATA2_BASE_DATA_ADDR 0x960000
44#define DATA2_BASE_DATA_ADDR_RA 0x100960000
45
46#define USER_PAGE_CUSTOM_MAP
47
48#define data_base_reg1 %o1
49#define data_base_reg2 %o2
50
51#define my_id_reg %l1
52#define test_reg %l2
53#define counter_reg %l3
54#define tmp1 %l4
55#define tmp2 %l5
56#define tmp3 %l6
57
58#define ITERATIONS 0x1
59
60#include "hboot.s"
61
62SECTION .MAIN TEXT_VA=0x150000, DATA_VA=0x160000
63
64attr_text {
65 Name = .MAIN,
66 VA=MAIN_BASE_TEXT_ADDR,
67 RA=MAIN_BASE_TEXT_ADDR_RA,
68 PA=ra2pa(MAIN_BASE_TEXT_ADDR_RA,0),
69part_0_ctx_nonzero_tsb_config_0,
70 TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
71 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
72 TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
73 }
74attr_data {
75 Name = .MAIN,
76 VA=MAIN_BASE_DATA_ADDR,
77 RA=MAIN_BASE_DATA_ADDR_RA,
78 PA=ra2pa(MAIN_BASE_DATA_ADDR_RA,0),
79part_0_ctx_nonzero_tsb_config_0,
80 TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
81 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
82 TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
83 }
84
85.text
86.global main
87main:
88
89 add %g0, 0x1, tmp3
90 set ITERATIONS, counter_reg
91 mov %g0, my_id_reg
92
93th_fork(th_main,%l0)
94
95th_main_0:
96 add my_id_reg, 0x00, my_id_reg ! ID address
97 ba go; nop
98th_main_1:
99 add my_id_reg, 0x04, my_id_reg
100 ba go; nop
101th_main_2:
102 add my_id_reg, 0x08, my_id_reg
103 ba go; nop
104th_main_3:
105 add my_id_reg, 0x0c, my_id_reg
106 ba go; nop
107th_main_4:
108 add my_id_reg, 0x10, my_id_reg
109 ba go; nop
110th_main_5:
111 add my_id_reg, 0x14, my_id_reg
112 ba go; nop
113th_main_6:
114 add my_id_reg, 0x18, my_id_reg
115 ba go; nop
116th_main_7:
117 add my_id_reg, 0x1c, my_id_reg
118 ba go; nop
119th_main_8:
120 add my_id_reg, 0x20, my_id_reg
121 ba go; nop
122th_main_9:
123 add my_id_reg, 0x24, my_id_reg
124 ba go; nop
125th_main_10:
126 add my_id_reg, 0x28, my_id_reg
127 ba go; nop
128th_main_11:
129 add my_id_reg, 0x2c, my_id_reg
130 ba go; nop
131th_main_12:
132 add my_id_reg, 0x30, my_id_reg
133 ba go; nop
134th_main_13:
135 add my_id_reg, 0x34, my_id_reg
136 ba go; nop
137th_main_14:
138 add my_id_reg, 0x38, my_id_reg
139 ba go; nop
140th_main_15:
141 add my_id_reg, 0x3c, my_id_reg
142 ba go; nop
143th_main_16:
144 add my_id_reg, 0x40, my_id_reg
145 ba go; nop
146th_main_17:
147 add my_id_reg, 0x44, my_id_reg
148 ba go; nop
149th_main_18:
150 add my_id_reg, 0x48, my_id_reg
151 ba go; nop
152th_main_19:
153 add my_id_reg, 0x4c, my_id_reg
154 ba go; nop
155th_main_20:
156 add my_id_reg, 0x50, my_id_reg
157 ba go; nop
158th_main_21:
159 add my_id_reg, 0x54, my_id_reg
160 ba go; nop
161th_main_22:
162 add my_id_reg, 0x58, my_id_reg
163 ba go; nop
164th_main_23:
165 add my_id_reg, 0x5c, my_id_reg
166 ba go; nop
167th_main_24:
168 add my_id_reg, 0x60, my_id_reg
169 ba go; nop
170th_main_25:
171 add my_id_reg, 0x64, my_id_reg
172 ba go; nop
173th_main_26:
174 add my_id_reg, 0x68, my_id_reg
175 ba go; nop
176th_main_27:
177 add my_id_reg, 0x6c, my_id_reg
178 ba go; nop
179th_main_28:
180 add my_id_reg, 0x70, my_id_reg
181 ba go; nop
182th_main_29:
183 add my_id_reg, 0x74, my_id_reg
184 ba go; nop
185th_main_30:
186 add my_id_reg, 0x78, my_id_reg
187 ba go; nop
188th_main_31:
189 add my_id_reg, 0x7c, my_id_reg
190 ba go; nop
191
192go:
193 setx protected_area, %l0, data_base_reg1 ! the data area
194 setx protected_area2,%l0, data_base_reg2 ! the data area2
195
196loop:
197 ld [data_base_reg1], test_reg ! read the data area
198#ifdef EVICT4
199 ld [data_base_reg1 + 0x10], test_reg ! read the data area
200 ld [data_base_reg1 + 0x20], test_reg ! read the data area
201 ld [data_base_reg1 + 0x30], test_reg ! read the data area
202#endif
203#ifdef EVICT3
204 ld [data_base_reg1 + 0x20], test_reg ! read the data area
205 ld [data_base_reg1 + 0x30], test_reg ! read the data area
206#endif
207#ifdef EVICT2
208 ld [data_base_reg1 + 0x30], test_reg ! read the data area
209#endif
210
211 set barrier_code,%i0
212 jmpl %i0,%o7
213 nop
214
215 brz my_id_reg, evict
216 nop
217goon:
218 dec counter_reg
219 brz counter_reg, good_end
220 nop
221 ba loop
222 nop
223
224evict:
225 ba goon
226 ld [data_base_reg2], test_reg ! read the data area2
227
228barrier_code:
229 setx barrier_data, tmp1, tmp2
230 mov my_id_reg, tmp1
231bloop1:
232 swap [tmp2], tmp3
233 brnz tmp3, bloop1
234#ifdef PREFETCH
235 prefetch [tmp2], #n_reads
236#else
237 nop
238#endif
239
240 ld [tmp2 + 4], tmp3
241 inc tmp3
242 st tmp3, [tmp2 + 4]
243
244 st %g0, [tmp2] ! unlock
245
246bloop2:
247 ld [tmp2 + 4], tmp3
248 brz tmp3, bout2 ! somebody already reset the barrier
249 sub tmp3, THREAD_COUNT, tmp3 ! subtract THREAD_COUNT
250 brnz tmp3, bloop2 ! wait if 0 we are out. Otherwise loop more.
251#ifdef PREFETCH
252 prefetch [tmp2], #n_reads
253#else
254 nop
255#endif
256
257 st %g0, [tmp2 + 4] ! clear the barrier counter
258bout2:
259 jmpl %o7+8, %g0 ! return
260 nop
261
262good_end:
263 ta T_GOOD_TRAP
264bad_end:
265 ta T_BAD_TRAP
266
267!==========================
268
269 .data
270.global protected_area
271protected_area:
272 .word 0xbee1
273 .skip 0x1000
274 .word 0xbee1
275
276SECTION .DATA2 DATA_VA=0x960000
277
278attr_data {
279 Name = .DATA2,
280 VA=DATA2_BASE_DATA_ADDR,
281 RA=DATA2_BASE_DATA_ADDR_RA,
282 PA=ra2pa(DATA2_BASE_DATA_ADDR_RA,0),
283part_0_ctx_nonzero_tsb_config_0,
284 TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
285 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
286 TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
287 }
288
289.data
290.global protected_area2
291protected_area2:
292 .word 0xbee2
293 .skip 0x400
294.global barrier_data
295barrier_data:
296 .word 0x0
297 .word 0x0
298
299
300
Full OpenSPARC design & verification tarball including full HDL.