[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_self_mod2.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: tso_n1_self_mod2.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_BASE_DATA_ADDR     0x160000
#define MAIN_BASE_TEXT_ADDR     0x150000
#define MAIN_BASE_DATA_ADDR_RA   0x100160000
#define MAIN_BASE_TEXT_ADDR_RA   0x100150000

#define USER_PAGE_CUSTOM_MAP
#include "hboot.s"

SECTION .MAIN  TEXT_VA=0x150000, DATA_VA=0x160000

attr_text {
        Name = .MAIN,
        VA=MAIN_BASE_TEXT_ADDR,
        RA=MAIN_BASE_TEXT_ADDR_RA,
        PA=ra2pa(MAIN_BASE_TEXT_ADDR_RA,0),
        part_0_ctx_nonzero_tsb_config_0,
        TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_EP=1, TTE_P=0, TTE_W=1
        }
attr_data {
        Name = .MAIN,
        VA=MAIN_BASE_DATA_ADDR,
        RA=MAIN_BASE_DATA_ADDR_RA,
        PA=ra2pa(MAIN_BASE_DATA_ADDR_RA,0),
        part_0_ctx_nonzero_tsb_config_0,
        TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
        }

.text
.global main

main:	clr	%l0

       add     %g0, 0x20, %i3	! loop counter

main_loop:
	clr	%l1
execute1:
	set	main1,%i0
	jmpl	%i0,%o7
        nop 
	add	%l1, %l0, %l1
        nop
        nop

modify1:
	set	main2,%i0   	!get some known data into the store reg.
	set	main1,%i1  	!change the data at main1
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush	%i1 		!update the I$ to be consistent with the E$

execute2:
        set     main1,%i0
        jmpl    %i0,%o7   	!the jump causes a new cache line to be
        nop             	!loaded into the ecache and the icache.
	add	%l1, %l0, %l1
        nop
        nop

modify2:
	set	main3,%i0    	!get some known data into the store reg.
	set	main1,%i1       !change the data at main1
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush	%i1 		!update the I$ to be consistent with the E$

execute3:
        set     main1,%i0
        jmpl    %i0,%o7  	!the jump causes a new cache line to be
        nop             	!loaded into the ecache and the icache.
	add	%l1, %l0, %l1
        nop
        nop

modify3:
	set	main4,%i0   	!get some known data into the store reg.
	set	main1,%i1     	!change the data at main1
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush	%i1 		!update the I$ to be consistent with the E$

execute4:
        set     main1,%i0
        jmpl    %i0,%o7          !the jump causes a new cache line to be
        nop                      !loaded into the ecache and the icache.
	add	%l1, %l0, %l1
        nop
        nop

modify4:
	set	main5,%i0    	!get some known data into the store reg.
	set	main1,%i1   	!change the data at main1
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush	%i1 		!update the I$ to be consistent with the E$

execute5:
        set     main1,%i0
        jmpl    %i0,%o7       	!the jump causes a new cache line to be
        nop               	!loaded into the ecache and the icache.
	add	%l1, %l0, %l1
        nop
        nop

	set	15, %i0
	subcc	%i0, %l1, %i0
	bnz	bad_end
	nop

modify5:
	set	main6,%i0    	!get some known data into the store reg.
	set	main1,%i1    	!change the data at main1
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush   %i1     	!update the I$ to be consistent with the E$

        dec %i3			! loop
        brnz %i3, main_loop
        nop

normal_end:
        ta      T_GOOD_TRAP
bad_end:
        ta      T_BAD_TRAP


user_text_end:

! the point of these next two pages is to have text pages that
! can be written and read
! The first page holds 2 cache lines worth, the second page has 1 cache line.

ALIGN_PAGE_8K
user_text2_start:

main1:
        mov     1,%l0           ! Replaced with copied_code second pass
	jmpl	%o7+8, %g0
	nop
main2:
	mov	2,%l0
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
main3:
	mov	3,%l0
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop

main4:
	mov	4,%l0
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
main5:
	mov	5,%l0
        nop
        nop
        nop
        nop
        nop

main6:
	mov	1,%l0
        nop
        nop
        nop
        nop
        nop
user_text2_end:

/***********************************************************************
   Test case data start
 ***********************************************************************/
.data

user_data_start:
	.word 0x0
user_data_end:
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: tso_n1_self_mod2.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_BASE_DATA_ADDR 0x160000
	39	#define MAIN_BASE_TEXT_ADDR 0x150000
	40	#define MAIN_BASE_DATA_ADDR_RA 0x100160000
	41	#define MAIN_BASE_TEXT_ADDR_RA 0x100150000
	42
	43	#define USER_PAGE_CUSTOM_MAP
	44	#include "hboot.s"
	45
	46	SECTION .MAIN TEXT_VA=0x150000, DATA_VA=0x160000
	47
	48	attr_text {
	49	Name = .MAIN,
	50	VA=MAIN_BASE_TEXT_ADDR,
	51	RA=MAIN_BASE_TEXT_ADDR_RA,
	52	PA=ra2pa(MAIN_BASE_TEXT_ADDR_RA,0),
	53	part_0_ctx_nonzero_tsb_config_0,
	54	TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
	55	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
	56	TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_EP=1, TTE_P=0, TTE_W=1
	57	}
	58	attr_data {
	59	Name = .MAIN,
	60	VA=MAIN_BASE_DATA_ADDR,
	61	RA=MAIN_BASE_DATA_ADDR_RA,
	62	PA=ra2pa(MAIN_BASE_DATA_ADDR_RA,0),
	63	part_0_ctx_nonzero_tsb_config_0,
	64	TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
65	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
66	TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
67	}
68
69	.text
70	.global main
71
72	main: clr %l0
73
74	add %g0, 0x20, %i3 ! loop counter
75
76	main_loop:
77	clr %l1
78	execute1:
79	set main1,%i0
80	jmpl %i0,%o7
81	nop
82	add %l1, %l0, %l1
83	nop
84	nop
85
86	modify1:
87	set main2,%i0 !get some known data into the store reg.
88	set main1,%i1 !change the data at main1
89	ld [%i0],%l0
90	st %l0,[%i1]
91	flush %i1 !update the I$ to be consistent with the E$
92
93	execute2:
94	set main1,%i0
95	jmpl %i0,%o7 !the jump causes a new cache line to be
96	nop !loaded into the ecache and the icache.
97	add %l1, %l0, %l1
98	nop
99	nop
100
101	modify2:
102	set main3,%i0 !get some known data into the store reg.
103	set main1,%i1 !change the data at main1
104	ld [%i0],%l0
105	st %l0,[%i1]
106	flush %i1 !update the I$ to be consistent with the E$
107
108	execute3:
109	set main1,%i0
110	jmpl %i0,%o7 !the jump causes a new cache line to be
111	nop !loaded into the ecache and the icache.
112	add %l1, %l0, %l1
113	nop
114	nop
115
116	modify3:
117	set main4,%i0 !get some known data into the store reg.
118	set main1,%i1 !change the data at main1
119	ld [%i0],%l0
120	st %l0,[%i1]
121	flush %i1 !update the I$ to be consistent with the E$
122
123	execute4:
124	set main1,%i0
125	jmpl %i0,%o7 !the jump causes a new cache line to be
126	nop !loaded into the ecache and the icache.
127	add %l1, %l0, %l1
128	nop
129	nop
130
131	modify4:
132	set main5,%i0 !get some known data into the store reg.
133	set main1,%i1 !change the data at main1
134	ld [%i0],%l0
135	st %l0,[%i1]
136	flush %i1 !update the I$ to be consistent with the E$
137
138	execute5:
139	set main1,%i0
140	jmpl %i0,%o7 !the jump causes a new cache line to be
141	nop !loaded into the ecache and the icache.
142	add %l1, %l0, %l1
143	nop
144	nop
145
146	set 15, %i0
147	subcc %i0, %l1, %i0
148	bnz bad_end
149	nop
150
151	modify5:
152	set main6,%i0 !get some known data into the store reg.
153	set main1,%i1 !change the data at main1
154	ld [%i0],%l0
155	st %l0,[%i1]
156	flush %i1 !update the I$ to be consistent with the E$
157
158	dec %i3 ! loop
159	brnz %i3, main_loop
160	nop
161
162	normal_end:
163	ta T_GOOD_TRAP
164	bad_end:
165	ta T_BAD_TRAP
166
167
168	user_text_end:
169
170	! the point of these next two pages is to have text pages that
171	! can be written and read
172	! The first page holds 2 cache lines worth, the second page has 1 cache line.
173
174	ALIGN_PAGE_8K
175	user_text2_start:
176
177	main1:
178	mov 1,%l0 ! Replaced with copied_code second pass
179	jmpl %o7+8, %g0
180	nop
181	main2:
182	mov 2,%l0
183	nop
184	nop
185	nop
186	nop
187	nop
188	nop
189	nop
190	nop
191	nop
192	main3:
193	mov 3,%l0
194	nop
195	nop
196	nop
197	nop
198	nop
199	nop
200	nop
201	nop
202	nop
203	nop
204	nop
205	nop
206	nop
207	nop
208	nop
209	nop
210	nop
211	nop
212	nop
213
214	main4:
215	mov 4,%l0
216	nop
217	nop
218	nop
219	nop
220	nop
221	nop
222	nop
223	nop
224	main5:
225	mov 5,%l0
226	nop
227	nop
228	nop
229	nop
230	nop
231
232	main6:
233	mov 1,%l0
234	nop
235	nop
236	nop
237	nop
238	nop
239	user_text2_end:
240
241	/***********************************************************************
242	Test case data start
243	***********************************************************************/
244	.data
245
246	user_data_start:
247	.word 0x0
248	user_data_end: