[OpenSPARC-T2-DV] / verif / diag / assembly / dbp / Debug_Event_Mcu2.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: Debug_Event_Mcu2.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#define  DRAM_ERR_STAT_REG              0x8400000280
#define  L2_ERR_STAT_REG                0xAB00000000

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc000123456700
#define DMA_DATA_BYP_EADDR      0xfffc000123456800

#define ADDR1      		0xfffc00002000aa00
#define TEST_DATA1		0xaaaaaaaaaaaaaaaa
#define  DRAM_ERR_INJ_REG   	0x8400000290

#define ERR_BITS                0x2
#define ERR_BITS_EXPECT         0x8000000000000002

#define DBG_ERR_PA  0x8400000230
#define DBG_ERR_VAL 0x4

/***Following will enable the MCU Debug Events in case of an Error*****/

#define  Soc_Decr_Pa         0x8600000010
#define  Soc_Decr_Val        0x000000000c0000


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop
	  setx Soc_Decr_Pa,%l1,%g4
	  setx Soc_Decr_Val,%l7,%g5
	  stx %g5,[%g4]
	   nop
	   membar #Sync
        nop
	setx DBG_ERR_PA,%l0,%g2
	setx DBG_ERR_VAL,%l2,%g4
	stx %g4,[%g2]
        nop
        nop
	membar #Sync
	clr	%i7
	clr	%o6
	clr	%o7
	clr	%i0

disable_l1:
  	ldxa  [%g0] ASI_LSU_CONTROL, %l0
  	! Remove the lower 2 bits (I-Cache and D-Cache enables)
  	andn  %l0, 0x3, %l0
  	stxa  %l0, [%g0] ASI_LSU_CONTROL

set_DRAM_error_inject_ch0:
	mov   0x606, %l1                ! ECC Mask (2-bit error)
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_SSHOT, %l3
	Or    %l1, %l3, %l1           ! Set single shot ;
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_ENB, %l3
	or    %l1, %l3, %l1           ! Enable error injection for the next write
	setx  DRAM_ERR_INJ_REG, %l3, %g6
	stx   %l1, [%g6]
	membar 0x40

L2_err_enable:
        set     0x3, %l1
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2]
        stx     %l1, [%g2 + 0x40]
        stx     %l1, [%g2 + 0x80]
        stx     %l1, [%g2 + 0xc0]
        stx     %l1, [%g2 + 0x100]
        stx     %l1, [%g2 + 0x140]
        stx     %l1, [%g2 + 0x180]
        stx     %l1, [%g2 + 0x1c0]

set_L2_Directly_Mapped_Mode:
	setx  L2CS_PA0, %l6, %g1
	mov   0x2, %l0
	stx   %l0, [%g1]

store_to_L2_way0:
	setx  TEST_DATA1, %l0, %g5
	setx  0x2000aa00, %l0, %g2  ! bits [21:18] select way
	stx %g5, [%g2]
	membar #Sync

	! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
	setx  0x1000aa00, %l0, %g3 ! bits [21:18] select way
	stx %g5, [%g3]
	membar #Sync

piu_iommu:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

	/*******************************************************
		RDD from DMU
	********************************************************/

dma_rdd:
	nop
UsrEvnt_rdd:
        nop         ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, *, * )

        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

l2_esr:
        mov     0x1, %g1
        sllx    %g1, L2ES_DRU, %g2

        mov     0x1, %g1
        sllx    %g1, L2ES_VEU, %g3

        or      %g2, %g3, %g4

        setx	0x7ffffffff0000000, %g7, %g5
	setx	0x30, %g7, %g6
check_l2_esr:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop
	dec	%g6

	setx	L2_ERR_STAT_REG, %g7, %g1  
	ldx	[%g1], %g2
	andcc	%g2, %g5, %g3			! Donot check L2ESR SYND bits and MEC

	cmp	%g3, %g4
	bne	%xcc, check_l2_esr 
	nop

cause_trap:
	setx	0x2000a000, %g3, %g1
	stx	%g0, [%g1]
	setx	0x800bb00, %g3, %g1
	ldx	[%g1], %g2

	setx	0x8300b000, %g3, %g1
	setx	0x2222222222222222, %g3, %g2	
	stx	%g2, [%g1]	
	setx	 0x6300b000, %g3, %g1	
	ldx	[%g1], %g2

eie_reg_ones_rdd:
        setx    SOC_EIE_REG, %g3, %g2
        setx 	0xffffffffffffffff, %g3, %g1
        stx     %g1, [%g2]
        membar  0x40

	set	0x1, %g1
        setx    0x30, %g7, %g6
err_trap_loop_rdd:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop

	cmp	%g1, %i7
	be	%xcc, check_tt_rdd
	nop

	ba	err_trap_loop_rdd
	nop

check_tt_rdd:
        mov     0x40, %l0
        cmp     %o7, %l0
        bne     %xcc, test_failed
        nop


check_l2_trap_cnt:
	set	0x1, %l0
	cmp	%i0, %l0
	bne	test_failed
	nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, l2_trap 
	nop

check_per_tt40:
	ba	test_failed
	nop


l2_trap:
	nop
	inc	%i0

check_desr_L2Trap_tt40:
        setx    0xb000000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
        nop

check_mcu2_esr_L2Trap_tt40:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_DAU, %l0

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l3

        setx  0xffffffffffff0000, %l2, %l1
        andcc %l1, %l3, %l4                   ! Donot check SYND bits

        sub     %l0, %l4, %i4
        brnz    %i4, test_failed
        nop

clear_mcu_esr_L2Trap_tt40:
        stx     %g0, [%g5]


check_L2_4_ESR_L2Trap_tt40:
        setx  	L2_ERR_STAT_REG, %l3, %g5  
        ldx   	[%g5], %l6

        setx  	0x7ffffffff0000000, %l3, %l0
        andcc 	%l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEU

        mov   	0x1, %l1
        sllx  	%l1, L2ES_DRU, %l0

        mov   	0x1, %l1
        sllx  	%l1, L2ES_VEU, %l2

        or    	%l0, %l2, %i4

        cmp   	%l5, %i4
        bne   	%xcc, test_failed
        nop

clear_l2_esr_L2Trap_tt40:
	stx	%g0, [%g5]

trap_done_tt40:
       	retry 
        nop


My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: Debug_Event_Mcu2.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#define DRAM_ERR_STAT_REG 0x8400000280
	46	#define L2_ERR_STAT_REG 0xAB00000000
	47
	48	#include "err_defines.h"
	49	#include "hboot.s"
	50	#include "peu_defines.h"
	51
	52	#define DMA_DATA_ADDR 0x0000000123456700
	53	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	54	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	55	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	56
	57	#define DMA_DATA_ADDR 0x0000000123456700
	58	#define DMA_DATA_BYP_SADDR 0xfffc000123456700
	59	#define DMA_DATA_BYP_EADDR 0xfffc000123456800
	60
	61	#define ADDR1 0xfffc00002000aa00
	62	#define TEST_DATA1 0xaaaaaaaaaaaaaaaa
	63	#define DRAM_ERR_INJ_REG 0x8400000290
	64
65	#define ERR_BITS 0x2
66	#define ERR_BITS_EXPECT 0x8000000000000002
67
68	#define DBG_ERR_PA 0x8400000230
69	#define DBG_ERR_VAL 0x4
70
71	/*Following will enable the MCU Debug Events in case of an Error***/
72
73	#define Soc_Decr_Pa 0x8600000010
74	#define Soc_Decr_Val 0x000000000c0000
75
76
77
78	/************************************************************************
79	Test case code start
80	************************************************************************/
81	.text
82	.global main
83	.global My_Corrected_ECC_error_trap
84	.global My_Recoverable_Sw_error_trap
85
86	main:
87	ta T_CHANGE_HPRIV
88	nop
89	setx Soc_Decr_Pa,%l1,%g4
90	setx Soc_Decr_Val,%l7,%g5
91	stx %g5,[%g4]
92	nop
93	membar #Sync
94	nop
95	setx DBG_ERR_PA,%l0,%g2
96	setx DBG_ERR_VAL,%l2,%g4
97	stx %g4,[%g2]
98	nop
99	nop
100	membar #Sync
101	clr %i7
102	clr %o6
103	clr %o7
104	clr %i0
105
106	disable_l1:
107	ldxa [%g0] ASI_LSU_CONTROL, %l0
108	! Remove the lower 2 bits (I-Cache and D-Cache enables)
109	andn %l0, 0x3, %l0
110	stxa %l0, [%g0] ASI_LSU_CONTROL
111
112	set_DRAM_error_inject_ch0:
113	mov 0x606, %l1 ! ECC Mask (2-bit error)
114	mov 0x1, %l2
115	sllx %l2, DRAM_EI_SSHOT, %l3
116	Or %l1, %l3, %l1 ! Set single shot ;
117	mov 0x1, %l2
118	sllx %l2, DRAM_EI_ENB, %l3
119	or %l1, %l3, %l1 ! Enable error injection for the next write
120	setx DRAM_ERR_INJ_REG, %l3, %g6
121	stx %l1, [%g6]
122	membar 0x40
123
124	L2_err_enable:
125	set 0x3, %l1
126	mov 0xaa, %g2
127	sllx %g2, 32, %g2
128	stx %l1, [%g2]
129	stx %l1, [%g2 + 0x40]
130	stx %l1, [%g2 + 0x80]
131	stx %l1, [%g2 + 0xc0]
132	stx %l1, [%g2 + 0x100]
133	stx %l1, [%g2 + 0x140]
134	stx %l1, [%g2 + 0x180]
135	stx %l1, [%g2 + 0x1c0]
136
137	set_L2_Directly_Mapped_Mode:
138	setx L2CS_PA0, %l6, %g1
139	mov 0x2, %l0
140	stx %l0, [%g1]
141
142	store_to_L2_way0:
143	setx TEST_DATA1, %l0, %g5
144	setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way
145	stx %g5, [%g2]
146	membar #Sync
147
148	! Storing to same L2 way0 but different tag,this will write to mcu
149	write_mcu_channel_0:
150	setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way
151	stx %g5, [%g3]
152	membar #Sync
153
154	piu_iommu:
155	! enable bypass in IOMMU
156	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
157	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
158	stx %g3, [%g2]
159	ldx [%g2], %g3
160
161	/*******************************************************
162	RDD from DMU
163	********************************************************/
164
165	dma_rdd:
166	nop
167	UsrEvnt_rdd:
168	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, , )
169
170	ldx [%g2], %g3
171	ldx [%g2], %g3
172	ldx [%g2], %g3
173	ldx [%g2], %g3
174
175	l2_esr:
176	mov 0x1, %g1
177	sllx %g1, L2ES_DRU, %g2
178
179	mov 0x1, %g1
180	sllx %g1, L2ES_VEU, %g3
181
182	or %g2, %g3, %g4
183
184	setx 0x7ffffffff0000000, %g7, %g5
185	setx 0x30, %g7, %g6
186	check_l2_esr:
187	cmp %g6, %g0
188	be %xcc, test_failed
189	nop
190	dec %g6
191
192	setx L2_ERR_STAT_REG, %g7, %g1
193	ldx [%g1], %g2
194	andcc %g2, %g5, %g3 ! Donot check L2ESR SYND bits and MEC
195
196	cmp %g3, %g4
197	bne %xcc, check_l2_esr
198	nop
199
200	cause_trap:
201	setx 0x2000a000, %g3, %g1
202	stx %g0, [%g1]
203	setx 0x800bb00, %g3, %g1
204	ldx [%g1], %g2
205
206	setx 0x8300b000, %g3, %g1
207	setx 0x2222222222222222, %g3, %g2
208	stx %g2, [%g1]
209	setx 0x6300b000, %g3, %g1
210	ldx [%g1], %g2
211
212	eie_reg_ones_rdd:
213	setx SOC_EIE_REG, %g3, %g2
214	setx 0xffffffffffffffff, %g3, %g1
215	stx %g1, [%g2]
216	membar 0x40
217
218	set 0x1, %g1
219	setx 0x30, %g7, %g6
220	err_trap_loop_rdd:
221	cmp %g6, %g0
222	be %xcc, test_failed
223	nop
224
225	cmp %g1, %i7
226	be %xcc, check_tt_rdd
227	nop
228
229	ba err_trap_loop_rdd
230	nop
231
232	check_tt_rdd:
233	mov 0x40, %l0
234	cmp %o7, %l0
235	bne %xcc, test_failed
236	nop
237
238
239	check_l2_trap_cnt:
240	set 0x1, %l0
241	cmp %i0, %l0
242	bne test_failed
243	nop
244
245	test_passed:
246	EXIT_GOOD
247
248	test_failed:
249	EXIT_BAD
250
251
252	/************************************************************************
253	RAS
254	Trap Handlers
255	************************************************************************/
256	My_Recoverable_Sw_error_trap:
257	! Signal trap taken
258	setx EXECUTED, %l0, %o6
259	! save trap type value
260	rdpr %tt, %o7
261
262	inc %i7
263
264	check_desr_NcuTrap_tt40:
265	ldxa [%g0]0x4c, %g2
266	nop
267
268	setx 0xb300000000000000, %l0, %g3
269	subcc %g2, %g3, %g4
270	brnz %g4, l2_trap
271	nop
272
273	check_per_tt40:
274	ba test_failed
275	nop
276
277
278	l2_trap:
279	nop
280	inc %i0
281
282	check_desr_L2Trap_tt40:
283	setx 0xb000000000000000, %l0, %g3
284	subcc %g2, %g3, %g4
285	brnz %g4, test_failed
286	nop
287
288	check_mcu2_esr_L2Trap_tt40:
289	mov 0x1, %l1
290	sllx %l1, DRAM_ES_DAU, %l0
291
292	setx DRAM_ERR_STAT_REG, %l3, %g5
293	ldx [%g5], %l3
294
295	setx 0xffffffffffff0000, %l2, %l1
296	andcc %l1, %l3, %l4 ! Donot check SYND bits
297
298	sub %l0, %l4, %i4
299	brnz %i4, test_failed
300	nop
301
302	clear_mcu_esr_L2Trap_tt40:
303	stx %g0, [%g5]
304
305
306	check_L2_4_ESR_L2Trap_tt40:
307	setx L2_ERR_STAT_REG, %l3, %g5
308	ldx [%g5], %l6
309
310	setx 0x7ffffffff0000000, %l3, %l0
311	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU
312
313	mov 0x1, %l1
314	sllx %l1, L2ES_DRU, %l0
315
316	mov 0x1, %l1
317	sllx %l1, L2ES_VEU, %l2
318
319	or %l0, %l2, %i4
320
321	cmp %l5, %i4
322	bne %xcc, test_failed
323	nop
324
325	clear_l2_esr_L2Trap_tt40:
326	stx %g0, [%g5]
327
328	trap_done_tt40:
329	retry
330	nop
331
332
333
334	My_Corrected_ECC_error_trap:
335	ba test_failed
336	nop
337
338
339	/************************************************************************
340	Test case data start
341	************************************************************************/
342
343	SECTION .DATA DATA_VA=DMA_DATA_ADDR
344	attr_data {
345	Name = .DATA,
346	hypervisor,
347	compressimage
348	}
349
350	.data
351	.global PCIAddr9
352	.xword 0x0001020304050607
353	.xword 0x08090a0b0c0d0e0f
354	.xword 0x1011121314151617
355	.xword 0x18191a1b1c1d1e1f
356	.xword 0x2021222324252627
357	.xword 0x28292a2b2c2d2e2f
358	.xword 0x3031323334353637
359	.xword 0x38393a3b3c3d3e3f
360
361	.xword 0x4041424344454647
362	.xword 0x48494a4b4c4d4e4f
363	.xword 0x5051525354555657
364	.xword 0x58595a5b5c5d5e5f
365	.xword 0x6061626364656667
366	.xword 0x68696a6b6c6d6e6f
367	.xword 0x7071727374757677
368	.xword 0x78797a7b7c7d7e7f
369
370	.xword 0x8081828384858687
371	.xword 0x88898a8b8c8d8e8f
372	.xword 0x9091929394959697
373	.xword 0x98999a9b9c9d9e9f
374	.xword 0xa0a1a2a3a4a5a6a7
375	.xword 0xa8a9aaabacadaeaf
376	.xword 0xb0b1b2b3b4b5b6b7
377	.xword 0xb8b9babbbcbdbebf
378
379	.xword 0xc0c1c2c3c4c5c6c7
380	.xword 0xc8c9cacbcccdcecf
381	.xword 0xd0d1d2d3d4d5d6d7
382	.xword 0xd8d9dadbdcdddedf
383	.xword 0xe0e1e2e3e4e5e6e7
384	.xword 0xe8e9eaebecedeeef
385	.xword 0xf0f1f2f3f4f5f6f7
386	.xword 0xf8f9fafbfcfdfeff
387
388	.xword 0x0001020304050607
389	.xword 0x08090a0b0c0d0e0f
390	.xword 0x1011121314151617
391	.xword 0x18191a1b1c1d1e1f
392	.xword 0x2021222324252627
393	.xword 0x28292a2b2c2d2e2f
394	.xword 0x3031323334353637
395	.xword 0x38393a3b3c3d3e3f
396
397	.xword 0x4041424344454647
398	.xword 0x48494a4b4c4d4e4f
399	.xword 0x5051525354555657
400	.xword 0x58595a5b5c5d5e5f
401	.xword 0x6061626364656667
402	.xword 0x68696a6b6c6d6e6f
403	.xword 0x7071727374757677
404	.xword 0x78797a7b7c7d7e7f
405
406	.xword 0x8081828384858687
407	.xword 0x88898a8b8c8d8e8f
408	.xword 0x9091929394959697
409	.xword 0x98999a9b9c9d9e9f
410	.xword 0xa0a1a2a3a4a5a6a7
411	.xword 0xa8a9aaabacadaeaf
412	.xword 0xb0b1b2b3b4b5b6b7
413	.xword 0xb8b9babbbcbdbebf
414
415	.xword 0xc0c1c2c3c4c5c6c7
416	.xword 0xc8c9cacbcccdcecf
417	.xword 0xd0d1d2d3d4d5d6d7
418	.xword 0xd8d9dadbdcdddedf
419	.xword 0xe0e1e2e3e4e5e6e7
420	.xword 0xe8e9eaebecedeeef
421	.xword 0xf0f1f2f3f4f5f6f7
422	.xword 0xf8f9fafbfcfdfeff
423
424	/************************************************************************/
425