[OpenSPARC-T2-DV] / verif / diag / assembly / dbp / Debug_Event_Soc.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: Debug_Event_Soc.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Sw_Recoverable_Error_0x40	 My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO
#define SOC_EST_REG	0x9001041000

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"


#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) | IO_ACCESS_PA)

#define MEM_LOC1 	0x42400000
#define DBG_ERR_PA  0x8000004000
#define DBG_ERR_VAL 0x1
/***following will enable the NCU related errors to trigger a pulse to MIO***/

#define  Soc_Decr_Pa         0x8600000010
#define  Soc_Decr_Val        0x0000300000

/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global	 My_Recoverable_Sw_error_trap


main:
        ta T_CHANGE_HPRIV
        nop

/**following will enable the NCU Debug Trigger Enable Register****/
   setx Soc_Decr_Pa,%l1,%g4
   setx Soc_Decr_Val,%l7,%g5
   stx %g5,[%g4]
   nop
   nop
   membar #Sync

   setx DBG_ERR_PA,%l5,%g3
   setx DBG_ERR_VAL,%l1,%g1
   stx %g1,[%g3]
   nop
   nop
   membar #Sync

get_th_id_o0:
        ta      T_RD_THID

        cmp     %o1, 0x0
        be      main_t0
        nop

        cmp     %o1, 0x1
        be      main_t1
        nop


        /**************************************
                THREAD 0
        **************************************/
main_t0:
	nop
        setx    MEM_LOC1, %g1, %g3
        st      %g0, [%g3]

clear_esr_first:
        setx    SOC_ESR_REG, %l7, %i0
        stx     %g0, [%i0]


set_ejr:
        set     0x1, %i1
        sllx    %i1, ERR_FIELD, %i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]

pio_addr:
        ! select an IO address in PCI address range and transmit the command to NCU
        setx IO_RD_ADDR, %g1, %g2

st_mem1:
        set     0x1, %g4
        st      %g4, [%g3]

pio:
        ! load byte - all byte offsets within an octlet
        ldub [%g2 + 1*8 + 0], %l0
	nop 				! ld hangs and not completes

	ba 	test_failed
	nop


        /**************************************
                THREAD 1
        **************************************/
main_t1:
        nop

read_mem_loc:
        setx    MEM_LOC1, %l7, %i3
	ldx	[%i3], %o0
	cmp	%o0, %g0
	be   	%xcc, read_mem_loc
	nop

delay:
	ld	[%i3+0x8], %o0
        ld     	[%i3+0x10], %o0
        ld     	[%i3+0x18], %o0
        ld     	[%i3+0x20], %o0
        ld      [%i3+0x28], %o0
        ld      [%i3+0x30], %o0
        ld      [%i3+0x40], %o0


        setx    0x8000000000000000, %g7, %g3    !valid bit
        set     0x1, %g2
        sllx    %g2, ERR_FIELD, %g4
        or      %g3, %g4, %g5

	set	0x100, %g1
read_esr:
	cmp	%g1, %g0
        be      %xcc, test_failed	! Timeout check
	nop	 

        setx    SOC_ESR_REG, %g7, %g3
        ldx     [%g3], %g6

	dec	%g1

        cmp     %g6, %g5
        bne      %xcc, read_esr 
        nop


est_reg:
        setx    SOC_EST_REG, %g3, %g2
        set     0x1, %g1
        stx     %g1, [%g2]
        membar  0x40


eie_reg_ones:
	setx	SOC_EIE_REG, %g3, %g2
        set	0x1, %i1
	sllx	%i1, ERR_FIELD, %g1
	stx	%g1, [%g2]
	membar	0x40

	setx	0x40, %g7, %g6
	 set	0x1, %g1			! 1 Trap
err_trap_loop:
	cmp	    %g6, %g0
	 be	%xcc, test_failed
        nop

	cmp	%g1, %i7
	 be	%xcc, check_tt
        nop

	ba	err_trap_loop
        nop

check_tt:
	mov	0x40, %l0
	cmp	%o7,  %l0
	 bne	%xcc, test_failed
        nop

        /********************************/
	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
	! Signal trap taken
	setx	EXECUTED, %l0, %o6
	! save trap type value
	rdpr	%tt, %o7

	inc	%i7

check_desr_tt40:
	ldxa  [%g0]0x4c, %g2
	nop
  	setx	0xb300000000000000, %l0, %g3
	subcc	%g2, %g3, %g4
	brnz	%g4, test_failed 
	nop

check_DSFSR_tt32:
	set	0x18, %g1
	ldxa	[%g1]0x58, %g2
/*
	nop
	set	0x4, %g3
	subcc	%g2, %g3, %g4
	brnz	%g4, test_failed
	nop
*/

check_per_tt40:
	setx	SOC_PER_REG, %l7, %g1
	ldx	[%g1], %g2
	setx	0x8000000000000000, %g7, %g1
	set	0x1, %g3
	sllx	%g3, ERR_FIELD, %g4
	or	%g1, %g4, %g3
	sub	%g2, %g3, %g5
	brnz	%g5, test_failed
	nop

clear_per_tt40:
	setx	SOC_PER_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

clear_ejr_tt40:
	setx	SOC_EJR_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

clear_eie_tt40:
	setx	SOC_EIE_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

trap_done_tt40:
 	done
	nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=IO_RD_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
        .xword 0xdeadbeefdeadbeef

        .xword 0x1101010101010101
        .xword 0x0122010101010101
        .xword 0x0101330101010101
        .xword 0x0101014401010101
        .xword 0x0101010155010101
        .xword 0x0101010101660101
        .xword 0x0101010101017701
        .xword 0x0101010101010188

        .xword 0x1122010101010101
        .xword 0x0101334401010101
        .xword 0x0101010155660101
        .xword 0x0101010101017788

        .xword 0x1122334401010101
        .xword 0x0101010155667788

        .xword 0xdeadbeefdeadbeef

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: Debug_Event_Soc.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	39
	40	#define ENABLE_PCIE_LINK_TRAINING
	41	#define MAIN_PAGE_HV_ALSO
	42	#define SOC_EST_REG 0x9001041000
	43
	44	#include "err_defines.h"
	45	#include "hboot.s"
	46	#include "peu_defines.h"
	47
	48
	49	#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) \| IO_ACCESS_PA)
	50
	51	#define MEM_LOC1 0x42400000
	52	#define DBG_ERR_PA 0x8000004000
	53	#define DBG_ERR_VAL 0x1
	54	/*following will enable the NCU related errors to trigger a pulse to MIO*/
	55
	56	#define Soc_Decr_Pa 0x8600000010
	57	#define Soc_Decr_Val 0x0000300000
	58
	59	/************************************************************************
	60	Test case code start
	61	************************************************************************/
	62	.text
	63	.global main
	64	.global My_Recoverable_Sw_error_trap
65
66
67	main:
68	ta T_CHANGE_HPRIV
69	nop
70
71	/following will enable the NCU Debug Trigger Enable Register**/
72	setx Soc_Decr_Pa,%l1,%g4
73	setx Soc_Decr_Val,%l7,%g5
74	stx %g5,[%g4]
75	nop
76	nop
77	membar #Sync
78
79	setx DBG_ERR_PA,%l5,%g3
80	setx DBG_ERR_VAL,%l1,%g1
81	stx %g1,[%g3]
82	nop
83	nop
84	membar #Sync
85
86	get_th_id_o0:
87	ta T_RD_THID
88
89	cmp %o1, 0x0
90	be main_t0
91	nop
92
93	cmp %o1, 0x1
94	be main_t1
95	nop
96
97
98	/**************************************
99	THREAD 0
100	**************************************/
101	main_t0:
102	nop
103	setx MEM_LOC1, %g1, %g3
104	st %g0, [%g3]
105
106	clear_esr_first:
107	setx SOC_ESR_REG, %l7, %i0
108	stx %g0, [%i0]
109
110
111	set_ejr:
112	set 0x1, %i1
113	sllx %i1, ERR_FIELD, %i2
114	setx SOC_EJR_REG, %l7, %i3
115	stx %i2, [%i3]
116
117	pio_addr:
118	! select an IO address in PCI address range and transmit the command to NCU
119	setx IO_RD_ADDR, %g1, %g2
120
121	st_mem1:
122	set 0x1, %g4
123	st %g4, [%g3]
124
125	pio:
126	! load byte - all byte offsets within an octlet
127	ldub [%g2 + 1*8 + 0], %l0
128	nop ! ld hangs and not completes
129
130	ba test_failed
131	nop
132
133
134
135	/**************************************
136	THREAD 1
137	**************************************/
138	main_t1:
139	nop
140
141	read_mem_loc:
142	setx MEM_LOC1, %l7, %i3
143	ldx [%i3], %o0
144	cmp %o0, %g0
145	be %xcc, read_mem_loc
146	nop
147
148	delay:
149	ld [%i3+0x8], %o0
150	ld [%i3+0x10], %o0
151	ld [%i3+0x18], %o0
152	ld [%i3+0x20], %o0
153	ld [%i3+0x28], %o0
154	ld [%i3+0x30], %o0
155	ld [%i3+0x40], %o0
156
157
158	setx 0x8000000000000000, %g7, %g3 !valid bit
159	set 0x1, %g2
160	sllx %g2, ERR_FIELD, %g4
161	or %g3, %g4, %g5
162
163	set 0x100, %g1
164	read_esr:
165	cmp %g1, %g0
166	be %xcc, test_failed ! Timeout check
167	nop
168
169	setx SOC_ESR_REG, %g7, %g3
170	ldx [%g3], %g6
171
172	dec %g1
173
174	cmp %g6, %g5
175	bne %xcc, read_esr
176	nop
177
178
179	est_reg:
180	setx SOC_EST_REG, %g3, %g2
181	set 0x1, %g1
182	stx %g1, [%g2]
183	membar 0x40
184
185
186	eie_reg_ones:
187	setx SOC_EIE_REG, %g3, %g2
188	set 0x1, %i1
189	sllx %i1, ERR_FIELD, %g1
190	stx %g1, [%g2]
191	membar 0x40
192
193	setx 0x40, %g7, %g6
194	set 0x1, %g1 ! 1 Trap
195	err_trap_loop:
196	cmp %g6, %g0
197	be %xcc, test_failed
198	nop
199
200	cmp %g1, %i7
201	be %xcc, check_tt
202	nop
203
204	ba err_trap_loop
205	nop
206
207	check_tt:
208	mov 0x40, %l0
209	cmp %o7, %l0
210	bne %xcc, test_failed
211	nop
212
213	/********************************/
214
215	test_passed:
216	EXIT_GOOD
217
218	test_failed:
219	EXIT_BAD
220
221
222
223	/************************************************************************
224	RAS
225	Trap Handlers
226	************************************************************************/
227	My_Recoverable_Sw_error_trap:
228	! Signal trap taken
229	setx EXECUTED, %l0, %o6
230	! save trap type value
231	rdpr %tt, %o7
232
233	inc %i7
234
235	check_desr_tt40:
236	ldxa [%g0]0x4c, %g2
237	nop
238	setx 0xb300000000000000, %l0, %g3
239	subcc %g2, %g3, %g4
240	brnz %g4, test_failed
241	nop
242
243	check_DSFSR_tt32:
244	set 0x18, %g1
245	ldxa [%g1]0x58, %g2
246	/*
247	nop
248	set 0x4, %g3
249	subcc %g2, %g3, %g4
250	brnz %g4, test_failed
251	nop
252	*/
253
254	check_per_tt40:
255	setx SOC_PER_REG, %l7, %g1
256	ldx [%g1], %g2
257	setx 0x8000000000000000, %g7, %g1
258	set 0x1, %g3
259	sllx %g3, ERR_FIELD, %g4
260	or %g1, %g4, %g3
261	sub %g2, %g3, %g5
262	brnz %g5, test_failed
263	nop
264
265	clear_per_tt40:
266	setx SOC_PER_REG, %l7, %g1
267	stx %g0, [%g1]
268	nop
269
270	clear_ejr_tt40:
271	setx SOC_EJR_REG, %l7, %g1
272	stx %g0, [%g1]
273	nop
274
275	clear_eie_tt40:
276	setx SOC_EIE_REG, %l7, %g1
277	stx %g0, [%g1]
278	nop
279
280	trap_done_tt40:
281	done
282	nop
283
284
285	/************************************************************************
286	Test case data start
287	************************************************************************/
288
289	SECTION .DATA DATA_VA=IO_RD_ADDR
290	attr_data {
291	Name = .DATA,
292	hypervisor,
293	compressimage
294	}
295
296	.data
297	.xword 0xdeadbeefdeadbeef
298
299	.xword 0x1101010101010101
300	.xword 0x0122010101010101
301	.xword 0x0101330101010101
302	.xword 0x0101014401010101
303	.xword 0x0101010155010101
304	.xword 0x0101010101660101
305	.xword 0x0101010101017701
306	.xword 0x0101010101010188
307
308	.xword 0x1122010101010101
309	.xword 0x0101334401010101
310	.xword 0x0101010155660101
311	.xword 0x0101010101017788
312
313	.xword 0x1122334401010101
314	.xword 0x0101010155667788
315
316	.xword 0xdeadbeefdeadbeef
317
318	/************************************************************************/