Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / dbp / Debug_Niu_Mode.s
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: Debug_Niu_Mode.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41#define DBG_CONFIG_PA 0x8600000000
42#define DBG_CONFIG_VAL 0x8000000000000309
43
44#define DBG_NIU_PA 0x8100180b90
45#define DBG_NIU_VAL 0x7800000000000000
46
47
48#define DBG_TRAIN_PA 0x8100180b98
49#define DBG_TRAIN_VAL 0xaa55aa55aa55aa55
50
51#define Soc_Decr_Pa 0x8600000010
52
53
54#define L2_ERR_STAT_REG 0xAB00000000
55#define L2_ERR_ADDR_REG 0xAC00000000
56
57#define TEST_DATA0 0x1000100081c3e008
58#define TEST_DATA1 0x2000200081c3e008
59#define TEST_DATA2 0x3000300081c3e008
60#define L2_ES_W1C_VALUE 0xc03ffff800000000
61#define DRAM_ES_W1C_VALUE 0xfe00000000000000
62
63#ifdef MCU0
64#define L2_BANK_ADDR 0x40
65#define MCU_BANK_ADDR 0x40
66#define DRAM_ERR_INJ_REG 0x8400000290
67#define DRAM_ERR_STAT_REG 0x8400000280
68#define ERROR_ADDR 0x20200000
69#define DBG_ERR_PA 0xAA00000040
70#define DBG_ERR_VAL 0x4
71#define Soc_Decr_Val 0x00000000000030
72#define L2_Addr_Mask_Reg 0xAF00000040
73#define L2_Addr_Mask_Val 0x000000002200aa00
74#define L2_Addr_Cmp_Reg 0xBF00000040
75#define L2_Addr_Cmp_Val 0x000000002200aa00
76#endif
77
78#ifdef MCU1
79#define L2_BANK_ADDR 0xc0
80#define MCU_BANK_ADDR 0xc0
81#define DRAM_ERR_INJ_REG 0x8400001290
82#define DRAM_ERR_STAT_REG 0x8400001280
83#define DBG_ERR_PA 0xAA000000c0
84#define DBG_ERR_VAL 0x4
85#define Soc_Decr_Val 0x00000000003000
86#define L2_Addr_Mask_Reg 0xAF000000c0
87#define L2_Addr_Mask_Val 0x000000002200aa00
88#define L2_Addr_Cmp_Reg 0xBF000000c0
89#define L2_Addr_Cmp_Val 0x000000002200aa00
90
91#endif
92
93#ifdef MCU2
94#define L2_BANK_ADDR 0x140
95#define MCU_BANK_ADDR 0x140
96#define DRAM_ERR_INJ_REG 0x8400002290
97#define DRAM_ERR_STAT_REG 0x8400002280
98#define ERROR_ADDR 0x20200140
99#define DBG_ERR_PA 0xAA00000140
100#define DBG_ERR_VAL 0x4
101#define Soc_Decr_Val 0x00000000300000
102#define L2_Addr_Mask_Reg 0xAF00000140
103#define L2_Addr_Mask_Val 0x000000002200aa00
104#define L2_Addr_Cmp_Reg 0xBF00000140
105#define L2_Addr_Cmp_Val 0x000000002200aa00
106#endif
107
108#ifdef MCU3
109#define L2_BANK_ADDR 0x1c0
110#define MCU_BANK_ADDR 0x1c0
111#define DRAM_ERR_INJ_REG 0x8400003290
112#define DRAM_ERR_STAT_REG 0x8400003280
113#define DBG_ERR_PA 0xAA000001c0
114#define DBG_ERR_VAL 0x4
115#define Soc_Decr_Val 0x00000030000000
116#define L2_Addr_Mask_Reg 0xAF000001c0
117#define L2_Addr_Mask_Val 0x000000002200aa00
118#define L2_Addr_Cmp_Reg 0xBF000001c0
119#define L2_Addr_Cmp_Val 0x000000002200aa00
120#endif
121
122
123#include "hboot.s"
124#include "asi_s.h"
125#include "err_defines.h"
126
127
128.text
129.global main
130.global My_Corrected_ECC_error_trap
131
132
133
134main:
135 ta T_CHANGE_HPRIV
136
137 nop
138 setx DBG_NIU_PA,%g1,%g2
139 setx DBG_NIU_VAL,%g3,%g4
140 stx %g4,[%g2]
141 membar #Sync
142 setx DBG_TRAIN_PA,%g1,%g2
143 setx DBG_TRAIN_VAL,%g3,%g4
144 stx %g4,[%g2]
145 membar #Sync
146 setx DBG_CONFIG_PA,%g1,%g2
147 setx DBG_CONFIG_VAL,%g3,%g4
148 stx %g4,[%g2]
149 membar #Sync
150
151
152
153
154
155setup_soc_decr_reg:
156 setx L2_Addr_Mask_Reg,%l1,%l4
157 add %l4,L2_BANK_ADDR,%l4
158 setx L2_Addr_Mask_Val,%l2,%l3
159 add %l3,L2_BANK_ADDR,%l3
160 stx %l3,[%l4]
161 nop
162 membar 0x40
163
164 setx L2_Addr_Cmp_Reg,%l4,%l5
165 add %l5,L2_BANK_ADDR,%l5
166 setx L2_Addr_Cmp_Val,%g5,%g4
167 add %g4,L2_BANK_ADDR,%g4
168 stx %g4,[%l5]
169 nop
170 membar 0x40
171
172 nop
173 setx Soc_Decr_Pa,%l1,%g4
174 setx Soc_Decr_Val,%l7,%g5
175 stx %g5,[%g4]
176 nop
177 membar 0x40
178
179
180disable_l1:
181 ldxa [%g0] ASI_LSU_CONTROL, %l0
182 ! Remove the lower 2 bits (I-Cache and D-Cache enables)
183 andn %l0, 0x3, %l0
184 stxa %l0, [%g0] ASI_LSU_CONTROL
185
186
187clear_dram_esr_0:
188 ! Clear DRAM Error status register (Bit[63:57] write-1-clear)
189 setx DRAM_ES_W1C_VALUE, %l0, %l5
190 setx DRAM_ERR_STAT_REG, %l3, %g5
191! add %g5, MCU_BANK_ADDR, %g5
192 stx %l5, [%g5]
193
194set_DRAM_error_inject_ch0:
195 mov 0x606, %l1 ! ECC Mask (Multi-bit error)
196 mov 0x1, %l2
197 sllx %l2, DRAM_EI_SSHOT, %l3
198 Or %l1, %l3, %l1 ! Set single shot ;
199 mov 0x1, %l2
200 sllx %l2, DRAM_EI_ENB, %l3
201 or %l1, %l3, %l1 ! Enable error injection for the next write
202 setx DRAM_ERR_INJ_REG, %l3, %g6
203! add %g6, MCU_BANK_ADDR, %g6
204 stx %l1, [%g6]
205 membar 0x40
206
207enable_err_reporting:
208 setx L2EE_PA0, %l0, %l1
209 add %l1, L2_BANK_ADDR, %l1
210 ldx [%l1], %l2
211 mov 0x3, %l0
212 or %l2, %l0, %l2
213 stx %l2, [%l1]
214
215
216 ! Write 1 to clear L2 Error status registers
217clear_l2_ESR:
218 setx L2ES_PA0, %l3, %l4
219 add %l4, L2_BANK_ADDR, %l4
220 stx %l5, [%l4]
221 nop
222
223set_L2_Off_Mode:
224 setx L2CS_PA0, %l6, %g1
225 add %g1, L2_BANK_ADDR, %g1
226 mov 0x1, %l0
227 stx %l0, [%g1]
228
229
230store_to_L2_way0:
231 setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way
232 add %g2, L2_BANK_ADDR, %g2
233 stx %g5, [%g2]
234 membar #Sync
235read_error_address_ch0:
236 ldx [%g2], %l1
237 membar #Sync
238
239
240! Storing to same L2 way0 but different tag,this will write to mcu
241write_mcu_channel_0:
242 setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way
243 add %g3, L2_BANK_ADDR, %g3
244 stx %g5, [%g3]
245 membar #Sync
246
247/**
248*read_error_address_ch0:
249* ldx [%g2], %l1
250* membar #Sync
251*! ldx [%g3], %l2
252*! membar #Sync
253**/
254
255
256check_DRAM_ESR_0:
257 setx DRAM_ERR_STAT_REG, %l3, %g5
258! add %g5, MCU_BANK_ADDR, %g5
259 ldx [%g5], %l6
260 setx 0xffc0000000000000, %l0,%o2
261 and %l6,%o2,%l6
262
263
264compute_dram_ESR:
265 mov 0x1, %l1
266 sllx %l1, DRAM_ES_DAU, %l0
267
268
269verify_dram_ESR:
270 cmp %l0, %l6
271// bne %xcc, test_fail
272 nop
273
274check_L2_ESR_0:
275 setx L2_ERR_STAT_REG, %l3, %g5
276 add %g5, L2_BANK_ADDR, %g5
277 ldx [%g5], %l6
278
279compute_L2_ESR:
280 setx 0xfffffffff0000000, %l3, %l0
281 andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits
282 mov 0x1, %l1
283 sllx %l1, L2ES_DAU, %l0
284 mov 0x1, %l1
285 sllx %l1, L2ES_VEU, %l2
286 or %l0, %l2, %l3
287
288verify_L2_ESR:
289 cmp %l6, %l3
290 bne %xcc, test_fail
291 nop
292
293
294 setx L2EA_PA0, %l2, %l3
295 add %l3, L2_BANK_ADDR, %l3
296check_l2_EAR:
297 ldx [%l3], %l4
298 ! Error address is the physical address of the cache line (PA[5:0] 0)
299 setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way
300 add %g2, L2_BANK_ADDR, %g2
301
302 setx 0xffffffffc0, %l0,%o2
303 and %l4, %o2, %l4
304 cmp %l4, %g2
305// bne %xcc, test_fail
306 nop
307
308check_Corr_err_trap:
309 ! Check if a Corrected ECC Error Trap happened
310 set EXECUTED, %l0
311 cmp %o0, %l0
312// bne test_fail
313 nop
314 mov TT_Data_Access_Error, %l0
315 cmp %o1, %l0
316// bne test_fail
317 nop
318
319
320 ba test_pass
321 nop
322
323My_Corrected_ECC_error_trap:
324
325!My_Recoverable_Sw_error_trap:
326 ! Signal trap taken
327 setx EXECUTED, %l0, %o0
328 ! save trap type value
329 rdpr %tt, %o1
330 retry
331 nop
332
333
334/*******************************************************
335 * Exit code
336 *******************************************************/
337
338test_pass:
339ta T_GOOD_TRAP
340
341
342test_fail:
343ta T_BAD_TRAP
344
345
346