[OpenSPARC-T2-DV] / verif / diag / assembly / dbp / Debug_Pciex_Mode.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: Debug_Pciex_Mode.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING    
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO
#define DBG_CONFIG_PA 0x8600000000
#define DBG_PCIEX_VAL 0x800000000000000B

#define DBG_PEUA_PA  0x8800683000
#define DBG_PEUA_VAL 0x40
#define DBG_PEUB_PA  0x8800683008
#define DBG_PEUB_VAL 0x40

#define DBG_DMUA_PA  0x8800653000
#define DBG_DMUA_VAL 0x140
#define DBG_DMUB_PA  0x8800653008
#define DBG_DMUB_VAL 0x140

	
#include "hboot.s"
#include "peu_defines.h"

#define MEM64_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM64_OFFSET_BASE_REG_DATA)
#define MEM64_WR_ADDR0 mpeval(MEM64_WR_ADDR + 0x0000000000)
#define MEM64_WR_ADDR1 mpeval(MEM64_WR_ADDR + 0x0100000000)
#define MEM64_WR_ADDR2 mpeval(MEM64_WR_ADDR + 0x0200000000)
#define MEM64_WR_ADDR4 mpeval(MEM64_WR_ADDR + 0x0400000000)
		
#ifndef NO_SELF_CHECK
#define BNE_TEST_FAIL  bne	test_failed
#else
#define BNE_TEST_FAIL  nop
#endif
	
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop
//////
	setx DBG_CONFIG_PA,%g1,%g2
	setx DBG_PCIEX_VAL,%g3,%g4
	stx %g4,[%g2]
	membar #Sync
	setx DBG_PEUA_PA,%g1,%g2
	setx DBG_PEUA_VAL,%g3,%g4
	stx %g4,[%g2]
	membar #Sync
	setx DBG_PEUB_PA,%g1,%g2
	setx DBG_PEUB_VAL,%g3,%g4
	stx %g4,[%g2]
	membar #Sync
	setx DBG_DMUA_PA,%g1,%g2
	setx DBG_DMUA_VAL,%g3,%g4
	stx %g4,[%g2]
	membar #Sync
	setx DBG_DMUB_PA,%g1,%g2
	setx DBG_DMUB_VAL,%g3,%g4
	stx %g4,[%g2]
	membar #Sync


///////	
	! select a Mem address in PCI address range and transmit the command to NCU
	setx	MEM64_WR_ADDR1, %g1, %g2

	! store byte to a few offsets
	setx	0x10, %g1, %l0
	stb	%l0, [%g2 + 0]
	mov     %l0, %l1
	ldub	[%g2 + 0], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop
	
	setx	0x20, %g1, %l0
	stb	%l0, [%g2 + 1]
	mov     %l0, %l1
	ldub	[%g2 + 1], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop
	
	setx	0x30, %g1, %l0
	stb	%l0, [%g2 + 2]
	mov     %l0, %l1
	ldub	[%g2 + 2], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop
	
	setx	0x40, %g1, %l0
	stb	%l0, [%g2 + 3]
	mov     %l0, %l1
	ldub	[%g2 + 3], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	setx	0x50, %g1, %l0
	stb	%l0, [%g2 + 4]
	mov     %l0, %l1
	ldub	[%g2 + 4], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop
	
	setx	0x60, %g1, %l0
	stb	%l0, [%g2 + 5]
	mov     %l0, %l1
	ldub	[%g2 + 5], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop
	
	setx	0x70, %g1, %l0
	stb	%l0, [%g2 + 6]
	mov     %l0, %l1
	ldub	[%g2 + 6], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop
	
	setx	0x80, %g1, %l0
	stb	%l0, [%g2 + 7]
	mov     %l0, %l1
	ldub	[%g2 + 7], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop
	
	! store half-word to a few offsets
	setx	0x9190, %g1, %l0
	sth	%l0, [%g2 + 8]
	mov     %l0, %l1
	lduh	[%g2 + 8], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	setx	0xa1a0, %g1, %l0
	sth	%l0, [%g2 + 10]
	mov     %l0, %l1
	lduh	[%g2 + 10], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	setx	0xb1b0, %g1, %l0
	sth	%l0, [%g2 + 12]
	mov     %l0, %l1
	lduh	[%g2 + 12], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	setx	0xc1c0, %g1, %l0
	sth	%l0, [%g2 + 14]
	mov     %l0, %l1
	lduh	[%g2 + 14], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop
	
	! store word
	setx	0xd3d2d1d0, %g1, %l0
	stw	%l0, [%g2 + 16]
	mov     %l0, %l1
	lduw	[%g2 + 16], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	setx	0xe3e2e1e0, %g1, %l0
	stw	%l0, [%g2 + 20]
	mov     %l0, %l1
	lduw	[%g2 + 20], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	setx	0xf3f2f1f0, %g1, %l0
	stw	%l0, [%g2 + 24]
	mov     %l0, %l1
	lduw	[%g2 + 24], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	setx	0x03020100, %g1, %l0
	stw	%l0, [%g2 + 28]
	mov     %l0, %l1
	lduw	[%g2 + 28], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	! store dword
	setx	0x1716151413121110, %g1, %l0
	stx	%l0, [%g2 + 32]
	mov     %l0, %l1
	ldx	[%g2 + 32], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	setx	0x2726252423222120, %g1, %l0
	stx	%l0, [%g2 + 40]
	mov     %l0, %l1
	ldx	[%g2 + 40], %l0
	cmp	%l0, %l1
	BNE_TEST_FAIL
	nop

	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=MEM64_WR_ADDR1
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
	
data0:	.xword 0x1111111111111111
	.xword 0x2222222222222222
	.xword 0x3333333333333333
	.xword 0x4444444444444444
	.xword 0x5555555555555555
	.xword 0x6666666666666666
	.xword 0x7777777777777777
	.xword 0x8888888888888888

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: Debug_Pciex_Mode.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	40	#define MAIN_PAGE_HV_ALSO
	41	#define DBG_CONFIG_PA 0x8600000000
	42	#define DBG_PCIEX_VAL 0x800000000000000B
	43
	44	#define DBG_PEUA_PA 0x8800683000
	45	#define DBG_PEUA_VAL 0x40
	46	#define DBG_PEUB_PA 0x8800683008
	47	#define DBG_PEUB_VAL 0x40
	48
	49	#define DBG_DMUA_PA 0x8800653000
	50	#define DBG_DMUA_VAL 0x140
	51	#define DBG_DMUB_PA 0x8800653008
	52	#define DBG_DMUB_VAL 0x140
	53
	54
	55	#include "hboot.s"
	56	#include "peu_defines.h"
	57
	58	#define MEM64_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM64_OFFSET_BASE_REG_DATA)
	59	#define MEM64_WR_ADDR0 mpeval(MEM64_WR_ADDR + 0x0000000000)
	60	#define MEM64_WR_ADDR1 mpeval(MEM64_WR_ADDR + 0x0100000000)
	61	#define MEM64_WR_ADDR2 mpeval(MEM64_WR_ADDR + 0x0200000000)
	62	#define MEM64_WR_ADDR4 mpeval(MEM64_WR_ADDR + 0x0400000000)
	63
	64	#ifndef NO_SELF_CHECK
65	#define BNE_TEST_FAIL bne test_failed
66	#else
67	#define BNE_TEST_FAIL nop
68	#endif
69
70	/************************************************************************
71	Test case code start
72	************************************************************************/
73	.text
74	.global main
75
76	main:
77	ta T_CHANGE_HPRIV
78	nop
79	//////
80	setx DBG_CONFIG_PA,%g1,%g2
81	setx DBG_PCIEX_VAL,%g3,%g4
82	stx %g4,[%g2]
83	membar #Sync
84	setx DBG_PEUA_PA,%g1,%g2
85	setx DBG_PEUA_VAL,%g3,%g4
86	stx %g4,[%g2]
87	membar #Sync
88	setx DBG_PEUB_PA,%g1,%g2
89	setx DBG_PEUB_VAL,%g3,%g4
90	stx %g4,[%g2]
91	membar #Sync
92	setx DBG_DMUA_PA,%g1,%g2
93	setx DBG_DMUA_VAL,%g3,%g4
94	stx %g4,[%g2]
95	membar #Sync
96	setx DBG_DMUB_PA,%g1,%g2
97	setx DBG_DMUB_VAL,%g3,%g4
98	stx %g4,[%g2]
99	membar #Sync
100
101
102
103
104
105	///////
106	! select a Mem address in PCI address range and transmit the command to NCU
107	setx MEM64_WR_ADDR1, %g1, %g2
108
109	! store byte to a few offsets
110	setx 0x10, %g1, %l0
111	stb %l0, [%g2 + 0]
112	mov %l0, %l1
113	ldub [%g2 + 0], %l0
114	cmp %l0, %l1
115	BNE_TEST_FAIL
116	nop
117
118	setx 0x20, %g1, %l0
119	stb %l0, [%g2 + 1]
120	mov %l0, %l1
121	ldub [%g2 + 1], %l0
122	cmp %l0, %l1
123	BNE_TEST_FAIL
124	nop
125
126	setx 0x30, %g1, %l0
127	stb %l0, [%g2 + 2]
128	mov %l0, %l1
129	ldub [%g2 + 2], %l0
130	cmp %l0, %l1
131	BNE_TEST_FAIL
132	nop
133
134	setx 0x40, %g1, %l0
135	stb %l0, [%g2 + 3]
136	mov %l0, %l1
137	ldub [%g2 + 3], %l0
138	cmp %l0, %l1
139	BNE_TEST_FAIL
140	nop
141
142	setx 0x50, %g1, %l0
143	stb %l0, [%g2 + 4]
144	mov %l0, %l1
145	ldub [%g2 + 4], %l0
146	cmp %l0, %l1
147	BNE_TEST_FAIL
148	nop
149
150	setx 0x60, %g1, %l0
151	stb %l0, [%g2 + 5]
152	mov %l0, %l1
153	ldub [%g2 + 5], %l0
154	cmp %l0, %l1
155	BNE_TEST_FAIL
156	nop
157
158	setx 0x70, %g1, %l0
159	stb %l0, [%g2 + 6]
160	mov %l0, %l1
161	ldub [%g2 + 6], %l0
162	cmp %l0, %l1
163	BNE_TEST_FAIL
164	nop
165
166	setx 0x80, %g1, %l0
167	stb %l0, [%g2 + 7]
168	mov %l0, %l1
169	ldub [%g2 + 7], %l0
170	cmp %l0, %l1
171	BNE_TEST_FAIL
172	nop
173
174	! store half-word to a few offsets
175	setx 0x9190, %g1, %l0
176	sth %l0, [%g2 + 8]
177	mov %l0, %l1
178	lduh [%g2 + 8], %l0
179	cmp %l0, %l1
180	BNE_TEST_FAIL
181	nop
182
183	setx 0xa1a0, %g1, %l0
184	sth %l0, [%g2 + 10]
185	mov %l0, %l1
186	lduh [%g2 + 10], %l0
187	cmp %l0, %l1
188	BNE_TEST_FAIL
189	nop
190
191	setx 0xb1b0, %g1, %l0
192	sth %l0, [%g2 + 12]
193	mov %l0, %l1
194	lduh [%g2 + 12], %l0
195	cmp %l0, %l1
196	BNE_TEST_FAIL
197	nop
198
199	setx 0xc1c0, %g1, %l0
200	sth %l0, [%g2 + 14]
201	mov %l0, %l1
202	lduh [%g2 + 14], %l0
203	cmp %l0, %l1
204	BNE_TEST_FAIL
205	nop
206
207	! store word
208	setx 0xd3d2d1d0, %g1, %l0
209	stw %l0, [%g2 + 16]
210	mov %l0, %l1
211	lduw [%g2 + 16], %l0
212	cmp %l0, %l1
213	BNE_TEST_FAIL
214	nop
215
216	setx 0xe3e2e1e0, %g1, %l0
217	stw %l0, [%g2 + 20]
218	mov %l0, %l1
219	lduw [%g2 + 20], %l0
220	cmp %l0, %l1
221	BNE_TEST_FAIL
222	nop
223
224	setx 0xf3f2f1f0, %g1, %l0
225	stw %l0, [%g2 + 24]
226	mov %l0, %l1
227	lduw [%g2 + 24], %l0
228	cmp %l0, %l1
229	BNE_TEST_FAIL
230	nop
231
232	setx 0x03020100, %g1, %l0
233	stw %l0, [%g2 + 28]
234	mov %l0, %l1
235	lduw [%g2 + 28], %l0
236	cmp %l0, %l1
237	BNE_TEST_FAIL
238	nop
239
240	! store dword
241	setx 0x1716151413121110, %g1, %l0
242	stx %l0, [%g2 + 32]
243	mov %l0, %l1
244	ldx [%g2 + 32], %l0
245	cmp %l0, %l1
246	BNE_TEST_FAIL
247	nop
248
249	setx 0x2726252423222120, %g1, %l0
250	stx %l0, [%g2 + 40]
251	mov %l0, %l1
252	ldx [%g2 + 40], %l0
253	cmp %l0, %l1
254	BNE_TEST_FAIL
255	nop
256
257
258	test_passed:
259	EXIT_GOOD
260
261	test_failed:
262	EXIT_BAD
263
264
265	/************************************************************************
266	Test case data start
267	************************************************************************/
268
269	SECTION .DATA DATA_VA=MEM64_WR_ADDR1
270	attr_data {
271	Name = .DATA,
272	hypervisor,
273	compressimage
274	}
275
276	.data
277	.global PCIAddr9
278
279	data0: .xword 0x1111111111111111
280	.xword 0x2222222222222222
281	.xword 0x3333333333333333
282	.xword 0x4444444444444444
283	.xword 0x5555555555555555
284	.xword 0x6666666666666666
285	.xword 0x7777777777777777
286	.xword 0x8888888888888888
287
288	/************************************************************************/
289