Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / debug / checkp / my_console.s
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: my_console.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38uart_init:
39 /*
40 * Supports only 16550 UART
41 *
42 * %g1 is UART base address
43 * %g2,%g3 clobbered
44 * %g7 return address
45 */
46 ldub [%g1 + LSR_ADDR], %g2 ! read LSR
47 stb %g0, [%g1 + IER_ADDR] ! clear IER
48 stb %g0, [%g1 + FCR_ADDR] ! clear FCR, disable FIFO
49 mov (FCR_XMIT_RESET | FCR_RCVR_RESET), %g3
50 stb %g3, [%g1 + FCR_ADDR] ! reset FIFOs in FCR
51 mov FCR_FIFO_ENABLE, %g3
52 stb %g3, [%g1 + FCR_ADDR] ! FCR enable FIFO
53 mov (LCR_DLAB | LCR_8N1), %g3
54 stb %g3, [%g1 + LCR_ADDR] ! set LCR for 8-n-1, set DLAB
55 ! DLAB = 1
56 mov DLL_9600, %g3
57 stb %g3, [%g1 + DLL_ADDR] ! set baud rate = 9600
58 stb %g0, [%g1 + DLM_ADDR] ! set MS = 0
59 ! disable DLAB
60 mov LCR_8N1, %g3 ! set LCR for 8-n-1, unset DLAB
61 stb %g3, [%g1 + LCR_ADDR] ! set LCR for 8-n-1, unset DLAB
62 jmp %g7 + 4
63 nop
64
65
66puts:
67 setx HV_UART, %g3, %g2
681:
69 ldub [%g2 + LSR_ADDR], %g3
70 btst LSR_THRE, %g3
71 bz 1b
72 nop
73
741:
75 ldub [%g1], %g3
76 cmp %g3, 0
77 inc %g1
78 bne,a,pt %icc, 2f
79 stb %g3, [%g2]
80 jmp %g7 + 4
81 nop
82
832:
84 ldub [%g2 + LSR_ADDR], %g3
85 btst LSR_TEMT, %g3
86 bz 2b
87 nop
88 ba,a 1b
89