[OpenSPARC-T2-DV] / verif / diag / assembly / exu / ffu_fsr_gsr_n2.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: ffu_fsr_gsr_n2.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define FSR_DUMP_P  %g2
#define FSR_DATA_P  %g3
#define NUM_CASES   64

#define  MAIN_PAGE_HV_ALSO  
#define  MAIN_PAGE_NUCLEUS_ALSO

#define ENABLE_T0_Clean_Window_0x24
#define ENABLE_T0_Corrected_ECC_error_0x63 
#define ENABLE_T0_Data_Access_Exception_0x30 
#define ENABLE_T0_Data_access_error_0x32 
#define ENABLE_T0_Division_By_Zero_0x28 
#define ENABLE_T0_Fp_disabled_0x20
#define ENABLE_T0_Fp_exception_ieee_754_0x21 
#define ENABLE_T0_Fp_exception_other_0x22 
#define ENABLE_T0_Illegal_instruction_0x10
#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
#define ENABLE_T0_Instruction_access_error_0x0a 
#define ENABLE_T0_Instruction_access_exception_0x08
#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
#define ENABLE_T0_Mem_Address_Not_Aligned_0x34 
#define ENABLE_T0_Privileged_Action_0x37 
#define ENABLE_T0_Privileged_opcode_0x11
#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
#define ENABLE_T0_Tag_Overflow_0x23 
#define ENABLE_T0_Unimplemented_LDD_0x12
#define ENABLE_T0_Unimplemented_STD_0x13
#define ENABLE_T0_data_access_protection_0x6c 
#define ENABLE_T0_fast_data_access_MMU_miss_0x68
#define ENABLE_T0_fast_instr_access_MMU_miss_0x64
	
#include "hboot.s"

.global main        
main:
th_fork(th_main,%l0)		! start up to four threads.
	! All threads run the same code with different data.
th_main_0:
	setx	fsr_save0,%g7,FSR_DUMP_P
	ba	all_thds
	nop
th_main_1:
	setx	fsr_save1,%g7,FSR_DUMP_P
	ba	all_thds
	nop
th_main_2:
	setx	fsr_save2,%g7,FSR_DUMP_P
	ba	all_thds
	nop    
th_main_3:
	setx	fsr_save3,%g7,FSR_DUMP_P
	ba	all_thds
	nop    

all_thds:       
    	wr      %g0,0x4,%fprs

	!------------------------------
	! test FSR reads and writes
	!------------------------------
	setx	ones_data,%g7,FSR_DATA_P
	setx	fp_data,%g7,%l0
	ldd	[%l0],%f0
	ldd	[%l0+8],%f2
	add	%g0,NUM_CASES,%l1
    
fsr_loop:
	! 32-bit loads and stores
	ld	[FSR_DATA_P],%fsr   ! load followed by store
	st	%fsr,[FSR_DUMP_P]

	fcmpd	%fcc0,%f0,%f2	    ! load must wait for fcmp to finish
	ld	[FSR_DUMP_P],%fsr
	fcmpd	%fcc0,%f2,%f0	    ! store must wait for fcmp to finish
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DATA_P],%fsr   ! store followed by load

    	! 64-bit loads and stores
	ldx	[FSR_DATA_P],%fsr   ! load followed by store
	stx	%fsr,[FSR_DUMP_P]

	fcmpd	%fcc3,%f0,%f2	    ! load must wait for fcmp to finish
	ldx	[FSR_DUMP_P],%fsr
	fcmpd	%fcc1,%f2,%f0	    ! store must wait for fcmp to finish
	stx	%fsr,[FSR_DUMP_P]
	ldx	[FSR_DATA_P],%fsr   ! store followed by load

        ! mixed 32 and 64-bit
	ldx	[FSR_DATA_P],%fsr   ! load followed by store
	stx	%fsr,[FSR_DUMP_P]

	fcmpd	%fcc3,%f0,%f2	    ! load must wait for fcmp to finish
	ld	[FSR_DUMP_P],%fsr
	fcmpd	%fcc0,%f2,%f0	    ! store must wait for fcmp to finish
	stx	%fsr,[FSR_DUMP_P]
	ldx	[FSR_DATA_P],%fsr   ! store followed by load
	fcmpd	%fcc3,%f0,%f0
	fcmpd	%fcc0,%f2,%f2
	st	%fsr,[FSR_DUMP_P]

	sub	%l1,1,%l1
	brnz	%l1,fsr_loop
	add	FSR_DATA_P,8,FSR_DATA_P


	!------------------------------
	! test GSR reads and writes
	!------------------------------
	setx	ones_data,%g7,FSR_DATA_P
	add	%g0,NUM_CASES,%l1
	add	%g0,7,%i0
    
gsr_loop:
	ldx	[FSR_DATA_P],%l2
	alignaddr %i0,%g0,%i1
	wr	%l2,0,%gsr
	alignaddr %i0,%g0,%i1
	rd	%gsr,%l3

    	sub	%l1,1,%l1
	brnz	%l1,gsr_loop
	add	FSR_DATA_P,8,FSR_DATA_P
    
good_end:   
	ta	T_GOOD_TRAP
	nop
	nop    

!==========================    
.data
.align 0x1fff+1

.align 8
fp_data:
	.word   0x3e780000, 0x12345678
	.word   0x3e790000, 0x12345678

.align 8
ones_data:
	.word	0x00000000, 0x00000000
	.word	0x00000000, 0x00000001
	.word	0x00000000, 0x00000002
	.word	0x00000000, 0x00000004
	.word	0x00000000, 0x00000008
	.word	0x00000000, 0x00000010
	.word	0x00000000, 0x00000020
	.word	0x00000000, 0x00000040
	.word	0x00000000, 0x00000080
	.word	0x00000000, 0x00000100
	.word	0x00000000, 0x00000200
	.word	0x00000000, 0x00000400
	.word	0x00000000, 0x00000800
	.word	0x00000000, 0x00001000
	.word	0x00000000, 0x00002000
	.word	0x00000000, 0x00004000
	.word	0x00000000, 0x00008000
	.word	0x00000000, 0x00010000
	.word	0x00000000, 0x00020000
	.word	0x00000000, 0x00040000
	.word	0x00000000, 0x00080000
	.word	0x00000000, 0x00100000
	.word	0x00000000, 0x00200000
	.word	0x00000000, 0x00400000
	.word	0x00000000, 0x00800000
	.word	0x00000000, 0x01000000
	.word	0x00000000, 0x02000000
	.word	0x00000000, 0x04000000
	.word	0x00000000, 0x08000000
	.word	0x00000000, 0x10000000
	.word	0x00000000, 0x20000000
	.word	0x00000000, 0x40000000
	.word	0x00000000, 0x80000000
	.word	0x00000001, 0x00000000
	.word	0x00000002, 0x00000000
	.word	0x00000004, 0x00000000
	.word	0x00000008, 0x00000000
	.word	0x00000010, 0x00000000
	.word	0x00000020, 0x00000000
	.word	0x00000040, 0x00000000
	.word	0x00000080, 0x00000000
	.word	0x00000100, 0x00000000
	.word	0x00000200, 0x00000000
	.word	0x00000400, 0x00000000
	.word	0x00000800, 0x00000000
	.word	0x00001000, 0x00000000
	.word	0x00002000, 0x00000000
	.word	0x00004000, 0x00000000
	.word	0x00008000, 0x00000000
	.word	0x00010000, 0x00000000
	.word	0x00020000, 0x00000000
	.word	0x00040000, 0x00000000
	.word	0x00080000, 0x00000000
	.word	0x00100000, 0x00000000
	.word	0x00200000, 0x00000000
	.word   0x00400000, 0x00000000
	.word	0x00800000, 0x00000000
	.word	0x01000000, 0x00000000
	.word	0x02000000, 0x00000000
	.word	0x04000000, 0x00000000
	.word	0x08000000, 0x00000000
	.word	0x10000000, 0x00000000
	.word	0x20000000, 0x00000000
	.word	0x40000000, 0x00000000
	.word	0x80000000, 0x00000000

fsr_save0:  
	.word	0,0
fsr_save1:  
	.word	0,0    
fsr_save2:  
	.word	0,0    
fsr_save3:  
	.word	0,0


.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: ffu_fsr_gsr_n2.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define FSR_DUMP_P %g2
	39	#define FSR_DATA_P %g3
	40	#define NUM_CASES 64
	41
	42	#define MAIN_PAGE_HV_ALSO
	43	#define MAIN_PAGE_NUCLEUS_ALSO
	44
	45	#define ENABLE_T0_Clean_Window_0x24
	46	#define ENABLE_T0_Corrected_ECC_error_0x63
	47	#define ENABLE_T0_Data_Access_Exception_0x30
	48	#define ENABLE_T0_Data_access_error_0x32
	49	#define ENABLE_T0_Division_By_Zero_0x28
	50	#define ENABLE_T0_Fp_disabled_0x20
	51	#define ENABLE_T0_Fp_exception_ieee_754_0x21
	52	#define ENABLE_T0_Fp_exception_other_0x22
	53	#define ENABLE_T0_Illegal_instruction_0x10
	54	#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
	55	#define ENABLE_T0_Instruction_access_error_0x0a
	56	#define ENABLE_T0_Instruction_access_exception_0x08
	57	#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
	58	#define ENABLE_T0_Mem_Address_Not_Aligned_0x34
	59	#define ENABLE_T0_Privileged_Action_0x37
	60	#define ENABLE_T0_Privileged_opcode_0x11
	61	#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
	62	#define ENABLE_T0_Tag_Overflow_0x23
	63	#define ENABLE_T0_Unimplemented_LDD_0x12
	64	#define ENABLE_T0_Unimplemented_STD_0x13
65	#define ENABLE_T0_data_access_protection_0x6c
66	#define ENABLE_T0_fast_data_access_MMU_miss_0x68
67	#define ENABLE_T0_fast_instr_access_MMU_miss_0x64
68
69	#include "hboot.s"
70
71	.global main
72	main:
73	th_fork(th_main,%l0) ! start up to four threads.
74	! All threads run the same code with different data.
75	th_main_0:
76	setx fsr_save0,%g7,FSR_DUMP_P
77	ba all_thds
78	nop
79	th_main_1:
80	setx fsr_save1,%g7,FSR_DUMP_P
81	ba all_thds
82	nop
83	th_main_2:
84	setx fsr_save2,%g7,FSR_DUMP_P
85	ba all_thds
86	nop
87	th_main_3:
88	setx fsr_save3,%g7,FSR_DUMP_P
89	ba all_thds
90	nop
91
92	all_thds:
93	wr %g0,0x4,%fprs
94
95	!------------------------------
96	! test FSR reads and writes
97	!------------------------------
98	setx ones_data,%g7,FSR_DATA_P
99	setx fp_data,%g7,%l0
100	ldd [%l0],%f0
101	ldd [%l0+8],%f2
102	add %g0,NUM_CASES,%l1
103
104	fsr_loop:
105	! 32-bit loads and stores
106	ld [FSR_DATA_P],%fsr ! load followed by store
107	st %fsr,[FSR_DUMP_P]
108
109	fcmpd %fcc0,%f0,%f2 ! load must wait for fcmp to finish
110	ld [FSR_DUMP_P],%fsr
111	fcmpd %fcc0,%f2,%f0 ! store must wait for fcmp to finish
112	st %fsr,[FSR_DUMP_P]
113	ld [FSR_DATA_P],%fsr ! store followed by load
114
115	! 64-bit loads and stores
116	ldx [FSR_DATA_P],%fsr ! load followed by store
117	stx %fsr,[FSR_DUMP_P]
118
119	fcmpd %fcc3,%f0,%f2 ! load must wait for fcmp to finish
120	ldx [FSR_DUMP_P],%fsr
121	fcmpd %fcc1,%f2,%f0 ! store must wait for fcmp to finish
122	stx %fsr,[FSR_DUMP_P]
123	ldx [FSR_DATA_P],%fsr ! store followed by load
124
125	! mixed 32 and 64-bit
126	ldx [FSR_DATA_P],%fsr ! load followed by store
127	stx %fsr,[FSR_DUMP_P]
128
129	fcmpd %fcc3,%f0,%f2 ! load must wait for fcmp to finish
130	ld [FSR_DUMP_P],%fsr
131	fcmpd %fcc0,%f2,%f0 ! store must wait for fcmp to finish
132	stx %fsr,[FSR_DUMP_P]
133	ldx [FSR_DATA_P],%fsr ! store followed by load
134	fcmpd %fcc3,%f0,%f0
135	fcmpd %fcc0,%f2,%f2
136	st %fsr,[FSR_DUMP_P]
137
138	sub %l1,1,%l1
139	brnz %l1,fsr_loop
140	add FSR_DATA_P,8,FSR_DATA_P
141
142
143	!------------------------------
144	! test GSR reads and writes
145	!------------------------------
146	setx ones_data,%g7,FSR_DATA_P
147	add %g0,NUM_CASES,%l1
148	add %g0,7,%i0
149
150	gsr_loop:
151	ldx [FSR_DATA_P],%l2
152	alignaddr %i0,%g0,%i1
153	wr %l2,0,%gsr
154	alignaddr %i0,%g0,%i1
155	rd %gsr,%l3
156
157	sub %l1,1,%l1
158	brnz %l1,gsr_loop
159	add FSR_DATA_P,8,FSR_DATA_P
160
161	good_end:
162	ta T_GOOD_TRAP
163	nop
164	nop
165
166	!==========================
167	.data
168	.align 0x1fff+1
169
170	.align 8
171	fp_data:
172	.word 0x3e780000, 0x12345678
173	.word 0x3e790000, 0x12345678
174
175	.align 8
176	ones_data:
177	.word 0x00000000, 0x00000000
178	.word 0x00000000, 0x00000001
179	.word 0x00000000, 0x00000002
180	.word 0x00000000, 0x00000004
181	.word 0x00000000, 0x00000008
182	.word 0x00000000, 0x00000010
183	.word 0x00000000, 0x00000020
184	.word 0x00000000, 0x00000040
185	.word 0x00000000, 0x00000080
186	.word 0x00000000, 0x00000100
187	.word 0x00000000, 0x00000200
188	.word 0x00000000, 0x00000400
189	.word 0x00000000, 0x00000800
190	.word 0x00000000, 0x00001000
191	.word 0x00000000, 0x00002000
192	.word 0x00000000, 0x00004000
193	.word 0x00000000, 0x00008000
194	.word 0x00000000, 0x00010000
195	.word 0x00000000, 0x00020000
196	.word 0x00000000, 0x00040000
197	.word 0x00000000, 0x00080000
198	.word 0x00000000, 0x00100000
199	.word 0x00000000, 0x00200000
200	.word 0x00000000, 0x00400000
201	.word 0x00000000, 0x00800000
202	.word 0x00000000, 0x01000000
203	.word 0x00000000, 0x02000000
204	.word 0x00000000, 0x04000000
205	.word 0x00000000, 0x08000000
206	.word 0x00000000, 0x10000000
207	.word 0x00000000, 0x20000000
208	.word 0x00000000, 0x40000000
209	.word 0x00000000, 0x80000000
210	.word 0x00000001, 0x00000000
211	.word 0x00000002, 0x00000000
212	.word 0x00000004, 0x00000000
213	.word 0x00000008, 0x00000000
214	.word 0x00000010, 0x00000000
215	.word 0x00000020, 0x00000000
216	.word 0x00000040, 0x00000000
217	.word 0x00000080, 0x00000000
218	.word 0x00000100, 0x00000000
219	.word 0x00000200, 0x00000000
220	.word 0x00000400, 0x00000000
221	.word 0x00000800, 0x00000000
222	.word 0x00001000, 0x00000000
223	.word 0x00002000, 0x00000000
224	.word 0x00004000, 0x00000000
225	.word 0x00008000, 0x00000000
226	.word 0x00010000, 0x00000000
227	.word 0x00020000, 0x00000000
228	.word 0x00040000, 0x00000000
229	.word 0x00080000, 0x00000000
230	.word 0x00100000, 0x00000000
231	.word 0x00200000, 0x00000000
232	.word 0x00400000, 0x00000000
233	.word 0x00800000, 0x00000000
234	.word 0x01000000, 0x00000000
235	.word 0x02000000, 0x00000000
236	.word 0x04000000, 0x00000000
237	.word 0x08000000, 0x00000000
238	.word 0x10000000, 0x00000000
239	.word 0x20000000, 0x00000000
240	.word 0x40000000, 0x00000000
241	.word 0x80000000, 0x00000000
242
243	fsr_save0:
244	.word 0,0
245	fsr_save1:
246	.word 0,0
247	fsr_save2:
248	.word 0,0
249	fsr_save3:
250	.word 0,0
251
252
253	.end