[OpenSPARC-T2-DV] / verif / diag / assembly / exu / ffu_siam_n2.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: ffu_siam_n2.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define	FSR_DUMP_P      	%g7
#define OPERAND_P	        %g2

#define NUM_MODES     8
      
#define H_T0_Fp_exception_ieee_754_0x21 trap_ieee754
    
#define  MAIN_PAGE_HV_ALSO  
#define  MAIN_PAGE_NUCLEUS_ALSO

#define ENABLE_T0_Clean_Window_0x24
#define ENABLE_T0_Corrected_ECC_error_0x63 
#define ENABLE_T0_Data_Access_Exception_0x30 
#define ENABLE_T0_Data_access_error_0x32 
#define ENABLE_T0_Division_By_Zero_0x28 
#define ENABLE_T0_Fp_disabled_0x20
#define ENABLE_T0_Fp_exception_ieee_754_0x21 
#define ENABLE_T0_Fp_exception_other_0x22 
#define ENABLE_T0_Illegal_instruction_0x10
#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
#define ENABLE_T0_Instruction_access_error_0x0a 
#define ENABLE_T0_Instruction_access_exception_0x08
#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
#define ENABLE_T0_Mem_Address_Not_Aligned_0x34 
#define ENABLE_T0_Privileged_Action_0x37 
#define ENABLE_T0_Privileged_opcode_0x11
#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
#define ENABLE_T0_Tag_Overflow_0x23 
#define ENABLE_T0_Unimplemented_LDD_0x12
#define ENABLE_T0_Unimplemented_STD_0x13
#define ENABLE_T0_data_access_protection_0x6c 
#define ENABLE_T0_fast_data_access_MMU_miss_0x68
#define ENABLE_T0_fast_instr_access_MMU_miss_0x64
	    
#include "hboot.s"

.global main
main:
	th_fork(th_main,%l0)		! seperate the threads

th_main_0:   
    	wr      %g0,0x4,%fprs 
	set	fsr_data0,%g1
	set	operands_0,OPERAND_P
	set	fsr_save0,FSR_DUMP_P
	ba      all_thds
	nop
     
th_main_1: 
    	wr      %g0,0x4,%fprs 
	set	fsr_data1,%g1
	set	operands_1,OPERAND_P
	set	fsr_save1,FSR_DUMP_P
	ba      all_thds
	nop
        
th_main_2: 
        wr      %g0,0x4,%fprs 
	set	fsr_data2,%g1
	set	operands_2,OPERAND_P
	set	fsr_save2,FSR_DUMP_P
	ba      all_thds
	nop   
th_main_3:
        wr      %g0,0x4,%fprs 
	set	fsr_data3,%g1
	set	operands_3,OPERAND_P
	set	fsr_save3,FSR_DUMP_P
	ba      all_thds
	nop   
    

all_thds:   
	mov	NUM_MODES,%i7
	ldd	[OPERAND_P], %f0
	ldd	[OPERAND_P+8], %f2
	! clear destination regs because they are unchagned on a trap
	set	zero_words,%l2
	ldd	[%l2],%f22
	ldd	[%l2],%f24
    
loop: 
	ld	[%g1],%fsr
    	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	st	%fsr,[FSR_DUMP_P]	! double check that st %fsr does not
	ld	[FSR_DUMP_P],%l2	! clear wrong fields

	th_fork(th_test,%l0)		! seperate the threads
    
th_test_3:   
	siam	0		! use fsr    
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
	siam	3		! use fsr
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
	siam	4	   
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
	siam	5
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
    	siam	6	   
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
	siam	7
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
	ba	next_case
	nop
    
th_test_2:   
	siam	0		! use fsr    
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1 
	fmovd	%f22,%f4
   
	siam	4
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
	siam	7	   
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
	siam	5
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
    	siam	2		! use fsr	   
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1 
	fmovd	%f22,%f4
   
	siam	6
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
	ba	next_case
	nop
    
th_test_1:   
	siam	7
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
	siam	6
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
	siam	5	   
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
	siam	3		! use fsr
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
    	siam	4	   
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
	siam	1		! use fsr
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
	ba	next_case
	nop    
    
th_test_0:   
	siam	6
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
	siam	5
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
	siam	4	   
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
	siam	2
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
    	siam	0		! use fsr	   
	faddd 	%f0, %f2, %f22
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f24,%f4
    
	siam	7
	faddd 	%f0, %f2, %f24
	st	%fsr,[FSR_DUMP_P]
	ld	[FSR_DUMP_P],%l1
	fmovd	%f22,%f4
    
next_case:
	add	 %g1, 4, %g1
	sub	 %i7, 1, %i7			! next mode
	brnz,a	 %i7, loop
	nop


good_end:   
	ta	T_GOOD_TRAP
	nop
	nop    

!==========================    
.data
.align 0x1fff+1

.align 8
fsr_data0:
	 	 .word	0x00800000
	 	 .word	0x40800000
	 	 .word	0x80800000
	 	 .word	0xc0800000
    	 	 .word	0x00000000
	 	 .word	0x40000000
	 	 .word	0x80000000
	 	 .word	0xc0000000
fsr_data1:  
	 	 .word	0x40800000
	 	 .word	0x40000000
	 	 .word	0x80800000
	 	 .word	0x80000000
	 	 .word	0xc0800000
	 	 .word	0xc0000000
	 	 .word	0x00800000
	 	 .word	0x00000000
fsr_data2:
	 	 .word	0x80000000
	 	 .word	0xc0000000
	 	 .word	0x00000000
	 	 .word	0x40000000
       	 	 .word	0x80800000
	 	 .word	0xc0800000
	 	 .word	0x00800000
	 	 .word	0x40800000
fsr_data3:
	 	 .word	0xc0800000    
	 	 .word	0x00800000
	 	 .word	0x00000000
	 	 .word	0x40800000
	 	 .word	0x80800000
    	 	 .word	0x40000000
	 	 .word	0x80000000
		 .word  0xc0000000

fsr_save0:	 .word  0
fsr_save1:	 .word  0
fsr_save2:	 .word  0
fsr_save3:	 .word  0

    
.align 8
.global operand_start
operands_0:
	! format = one bit of sign, 11 bits of exponent, 52 bits of fraction
	 .word	 0xf0080000, 0x00000000, 0x80080000, 0x00000000
operands_1:
	 .word	 0x3fefffff, 0xfffffffe, 0x3fefffff, 0xfffffffd
operands_2:
	 .word	 0x3fefffff, 0xfffffffc, 0x3ff80000, 0x00000001
operands_3:
	 .word	 0x00efffff, 0xffffffff, 0x00f80000, 0x00000004

zero_words:
	.word    0,0,0,0


.text
 
.global trap_ieee754   
trap_ieee754:
	done
	nop
    
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: ffu_siam_n2.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define FSR_DUMP_P %g7
	39	#define OPERAND_P %g2
	40
	41	#define NUM_MODES 8
	42
	43	#define H_T0_Fp_exception_ieee_754_0x21 trap_ieee754
	44
	45	#define MAIN_PAGE_HV_ALSO
	46	#define MAIN_PAGE_NUCLEUS_ALSO
	47
	48	#define ENABLE_T0_Clean_Window_0x24
	49	#define ENABLE_T0_Corrected_ECC_error_0x63
	50	#define ENABLE_T0_Data_Access_Exception_0x30
	51	#define ENABLE_T0_Data_access_error_0x32
	52	#define ENABLE_T0_Division_By_Zero_0x28
	53	#define ENABLE_T0_Fp_disabled_0x20
	54	#define ENABLE_T0_Fp_exception_ieee_754_0x21
	55	#define ENABLE_T0_Fp_exception_other_0x22
	56	#define ENABLE_T0_Illegal_instruction_0x10
	57	#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
	58	#define ENABLE_T0_Instruction_access_error_0x0a
	59	#define ENABLE_T0_Instruction_access_exception_0x08
	60	#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
	61	#define ENABLE_T0_Mem_Address_Not_Aligned_0x34
	62	#define ENABLE_T0_Privileged_Action_0x37
	63	#define ENABLE_T0_Privileged_opcode_0x11
	64	#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
65	#define ENABLE_T0_Tag_Overflow_0x23
66	#define ENABLE_T0_Unimplemented_LDD_0x12
67	#define ENABLE_T0_Unimplemented_STD_0x13
68	#define ENABLE_T0_data_access_protection_0x6c
69	#define ENABLE_T0_fast_data_access_MMU_miss_0x68
70	#define ENABLE_T0_fast_instr_access_MMU_miss_0x64
71
72	#include "hboot.s"
73
74	.global main
75	main:
76	th_fork(th_main,%l0) ! seperate the threads
77
78	th_main_0:
79	wr %g0,0x4,%fprs
80	set fsr_data0,%g1
81	set operands_0,OPERAND_P
82	set fsr_save0,FSR_DUMP_P
83	ba all_thds
84	nop
85
86	th_main_1:
87	wr %g0,0x4,%fprs
88	set fsr_data1,%g1
89	set operands_1,OPERAND_P
90	set fsr_save1,FSR_DUMP_P
91	ba all_thds
92	nop
93
94	th_main_2:
95	wr %g0,0x4,%fprs
96	set fsr_data2,%g1
97	set operands_2,OPERAND_P
98	set fsr_save2,FSR_DUMP_P
99	ba all_thds
100	nop
101	th_main_3:
102	wr %g0,0x4,%fprs
103	set fsr_data3,%g1
104	set operands_3,OPERAND_P
105	set fsr_save3,FSR_DUMP_P
106	ba all_thds
107	nop
108
109
110	all_thds:
111	mov NUM_MODES,%i7
112	ldd [OPERAND_P], %f0
113	ldd [OPERAND_P+8], %f2
114	! clear destination regs because they are unchagned on a trap
115	set zero_words,%l2
116	ldd [%l2],%f22
117	ldd [%l2],%f24
118
119	loop:
120	ld [%g1],%fsr
121	st %fsr,[FSR_DUMP_P]
122	ld [FSR_DUMP_P],%l1
123	st %fsr,[FSR_DUMP_P] ! double check that st %fsr does not
124	ld [FSR_DUMP_P],%l2 ! clear wrong fields
125
126	th_fork(th_test,%l0) ! seperate the threads
127
128	th_test_3:
129	siam 0 ! use fsr
130	faddd %f0, %f2, %f22
131	st %fsr,[FSR_DUMP_P]
132	ld [FSR_DUMP_P],%l1
133	fmovd %f22,%f4
134
135	siam 3 ! use fsr
136	faddd %f0, %f2, %f24
137	st %fsr,[FSR_DUMP_P]
138	ld [FSR_DUMP_P],%l1
139	fmovd %f24,%f4
140
141	siam 4
142	faddd %f0, %f2, %f22
143	st %fsr,[FSR_DUMP_P]
144	ld [FSR_DUMP_P],%l1
145	fmovd %f22,%f4
146
147	siam 5
148	faddd %f0, %f2, %f24
149	st %fsr,[FSR_DUMP_P]
150	ld [FSR_DUMP_P],%l1
151	fmovd %f24,%f4
152
153	siam 6
154	faddd %f0, %f2, %f22
155	st %fsr,[FSR_DUMP_P]
156	ld [FSR_DUMP_P],%l1
157	fmovd %f22,%f4
158
159	siam 7
160	faddd %f0, %f2, %f24
161	st %fsr,[FSR_DUMP_P]
162	ld [FSR_DUMP_P],%l1
163	fmovd %f24,%f4
164
165	ba next_case
166	nop
167
168	th_test_2:
169	siam 0 ! use fsr
170	faddd %f0, %f2, %f22
171	st %fsr,[FSR_DUMP_P]
172	ld [FSR_DUMP_P],%l1
173	fmovd %f22,%f4
174
175	siam 4
176	faddd %f0, %f2, %f24
177	st %fsr,[FSR_DUMP_P]
178	ld [FSR_DUMP_P],%l1
179	fmovd %f24,%f4
180
181	siam 7
182	faddd %f0, %f2, %f22
183	st %fsr,[FSR_DUMP_P]
184	ld [FSR_DUMP_P],%l1
185	fmovd %f22,%f4
186
187	siam 5
188	faddd %f0, %f2, %f24
189	st %fsr,[FSR_DUMP_P]
190	ld [FSR_DUMP_P],%l1
191	fmovd %f24,%f4
192
193	siam 2 ! use fsr
194	faddd %f0, %f2, %f22
195	st %fsr,[FSR_DUMP_P]
196	ld [FSR_DUMP_P],%l1
197	fmovd %f22,%f4
198
199	siam 6
200	faddd %f0, %f2, %f24
201	st %fsr,[FSR_DUMP_P]
202	ld [FSR_DUMP_P],%l1
203	fmovd %f24,%f4
204
205	ba next_case
206	nop
207
208	th_test_1:
209	siam 7
210	faddd %f0, %f2, %f22
211	st %fsr,[FSR_DUMP_P]
212	ld [FSR_DUMP_P],%l1
213	fmovd %f22,%f4
214
215	siam 6
216	faddd %f0, %f2, %f24
217	st %fsr,[FSR_DUMP_P]
218	ld [FSR_DUMP_P],%l1
219	fmovd %f24,%f4
220
221	siam 5
222	faddd %f0, %f2, %f22
223	st %fsr,[FSR_DUMP_P]
224	ld [FSR_DUMP_P],%l1
225	fmovd %f22,%f4
226
227	siam 3 ! use fsr
228	faddd %f0, %f2, %f24
229	st %fsr,[FSR_DUMP_P]
230	ld [FSR_DUMP_P],%l1
231	fmovd %f24,%f4
232
233	siam 4
234	faddd %f0, %f2, %f22
235	st %fsr,[FSR_DUMP_P]
236	ld [FSR_DUMP_P],%l1
237	fmovd %f22,%f4
238
239	siam 1 ! use fsr
240	faddd %f0, %f2, %f24
241	st %fsr,[FSR_DUMP_P]
242	ld [FSR_DUMP_P],%l1
243	fmovd %f24,%f4
244
245	ba next_case
246	nop
247
248	th_test_0:
249	siam 6
250	faddd %f0, %f2, %f22
251	st %fsr,[FSR_DUMP_P]
252	ld [FSR_DUMP_P],%l1
253	fmovd %f22,%f4
254
255	siam 5
256	faddd %f0, %f2, %f24
257	st %fsr,[FSR_DUMP_P]
258	ld [FSR_DUMP_P],%l1
259	fmovd %f24,%f4
260
261	siam 4
262	faddd %f0, %f2, %f22
263	st %fsr,[FSR_DUMP_P]
264	ld [FSR_DUMP_P],%l1
265	fmovd %f22,%f4
266
267	siam 2
268	faddd %f0, %f2, %f24
269	st %fsr,[FSR_DUMP_P]
270	ld [FSR_DUMP_P],%l1
271	fmovd %f24,%f4
272
273	siam 0 ! use fsr
274	faddd %f0, %f2, %f22
275	st %fsr,[FSR_DUMP_P]
276	ld [FSR_DUMP_P],%l1
277	fmovd %f24,%f4
278
279	siam 7
280	faddd %f0, %f2, %f24
281	st %fsr,[FSR_DUMP_P]
282	ld [FSR_DUMP_P],%l1
283	fmovd %f22,%f4
284
285	next_case:
286	add %g1, 4, %g1
287	sub %i7, 1, %i7 ! next mode
288	brnz,a %i7, loop
289	nop
290
291
292
293	good_end:
294	ta T_GOOD_TRAP
295	nop
296	nop
297
298	!==========================
299	.data
300	.align 0x1fff+1
301
302	.align 8
303	fsr_data0:
304	.word 0x00800000
305	.word 0x40800000
306	.word 0x80800000
307	.word 0xc0800000
308	.word 0x00000000
309	.word 0x40000000
310	.word 0x80000000
311	.word 0xc0000000
312	fsr_data1:
313	.word 0x40800000
314	.word 0x40000000
315	.word 0x80800000
316	.word 0x80000000
317	.word 0xc0800000
318	.word 0xc0000000
319	.word 0x00800000
320	.word 0x00000000
321	fsr_data2:
322	.word 0x80000000
323	.word 0xc0000000
324	.word 0x00000000
325	.word 0x40000000
326	.word 0x80800000
327	.word 0xc0800000
328	.word 0x00800000
329	.word 0x40800000
330	fsr_data3:
331	.word 0xc0800000
332	.word 0x00800000
333	.word 0x00000000
334	.word 0x40800000
335	.word 0x80800000
336	.word 0x40000000
337	.word 0x80000000
338	.word 0xc0000000
339
340	fsr_save0: .word 0
341	fsr_save1: .word 0
342	fsr_save2: .word 0
343	fsr_save3: .word 0
344
345
346	.align 8
347	.global operand_start
348	operands_0:
349	! format = one bit of sign, 11 bits of exponent, 52 bits of fraction
350	.word 0xf0080000, 0x00000000, 0x80080000, 0x00000000
351	operands_1:
352	.word 0x3fefffff, 0xfffffffe, 0x3fefffff, 0xfffffffd
353	operands_2:
354	.word 0x3fefffff, 0xfffffffc, 0x3ff80000, 0x00000001
355	operands_3:
356	.word 0x00efffff, 0xffffffff, 0x00f80000, 0x00000004
357
358	zero_words:
359	.word 0,0,0,0
360
361
362
363
364	.text
365
366	.global trap_ieee754
367	trap_ieee754:
368	done
369	nop
370
371	.end