[OpenSPARC-T2-DV] / verif / diag / assembly / exu / fp_arth_exc0_n2.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: fp_arth_exc0_n2.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define	H_T0_Fp_exception_ieee_754_0x21 T0_Fp_exception_ieee_754

#define ENABLE_T0_Fp_disabled_0x20

#define  MAIN_PAGE_HV_ALSO  
#define  MAIN_PAGE_NUCLEUS_ALSO

#define ENABLE_T0_Clean_Window_0x24
#define ENABLE_T0_Corrected_ECC_error_0x63 
#define ENABLE_T0_Data_Access_Exception_0x30 
#define ENABLE_T0_Data_access_error_0x32 
#define ENABLE_T0_Division_By_Zero_0x28 
#define ENABLE_T0_Fp_disabled_0x20
#define ENABLE_T0_Fp_exception_ieee_754_0x21 
#define ENABLE_T0_Fp_exception_other_0x22 
#define ENABLE_T0_Illegal_instruction_0x10
#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
#define ENABLE_T0_Instruction_access_error_0x0a 
#define ENABLE_T0_Instruction_access_exception_0x08
#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
#define ENABLE_T0_Mem_Address_Not_Aligned_0x34 
#define ENABLE_T0_Privileged_Action_0x37 
#define ENABLE_T0_Privileged_opcode_0x11
#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
#define ENABLE_T0_Tag_Overflow_0x23 
#define ENABLE_T0_Unimplemented_LDD_0x12
#define ENABLE_T0_Unimplemented_STD_0x13
#define ENABLE_T0_data_access_protection_0x6c 
#define ENABLE_T0_fast_data_access_MMU_miss_0x68
#define ENABLE_T0_fast_instr_access_MMU_miss_0x64

	
#include "hboot.s"


.text
.global main  

main:

        wr      	%g0, 0x4, %fprs         /* make sure fef is 1 */

	setx		data0, %l0, %l1		! Single precision boundaries
	setx		data1, %l0, %l2		! Some data
	setx		fsr_tem_en, %l0, %l3	! fsr tem enable value
	setx		fsr_tem_dis, %l0, %l4	! fsr tem disable value
	setx		ddata0, %l0, %l6	! Double precision boundaries

/*******************************************************
 * Create arithmetic exceptions
 *******************************************************/

	! By default, mask is disabled

	ld		[%l4+0x0], %fsr		! Read it from memory - trap disabled
						! expect aexc fields to accrue

/* floating point integer Conversions */

	! Convert all the numbers into integer - put it in a loop

	set		0x17, %g1		! Max loop count
	set		0x0, %g2		! loop iterator	

fp_convert_loop0:

	sll		%g2, 0x2, %g3		! Align address
	sll		%g2, 0x3, %g4		! Align address
	ld		[%l1+%g3], %f0		! single precision
	ldd		[%l6+%g4], %f2		! double precision

	fstox		%f0, %f10		! Conversions
	fstoi		%f0, %f11		! Conversions

	setx		user_scratch, %l0, %l5	! scratch
	stx		%fsr, [%l5+0x0]		! Test out fsr
	ldx		[%l5+0x0], %fsr		! Need to test the sync operation

	fdtox		%f2, %f12		! Conversions
	fdtoi		%f2, %f13		! Conversions

	setx		user_scratch, %l0, %l5	! scratch
	stx		%fsr, [%l5+0x0]		! Test out fsr
	ldx		[%l5+0x0], %fsr		! Need to test the sync operation

	fstod		%f0, %f14		! Conversions
	fdtos		%f2, %f15		! Conversions - Should cause NX in some cases

	setx		user_scratch, %l0, %l5	! scratch
	stx		%fsr, [%l5+0x0]		! Test out fsr
	ldx		[%l5+0x0], %fsr		! Need to test the sync operation

	fstox		%f2, %f14		! Conversions
	fstoi		%f2, %f16		! Conversions

	fxtos		%f14, %f18		! Conversions
	fxtod		%f14, %f20		! Conversions
	fitos		%f16, %f18		! Conversions
	fitod		%f16, %f20		! Conversions

	fdtox		%f2, %f14		! Conversions
	fdtoi		%f2, %f16		! Conversions

	fxtos		%f14, %f18		! Conversions
	fxtod		%f14, %f20		! Conversions
	fitos		%f16, %f18		! Conversions
	fitod		%f16, %f20		! Conversions

	fdtoi		%f20, %f20		! Just to see how the registers are preserved

	setx		user_scratch, %l0, %l5	! scratch
	stx		%fsr, [%l5+0x0]		! Test out fsr
	ldx		[%l5+0x0], %fsr		! Need to test the sync operation

	add		%g2, 0x1, %g2
	subcc		%g2, %g1, %g0

	bne,a		fp_convert_loop0	! If not 0, go to test more
        wr      	%g0, 0x4, %fprs         ! set ul and ll to 0

/* floating add/sub/compare/multiply */

	ld		[%l3+0x0], %fsr		! Read it from memory - trap enabled

	set		0x16, %g1		! Max loop count
	set		0x0, %g2		! loop iterator	
		
fp_asmds_loop0:

	sll		%g2, 0x2, %g3		! Align address
	sll		%g2, 0x3, %g4		! Align address
	ld		[%l1+%g3], %f0		! single precision
	ldd		[%l6+%g4], %f2		! double precision

	add		%g3, 0x4, %g3
	add		%g4, 0x8, %g4
	ld		[%l1+%g3], %f4		! single precision
	ldd		[%l6+%g4], %f6		! double precision

	fadds		%f0, %f4, %f8
	faddd		%f2, %f6, %f10
	fsubs		%f0, %f4, %f8
	fsubd		%f2, %f6, %f10
	fsubs		%f4, %f0, %f32		! This should set fprs.ul
	fsubd		%f6, %f2, %f34
	fcmps		%fcc0, %f0, %f4
	fcmpd		%fcc1, %f2, %f6
	fcmpes		%fcc0, %f0, %f4
	fcmped		%fcc1, %f2, %f6
	fmuls		%f0, %f4, %f8
	fmuld		%f2, %f6, %f10
	fsmuld		%f0, %f4, %f8
	fdivs		%f0, %f4, %f8
	fdivs		%f4, %f0, %f8
	fdivd		%f2, %f6, %f10
	fdivd		%f6, %f2, %f10
!	fsqrts		%f2, %f8
!	fsqrtd		%f6, %f10

	setx		user_scratch, %l0, %l5	! scratch
	stx		%fsr, [%l5+0x0]		! Test out fsr
	ldx		[%l5+0x0], %fsr		! Need to test the sync operation

	add		%g2, 0x1, %g2
	subcc		%g2, %g1, %g0

	bne,a		fp_asmds_loop0		! If not 0, go to test more
        wr      	%g0, 0x4, %fprs         ! set ul and ll to 0

/* Floating point divide */

	! fdivs

	ld		[%l2+0x0], %f0
	ld		[%l2+0x4], %f1
	ld		[%l2+0x8], %f2

	fdivs		%f0, %f1, %f10		! This should cause fp divide-by-0 exception if enabled
	setx		user_scratch, %l0, %l5	! scratch
	stx		%fsr, [%l5+0x0]
	ldx		[%l5+0x0], %fsr		! Need to test the sync operation

	! Enable mask

	ld		[%l3+0x0], %fsr		! Read it from memory
	fdivs		%f0, %f1, %f10		! This should cause fp divide-by-0 exception if enabled
	setx		user_scratch, %l0, %l5	! scratch
	stx		%fsr, [%l5+0x8]
	ldx		[%l5+0x8], %g1		! Just read them from memory
	ldx		[%l5+0x0], %g2		! Just read them from memory

	! Disable mask

	ld		[%l4+0x0], %fsr		! Read it from memory
	fdivs		%f0, %f1, %f10		! This should cause fp divide-by-0 exception if enabled
	

	! Disable mask


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
	ta		T_GOOD_TRAP

test_fail:
	ta		T_BAD_TRAP
/*******************************************************
 * Data section 
 *******************************************************/
	
.data

data0:
	.word		0xffffffff	! -NaN (Quiet)		(S = 1, E = 255, F > 0)		00
	.word		0xffc00001	! -NaN (Quiet)		(S = 1, E = 255, F > 0)		04
	.word		0xffc00000	! -NaN (Indeterminate)	(S = 1, E = 255, F > 0)		08
	.word		0xffbfffff	! -NaN (Signaling)	(S = 1, E = 255, F > 0)		0c
	.word		0xff800001	! -NaN (Signaling)	(S = 1, E = 255, F > 0)		10
	.word		0xff800000	! -ve Infinity (ovf)	(S = 1, E = 255, F = 0)		14
	.word		0xff7fffff	! -ve normalized	(S = 1, 0 < E < 255)		18
	.word		0x80800000	! -ve normalized	(S = 1, 0 < E < 255)		1c
	.word		0x807fffff	! -ve denormalized	(S = 1, E=0, F is non-zero)	20
	.word		0x80000001	! -ve denormalized	(S = 1, E=0, F is non-zero)	24
	.word		0x80000000	! -ve Underflow		(S = 1, E=0, F = 0)		28
	.word		0x80000000	! -ve 0			(S = 1, E=0, F = 0)		2c
	.word		0x00000000	! +ve 0			(S = 0, E=0, F = 0)		30
	.word		0x00000000	! +ve Underflow		(S = 0, E=0, F = 0)		34
	.word		0x00000001	! +ve denormalized	(S = 0, E=0, F is non-zero)	38
	.word		0x007fffff	! +ve denormalized	(S = 0, E=0, F is non-zero)	3c
	.word		0x00800000	! +ve normalized	(S = 0, 0 < E < 255)		40
	.word		0x7f7fffff	! +ve normalized	(S = 0, 0 < E < 255)		44
	.word		0x7f800000	! +ve Infinity (ovf)	(S = 0, E = 255, F = 0)		48
	.word		0x7f800001	! +NaN (Signaling)	(S = 0, E = 255, F > 0)		4c
	.word		0x7fbfffff	! +NaN (Signaling)	(S = 0, E = 255, F > 0)		50
	.word		0x7fc00000	! +NaN (Quiet)		(S = 0, E = 255, F > 0)		54
	.word		0x7fffffff	! +NaN (Quiet)		(S = 0, E = 255, F > 0)		5c

.align 256

ddata0:
	.xword		0xffffffffffffffff	! -NaN (Quiet)		(S = 1, E = 2047, F > 0)		00
	.xword		0xfff8000000000001	! -NaN (Quiet)		(S = 1, E = 2047, F > 0)		04
	.xword		0xfff8000000000000	! -NaN (Indeterminate)	(S = 1, E = 2047, F > 0)		08
	.xword		0xfff7ffffffffffff	! -NaN (Signaling)	(S = 1, E = 2047, F > 0)		0c
	.xword		0xfff0000000000001	! -NaN (Signaling)	(S = 1, E = 2047, F > 0)		10
	.xword		0xfff0000000000000	! -ve Infinity (ovf)	(S = 1, E = 2047, F = 0)		14
	.xword		0xffefffffffffffff	! -ve normalized	(S = 1, 0 < E < 2047)			18
	.xword		0x8010000000000000	! -ve normalized	(S = 1, 0 < E < 2047)			1c
	.xword		0x800fffffffffffff	! -ve denormalized	(S = 1, E=0, F is non-zero)		20
	.xword		0x8000000000000001	! -ve denormalized	(S = 1, E=0, F is non-zero)		24
	.xword		0x8000000000000000	! -ve Underflow		(S = 1, E=0, F = 0)			28
	.xword		0x8000000000000000	! -ve 0			(S = 1, E=0, F = 0)			2c
	.xword		0x0000000000000000	! +ve 0			(S = 0, E=0, F = 0)			30
	.xword		0x0000000000000000	! +ve Underflow		(S = 0, E=0, F = 0)			34
	.xword		0x0000000000000001	! +ve denormalized	(S = 0, E=0, F is non-zero)		38
	.xword		0x000fffffffffffff	! +ve denormalized	(S = 0, E=0, F is non-zero)		3c
	.xword		0x0010000000000000	! +ve normalized	(S = 0, 0 < E < 2047)			40
	.xword		0x7fefffffffffffff	! +ve normalized	(S = 0, 0 < E < 2047)			44
	.xword		0x7ff0000000000000	! +ve Infinity (ovf)	(S = 0, E = 2047, F = 0)		48
	.xword		0x7ff0000000000001	! +NaN (Signaling)	(S = 0, E = 2047, F > 0)		4c
	.xword		0x7ff7ffffffffffff	! +NaN (Signaling)	(S = 0, E = 2047, F > 0)		50
	.xword		0x7ff8000000000000	! +NaN (Quiet)		(S = 0, E = 2047, F > 0)		54
	.xword		0x7fffffffffffffff	! +NaN (Quiet)		(S = 0, E = 2047, F > 0)		5c

.align 256

data1:
	.word		0x3f800000	! 1.0
	.word		0x00000000	! 0.0
	.word		0xbf800000	! -1.0


.align 128

fsr_tem_en:
	.word		0x0f800000	! TEM - all enabled

fsr_tem_dis:
	.word		0x00000000	! TEM - all disabled
	.word		0x00000000

.align 128

user_scratch:
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000


/*******************************************************
 * My own trap handlers
 *******************************************************/


.global T0_Fp_exception_ieee_754
T0_Fp_exception_ieee_754:	
	rdpr	%tpc, %i0
	rdpr	%tnpc, %i1
	rdpr	%tstate, %i1
	rdpr	%tt, %i1
	setx	scratch, %l0, %l5	! scratch
	stx	%fsr, [%l5+0x0]
	ldx	[%l5+0x0], %fsr		! 
	done
	nop

.data
.align 128

scratch:
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
	.word		0x00000000
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: fp_arth_exc0_n2.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_T0_Fp_exception_ieee_754_0x21 T0_Fp_exception_ieee_754
	39
	40	#define ENABLE_T0_Fp_disabled_0x20
	41
	42	#define MAIN_PAGE_HV_ALSO
	43	#define MAIN_PAGE_NUCLEUS_ALSO
	44
	45	#define ENABLE_T0_Clean_Window_0x24
	46	#define ENABLE_T0_Corrected_ECC_error_0x63
	47	#define ENABLE_T0_Data_Access_Exception_0x30
	48	#define ENABLE_T0_Data_access_error_0x32
	49	#define ENABLE_T0_Division_By_Zero_0x28
	50	#define ENABLE_T0_Fp_disabled_0x20
	51	#define ENABLE_T0_Fp_exception_ieee_754_0x21
	52	#define ENABLE_T0_Fp_exception_other_0x22
	53	#define ENABLE_T0_Illegal_instruction_0x10
	54	#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
	55	#define ENABLE_T0_Instruction_access_error_0x0a
	56	#define ENABLE_T0_Instruction_access_exception_0x08
	57	#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
	58	#define ENABLE_T0_Mem_Address_Not_Aligned_0x34
	59	#define ENABLE_T0_Privileged_Action_0x37
	60	#define ENABLE_T0_Privileged_opcode_0x11
	61	#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
	62	#define ENABLE_T0_Tag_Overflow_0x23
	63	#define ENABLE_T0_Unimplemented_LDD_0x12
	64	#define ENABLE_T0_Unimplemented_STD_0x13
65	#define ENABLE_T0_data_access_protection_0x6c
66	#define ENABLE_T0_fast_data_access_MMU_miss_0x68
67	#define ENABLE_T0_fast_instr_access_MMU_miss_0x64
68
69
70	#include "hboot.s"
71
72
73
74	.text
75	.global main
76
77	main:
78
79	wr %g0, 0x4, %fprs /* make sure fef is 1 */
80
81	setx data0, %l0, %l1 ! Single precision boundaries
82	setx data1, %l0, %l2 ! Some data
83	setx fsr_tem_en, %l0, %l3 ! fsr tem enable value
84	setx fsr_tem_dis, %l0, %l4 ! fsr tem disable value
85	setx ddata0, %l0, %l6 ! Double precision boundaries
86
87	/*******************************************************
88	* Create arithmetic exceptions
89	*******************************************************/
90
91	! By default, mask is disabled
92
93	ld [%l4+0x0], %fsr ! Read it from memory - trap disabled
94	! expect aexc fields to accrue
95
96	/* floating point integer Conversions */
97
98	! Convert all the numbers into integer - put it in a loop
99
100	set 0x17, %g1 ! Max loop count
101	set 0x0, %g2 ! loop iterator
102
103	fp_convert_loop0:
104
105	sll %g2, 0x2, %g3 ! Align address
106	sll %g2, 0x3, %g4 ! Align address
107	ld [%l1+%g3], %f0 ! single precision
108	ldd [%l6+%g4], %f2 ! double precision
109
110	fstox %f0, %f10 ! Conversions
111	fstoi %f0, %f11 ! Conversions
112
113	setx user_scratch, %l0, %l5 ! scratch
114	stx %fsr, [%l5+0x0] ! Test out fsr
115	ldx [%l5+0x0], %fsr ! Need to test the sync operation
116
117	fdtox %f2, %f12 ! Conversions
118	fdtoi %f2, %f13 ! Conversions
119
120	setx user_scratch, %l0, %l5 ! scratch
121	stx %fsr, [%l5+0x0] ! Test out fsr
122	ldx [%l5+0x0], %fsr ! Need to test the sync operation
123
124	fstod %f0, %f14 ! Conversions
125	fdtos %f2, %f15 ! Conversions - Should cause NX in some cases
126
127	setx user_scratch, %l0, %l5 ! scratch
128	stx %fsr, [%l5+0x0] ! Test out fsr
129	ldx [%l5+0x0], %fsr ! Need to test the sync operation
130
131	fstox %f2, %f14 ! Conversions
132	fstoi %f2, %f16 ! Conversions
133
134	fxtos %f14, %f18 ! Conversions
135	fxtod %f14, %f20 ! Conversions
136	fitos %f16, %f18 ! Conversions
137	fitod %f16, %f20 ! Conversions
138
139	fdtox %f2, %f14 ! Conversions
140	fdtoi %f2, %f16 ! Conversions
141
142	fxtos %f14, %f18 ! Conversions
143	fxtod %f14, %f20 ! Conversions
144	fitos %f16, %f18 ! Conversions
145	fitod %f16, %f20 ! Conversions
146
147	fdtoi %f20, %f20 ! Just to see how the registers are preserved
148
149	setx user_scratch, %l0, %l5 ! scratch
150	stx %fsr, [%l5+0x0] ! Test out fsr
151	ldx [%l5+0x0], %fsr ! Need to test the sync operation
152
153	add %g2, 0x1, %g2
154	subcc %g2, %g1, %g0
155
156	bne,a fp_convert_loop0 ! If not 0, go to test more
157	wr %g0, 0x4, %fprs ! set ul and ll to 0
158
159	/* floating add/sub/compare/multiply */
160
161	ld [%l3+0x0], %fsr ! Read it from memory - trap enabled
162
163	set 0x16, %g1 ! Max loop count
164	set 0x0, %g2 ! loop iterator
165
166	fp_asmds_loop0:
167
168	sll %g2, 0x2, %g3 ! Align address
169	sll %g2, 0x3, %g4 ! Align address
170	ld [%l1+%g3], %f0 ! single precision
171	ldd [%l6+%g4], %f2 ! double precision
172
173	add %g3, 0x4, %g3
174	add %g4, 0x8, %g4
175	ld [%l1+%g3], %f4 ! single precision
176	ldd [%l6+%g4], %f6 ! double precision
177
178	fadds %f0, %f4, %f8
179	faddd %f2, %f6, %f10
180	fsubs %f0, %f4, %f8
181	fsubd %f2, %f6, %f10
182	fsubs %f4, %f0, %f32 ! This should set fprs.ul
183	fsubd %f6, %f2, %f34
184	fcmps %fcc0, %f0, %f4
185	fcmpd %fcc1, %f2, %f6
186	fcmpes %fcc0, %f0, %f4
187	fcmped %fcc1, %f2, %f6
188	fmuls %f0, %f4, %f8
189	fmuld %f2, %f6, %f10
190	fsmuld %f0, %f4, %f8
191	fdivs %f0, %f4, %f8
192	fdivs %f4, %f0, %f8
193	fdivd %f2, %f6, %f10
194	fdivd %f6, %f2, %f10
195	! fsqrts %f2, %f8
196	! fsqrtd %f6, %f10
197
198	setx user_scratch, %l0, %l5 ! scratch
199	stx %fsr, [%l5+0x0] ! Test out fsr
200	ldx [%l5+0x0], %fsr ! Need to test the sync operation
201
202	add %g2, 0x1, %g2
203	subcc %g2, %g1, %g0
204
205	bne,a fp_asmds_loop0 ! If not 0, go to test more
206	wr %g0, 0x4, %fprs ! set ul and ll to 0
207
208	/* Floating point divide */
209
210	! fdivs
211
212	ld [%l2+0x0], %f0
213	ld [%l2+0x4], %f1
214	ld [%l2+0x8], %f2
215
216	fdivs %f0, %f1, %f10 ! This should cause fp divide-by-0 exception if enabled
217	setx user_scratch, %l0, %l5 ! scratch
218	stx %fsr, [%l5+0x0]
219	ldx [%l5+0x0], %fsr ! Need to test the sync operation
220
221	! Enable mask
222
223	ld [%l3+0x0], %fsr ! Read it from memory
224	fdivs %f0, %f1, %f10 ! This should cause fp divide-by-0 exception if enabled
225	setx user_scratch, %l0, %l5 ! scratch
226	stx %fsr, [%l5+0x8]
227	ldx [%l5+0x8], %g1 ! Just read them from memory
228	ldx [%l5+0x0], %g2 ! Just read them from memory
229
230	! Disable mask
231
232	ld [%l4+0x0], %fsr ! Read it from memory
233	fdivs %f0, %f1, %f10 ! This should cause fp divide-by-0 exception if enabled
234
235
236	! Disable mask
237
238
239	/*******************************************************
240	* Exit code
241	*******************************************************/
242
243	test_pass:
244	ta T_GOOD_TRAP
245
246	test_fail:
247	ta T_BAD_TRAP
248	/*******************************************************
249	* Data section
250	*******************************************************/
251
252	.data
253
254	data0:
255	.word 0xffffffff ! -NaN (Quiet) (S = 1, E = 255, F > 0) 00
256	.word 0xffc00001 ! -NaN (Quiet) (S = 1, E = 255, F > 0) 04
257	.word 0xffc00000 ! -NaN (Indeterminate) (S = 1, E = 255, F > 0) 08
258	.word 0xffbfffff ! -NaN (Signaling) (S = 1, E = 255, F > 0) 0c
259	.word 0xff800001 ! -NaN (Signaling) (S = 1, E = 255, F > 0) 10
260	.word 0xff800000 ! -ve Infinity (ovf) (S = 1, E = 255, F = 0) 14
261	.word 0xff7fffff ! -ve normalized (S = 1, 0 < E < 255) 18
262	.word 0x80800000 ! -ve normalized (S = 1, 0 < E < 255) 1c
263	.word 0x807fffff ! -ve denormalized (S = 1, E=0, F is non-zero) 20
264	.word 0x80000001 ! -ve denormalized (S = 1, E=0, F is non-zero) 24
265	.word 0x80000000 ! -ve Underflow (S = 1, E=0, F = 0) 28
266	.word 0x80000000 ! -ve 0 (S = 1, E=0, F = 0) 2c
267	.word 0x00000000 ! +ve 0 (S = 0, E=0, F = 0) 30
268	.word 0x00000000 ! +ve Underflow (S = 0, E=0, F = 0) 34
269	.word 0x00000001 ! +ve denormalized (S = 0, E=0, F is non-zero) 38
270	.word 0x007fffff ! +ve denormalized (S = 0, E=0, F is non-zero) 3c
271	.word 0x00800000 ! +ve normalized (S = 0, 0 < E < 255) 40
272	.word 0x7f7fffff ! +ve normalized (S = 0, 0 < E < 255) 44
273	.word 0x7f800000 ! +ve Infinity (ovf) (S = 0, E = 255, F = 0) 48
274	.word 0x7f800001 ! +NaN (Signaling) (S = 0, E = 255, F > 0) 4c
275	.word 0x7fbfffff ! +NaN (Signaling) (S = 0, E = 255, F > 0) 50
276	.word 0x7fc00000 ! +NaN (Quiet) (S = 0, E = 255, F > 0) 54
277	.word 0x7fffffff ! +NaN (Quiet) (S = 0, E = 255, F > 0) 5c
278
279	.align 256
280
281	ddata0:
282	.xword 0xffffffffffffffff ! -NaN (Quiet) (S = 1, E = 2047, F > 0) 00
283	.xword 0xfff8000000000001 ! -NaN (Quiet) (S = 1, E = 2047, F > 0) 04
284	.xword 0xfff8000000000000 ! -NaN (Indeterminate) (S = 1, E = 2047, F > 0) 08
285	.xword 0xfff7ffffffffffff ! -NaN (Signaling) (S = 1, E = 2047, F > 0) 0c
286	.xword 0xfff0000000000001 ! -NaN (Signaling) (S = 1, E = 2047, F > 0) 10
287	.xword 0xfff0000000000000 ! -ve Infinity (ovf) (S = 1, E = 2047, F = 0) 14
288	.xword 0xffefffffffffffff ! -ve normalized (S = 1, 0 < E < 2047) 18
289	.xword 0x8010000000000000 ! -ve normalized (S = 1, 0 < E < 2047) 1c
290	.xword 0x800fffffffffffff ! -ve denormalized (S = 1, E=0, F is non-zero) 20
291	.xword 0x8000000000000001 ! -ve denormalized (S = 1, E=0, F is non-zero) 24
292	.xword 0x8000000000000000 ! -ve Underflow (S = 1, E=0, F = 0) 28
293	.xword 0x8000000000000000 ! -ve 0 (S = 1, E=0, F = 0) 2c
294	.xword 0x0000000000000000 ! +ve 0 (S = 0, E=0, F = 0) 30
295	.xword 0x0000000000000000 ! +ve Underflow (S = 0, E=0, F = 0) 34
296	.xword 0x0000000000000001 ! +ve denormalized (S = 0, E=0, F is non-zero) 38
297	.xword 0x000fffffffffffff ! +ve denormalized (S = 0, E=0, F is non-zero) 3c
298	.xword 0x0010000000000000 ! +ve normalized (S = 0, 0 < E < 2047) 40
299	.xword 0x7fefffffffffffff ! +ve normalized (S = 0, 0 < E < 2047) 44
300	.xword 0x7ff0000000000000 ! +ve Infinity (ovf) (S = 0, E = 2047, F = 0) 48
301	.xword 0x7ff0000000000001 ! +NaN (Signaling) (S = 0, E = 2047, F > 0) 4c
302	.xword 0x7ff7ffffffffffff ! +NaN (Signaling) (S = 0, E = 2047, F > 0) 50
303	.xword 0x7ff8000000000000 ! +NaN (Quiet) (S = 0, E = 2047, F > 0) 54
304	.xword 0x7fffffffffffffff ! +NaN (Quiet) (S = 0, E = 2047, F > 0) 5c
305
306	.align 256
307
308	data1:
309	.word 0x3f800000 ! 1.0
310	.word 0x00000000 ! 0.0
311	.word 0xbf800000 ! -1.0
312
313
314	.align 128
315
316	fsr_tem_en:
317	.word 0x0f800000 ! TEM - all enabled
318
319	fsr_tem_dis:
320	.word 0x00000000 ! TEM - all disabled
321	.word 0x00000000
322
323	.align 128
324
325	user_scratch:
326	.word 0x00000000
327	.word 0x00000000
328	.word 0x00000000
329	.word 0x00000000
330	.word 0x00000000
331	.word 0x00000000
332	.word 0x00000000
333	.word 0x00000000
334
335
336	/*******************************************************
337	* My own trap handlers
338	*******************************************************/
339
340
341
342	.global T0_Fp_exception_ieee_754
343	T0_Fp_exception_ieee_754:
344	rdpr %tpc, %i0
345	rdpr %tnpc, %i1
346	rdpr %tstate, %i1
347	rdpr %tt, %i1
348	setx scratch, %l0, %l5 ! scratch
349	stx %fsr, [%l5+0x0]
350	ldx [%l5+0x0], %fsr !
351	done
352	nop
353
354	.data
355	.align 128
356
357	scratch:
358	.word 0x00000000
359	.word 0x00000000
360	.word 0x00000000
361	.word 0x00000000
362	.word 0x00000000
363	.word 0x00000000
364	.word 0x00000000
365	.word 0x00000000