projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: apex_knobs.h | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #ifndef GMMU_DS | |
| 39 | #define GMMU_EN 1 /* global IOMMU enable */ | |
| 40 | #else | |
| 41 | #define GMMU_EN 0 | |
| 42 | #endif | |
| 43 | ||
| 44 | #ifndef MMUC_DS | |
| 45 | #define MMUC_EN 1 /* global iommu cache enable */ | |
| 46 | #else | |
| 47 | #define MMUC_EN 0 | |
| 48 | #endif | |
| 49 | ||
| 50 | #ifndef GBYP_DS | |
| 51 | #define GBYP_EN 1 /* global bypass enable */ | |
| 52 | #else | |
| 53 | #define GBYP_EN 0 | |
| 54 | #endif | |
| 55 | ||
| 56 | #ifndef GINT_DS | |
| 57 | #define GINT_EN 1 /* global completion intx enable */ | |
| 58 | #else | |
| 59 | #define GINT_EN 0 | |
| 60 | #endif | |
| 61 | ||
| 62 | #ifndef GMSI_DS | |
| 63 | #define GMSI_EN 0 /* global completion msi enable */ | |
| 64 | #else | |
| 65 | #define GMSI_EN 0 | |
| 66 | #endif | |
| 67 | ||
| 68 | #ifndef GINTF_DS | |
| 69 | #define GINTF_EN 1 /* global interference enable */ | |
| 70 | #else | |
| 71 | #define GINTF_EN 0 | |
| 72 | #endif | |
| 73 | ||
| 74 | #ifndef GLDST_DS | |
| 75 | #define GLDST_EN 1 /* load store interference enable */ | |
| 76 | #else | |
| 77 | #define GLDST_EN 0 | |
| 78 | #endif | |
| 79 | ||
| 80 | #ifndef GCASA_DS | |
| 81 | #define GCASA_EN 0 /* CASA interference in data area enable */ | |
| 82 | #else | |
| 83 | #define GCASA_EN 1 | |
| 84 | #endif | |
| 85 | ||
| 86 | #ifndef GCAS2_DS | |
| 87 | #define GCAS2_EN 0 /* CASA interference adjacent to data area enable */ | |
| 88 | #else | |
| 89 | #define GCAS2_EN 1 | |
| 90 | #endif | |
| 91 | ||
| 92 | #ifndef GL2IF_DS | |
| 93 | #define GL2IF_EN 1 /* L2 interference enable */ | |
| 94 | #else | |
| 95 | #define GL2IF_EN 0 | |
| 96 | #endif | |
| 97 | ||
| 98 | #ifndef GPIOI_DS | |
| 99 | #define GPIOI_EN 1 /* global PIO interference enable */ | |
| 100 | #else | |
| 101 | #define GPIOI_EN 0 | |
| 102 | #endif | |
| 103 | ||
| 104 | #ifndef PIO00_DS | |
| 105 | #define PIO00_EN 1 /* pio to ncx,ncu,piu csr space enable */ | |
| 106 | #else | |
| 107 | #define PIO00_EN 0 | |
| 108 | #endif | |
| 109 | ||
| 110 | #ifndef PIOCF_DS | |
| 111 | #define PIOCF_EN 1 /* pio to IO space enable (config) */ | |
| 112 | #else | |
| 113 | #define PIOCF_EN 0 | |
| 114 | #endif | |
| 115 | ||
| 116 | #ifndef PIO32_DS | |
| 117 | #define PIO32_EN 0 /* pio to IO space enable (mem32) */ | |
| 118 | #else | |
| 119 | #define PIO32_EN 1 | |
| 120 | #endif | |
| 121 | ||
| 122 | #ifndef PIO64_DS | |
| 123 | #define PIO64_EN 1 /* pio to IO space enable (mem64) */ | |
| 124 | #else | |
| 125 | #define PIO64_EN 0 | |
| 126 | #endif | |
| 127 | ||
| 128 | #ifndef E0IMU_DS | |
| 129 | #define E0IMU_EN 1 /* per engine IOMMU enable */ | |
| 130 | #else | |
| 131 | #define E0IMU_EN 0 | |
| 132 | #endif | |
| 133 | ||
| 134 | #ifndef E0PSZ_DS | |
| 135 | #define E0PSZ_EN 1 /* per engine IOMMU page size random selection enable */ | |
| 136 | #else | |
| 137 | #define E0IMU_EN 0 | |
| 138 | #endif | |
| 139 | ||
| 140 | #ifndef E0BYP_DS | |
| 141 | #define E0BYP_EN 1 /* per engine bypass enable */ | |
| 142 | #else | |
| 143 | #define E0BYP_EN 0 | |
| 144 | #endif | |
| 145 | ||
| 146 | #ifndef E0INT_DS | |
| 147 | #define E0INT_EN 1 /* per engine completion intx enable */ | |
| 148 | #else | |
| 149 | #define E0INT_EN 0 | |
| 150 | #endif | |
| 151 | ||
| 152 | #ifndef E0MSI_DS | |
| 153 | #define E0MSI_EN 0 /* per engine completion msi enable */ | |
| 154 | #else | |
| 155 | #define E0MSI_EN 0 | |
| 156 | #endif | |
| 157 | ||
| 158 | #ifndef E0PLD_DS | |
| 159 | #define E0PLD_EN 1 /* per engine payload size floor enable */ | |
| 160 | #else | |
| 161 | #define E0PLD_EN 0 | |
| 162 | #endif | |
| 163 | ||
| 164 | #ifndef E0FPL_DS | |
| 165 | #define E0FPL_EN 0 /* per engine fixed payload size enable */ | |
| 166 | #else | |
| 167 | #define E0FPL_EN 1 | |
| 168 | #endif | |
| 169 | ||
| 170 | #ifndef E0BYC_DS | |
| 171 | #define E0BYC_EN 1 /* per engine byte count floor enable */ | |
| 172 | #else | |
| 173 | #define E0BYC_EN 0 | |
| 174 | #endif | |
| 175 | ||
| 176 | #ifndef E0FBC_DS | |
| 177 | #define E0FBC_EN 1 /* per engine fixed byte count enable */ | |
| 178 | #else | |
| 179 | #define E0FBC_EN 0 | |
| 180 | #endif | |
| 181 | ||
| 182 | #ifndef E0ROF_DS | |
| 183 | #define E0ROF_EN 1 /* per engine random offset enable */ | |
| 184 | #else | |
| 185 | #define E0ROF_EN 0 | |
| 186 | #endif | |
| 187 | ||
| 188 | ||
| 189 | #ifndef E0DOMASK | |
| 190 | #define E0DOMASK 0x7fc /* per engine data offset mask */ | |
| 191 | #endif | |
| 192 | ||
| 193 | #ifndef E0RRD_DS | |
| 194 | #define E0RRD_EN 1 /* per engine PIO read return delay floor enable */ | |
| 195 | #else | |
| 196 | #define E0RRD_EN 0 | |
| 197 | #endif | |
| 198 | ||
| 199 | #ifndef E0DMW_DS | |
| 200 | #define E0DMW_EN 1 /* per engine dma memory write enable */ | |
| 201 | #else | |
| 202 | #define E0DMW_EN 0 | |
| 203 | #endif | |
| 204 | ||
| 205 | #ifndef E0DMR_DS | |
| 206 | #define E0DMR_EN 1 /* per engine dma memory read enable */ | |
| 207 | #else | |
| 208 | #define E0DMR_EN 0 | |
| 209 | #endif | |
| 210 | ||
| 211 | #ifndef E0ROP_DS | |
| 212 | #define E0ROP_EN 1 /* per engine random operation selection */ | |
| 213 | #else | |
| 214 | #define E0ROP_EN 0 | |
| 215 | #endif | |
| 216 | ||
| 217 | #ifndef E0FIT_DS | |
| 218 | #define E0FIT_EN 0 /* user specified fixed interrupt thread */ | |
| 219 | #else | |
| 220 | #define E0FIT_EN 1 | |
| 221 | #endif | |
| 222 | ||
| 223 | #ifndef E0M64_DS | |
| 224 | #define E0M64_EN 1 /* mem64 memory block enable */ | |
| 225 | #else | |
| 226 | #define E0M64_EN 0 | |
| 227 | #endif | |
| 228 | ||
| 229 | #ifndef E0M32_DS | |
| 230 | #define E0M32_EN 0 /* mem32 memory block enable */ | |
| 231 | #else | |
| 232 | #define E0M32_EN 1 | |
| 233 | #endif | |
| 234 | ||
| 235 | #ifndef E0RIT_DS | |
| 236 | #define E0RIT_EN 1 /* per engine random interrupt thread selection */ | |
| 237 | #else | |
| 238 | #define E0RIT_EN 0 | |
| 239 | #endif | |
| 240 | ||
| 241 | #ifndef TROE_DS | |
| 242 | #define TROE_EN 0 /* tte relaxed ordering enable */ | |
| 243 | #else | |
| 244 | #define TROE_EN 1 | |
| 245 | #endif | |
| 246 | ||
| 247 | #ifndef TROR_DS | |
| 248 | #define TROR_EN 1 /* tte relaxed ordering randomize */ | |
| 249 | #else | |
| 250 | #define TROR_EN 0 | |
| 251 | #endif | |
| 252 | ||
| 253 | #ifndef E0RRS_DS | |
| 254 | #define E0RRS_EN 0 /* bobo random request size enable */ | |
| 255 | #else | |
| 256 | #define E0RRS_EN 1 | |
| 257 | #endif | |
| 258 | ||
| 259 | #ifndef E0RRC_DS | |
| 260 | #define E0RRC_EN 0 /* bobo random request count enable */ | |
| 261 | #else | |
| 262 | #define E0RRC_EN 1 | |
| 263 | #endif | |
| 264 | ||
| 265 | #ifndef RREQD_DS | |
| 266 | #define RREQD_EN 0 /* bobo random request delay enable */ | |
| 267 | #else | |
| 268 | #define RREQD_EN 1 | |
| 269 | #endif | |
| 270 | ||
| 271 | #ifndef DROE_DS | |
| 272 | #define DROE_EN 0 /* dev relaxed ordering enable */ | |
| 273 | #else | |
| 274 | #define DROE_EN 1 | |
| 275 | #endif | |
| 276 | ||
| 277 | #ifndef DROR_DS | |
| 278 | #define DROR_EN 1 /* dev relaxed ordering randomize */ | |
| 279 | #else | |
| 280 | #define DROR_EN 0 | |
| 281 | #endif | |
| 282 | ||
| 283 | #ifndef TTEP2_DS | |
| 284 | #define TTEP2_EN 0 /* enable random tte flush */ | |
| 285 | #else | |
| 286 | #define TTEP2_EN 1 | |
| 287 | #endif | |
| 288 | ||
| 289 | #ifndef TSBP2_DS | |
| 290 | #define TSBP2_EN 0 /* enable random tte cas */ | |
| 291 | #else | |
| 292 | #define TSBP2_EN 1 | |
| 293 | #endif | |
| 294 | ||
| 295 | #ifndef INTP2_DS | |
| 296 | #define INTP2_EN 0 /* enable random io mondos */ | |
| 297 | #else | |
| 298 | #define INTP2_EN 1 | |
| 299 | #endif | |
| 300 | ||
| 301 | #ifndef IGNERR_DS | |
| 302 | #define IGNERR_EN 0 /* ignore errors */ | |
| 303 | #else | |
| 304 | #define IGNERR_EN 1 | |
| 305 | #endif | |
| 306 | ||
| 307 | #ifndef E0DCP_DS | |
| 308 | #define E0DCP_EN 0 /* enable dma copy operation */ | |
| 309 | #else | |
| 310 | #define E0DCP_EN 1 | |
| 311 | #endif | |
| 312 | ||
| 313 | #ifndef HALT_DS | |
| 314 | #define HALT_EN 0 /* enable halt instruction */ | |
| 315 | #else | |
| 316 | #define HALT_EN 1 | |
| 317 | #endif | |
| 318 | ||
| 319 | #ifndef BLKLS_DS | |
| 320 | #define BLKLS_EN 0 /* enable block load store */ | |
| 321 | #else | |
| 322 | #define BLKLS_EN 1 | |
| 323 | #endif | |
| 324 | ||
| 325 | #ifndef SU4V_DS | |
| 326 | #define SU4V_EN 1 /* enable sun4v mode iommu */ | |
| 327 | #else | |
| 328 | #define SU4V_EN 0 | |
| 329 | #endif | |
| 330 | ||
| 331 | #ifndef MPS0_DS | |
| 332 | #define MPS0_EN 1 /* IOMMU TTE page size 0 (8K) enable */ | |
| 333 | #else | |
| 334 | #define MPS0_EN 0 | |
| 335 | #endif | |
| 336 | ||
| 337 | #ifndef MPS1_DS | |
| 338 | #define MPS1_EN 1 /* IOMMU TTE page size 1 (64K) enable */ | |
| 339 | #else | |
| 340 | #define MPS1_EN 0 | |
| 341 | #endif | |
| 342 | ||
| 343 | #ifndef MPS3_DS | |
| 344 | #define MPS3_EN 1 /* IOMMU TTE page size 3 (4M) enable */ | |
| 345 | #else | |
| 346 | #define MPS3_EN 0 | |
| 347 | #endif | |
| 348 | ||
| 349 | #ifndef MPS5_DS | |
| 350 | #define MPS5_EN 1 /* IOMMU TTE page size 5 (256M) enable */ | |
| 351 | #else | |
| 352 | #define MPS5_EN 0 | |
| 353 | #endif | |
| 354 | ||
| 355 | #ifndef PIODW_DS | |
| 356 | #define PIODW_EN 0 /* PIO double word read/write enable */ | |
| 357 | #else | |
| 358 | #define PIODW_EN 1 | |
| 359 | #endif | |
| 360 | ||
| 361 | #ifndef PIOWD_DS | |
| 362 | #define PIOWD_EN 1 /* PIO word read/write enable */ | |
| 363 | #else | |
| 364 | #define PIOWD_EN 0 | |
| 365 | #endif | |
| 366 | ||
| 367 | #ifndef PIOHW_DS | |
| 368 | #define PIOHW_EN 0 /* PIO half word read/write enable */ | |
| 369 | #else | |
| 370 | #define PIOHW_EN 1 | |
| 371 | #endif | |
| 372 | ||
| 373 | #ifndef PIOBY_DS | |
| 374 | #define PIOBY_EN 0 /* PIO byte read/write enable */ | |
| 375 | #else | |
| 376 | #define PIOBY_EN 1 | |
| 377 | #endif | |
| 378 | ||
| 379 | #ifndef PSHR_DS | |
| 380 | #define PSHR_EN 0 /* Pseudo share interference enable */ | |
| 381 | #else | |
| 382 | #define PSHR_EN 1 | |
| 383 | #endif | |
| 384 | ||
| 385 | ||
| 386 | ||
| 387 | ||
| 388 | #ifndef PIORRD | |
| 389 | #define PIORRD 0x0f | |
| 390 | #endif | |
| 391 | ||
| 392 | /* | |
| 393 | Maximum data xfer length must be word aligned & < (0x80000 - (0x2000 + 8)). | |
| 394 | 7dff8 or less should work. | |
| 395 | */ | |
| 396 | #ifndef LNGTH_MASK | |
| 397 | #define LNGTH_MASK 0x3fc | |
| 398 | #elif (LNGTH_MASK > 0x3fffc) | |
| 399 | #undef LNGTH_MASK | |
| 400 | #define LNGTH_MASK 0x3fffc | |
| 401 | #endif | |
| 402 | ||
| 403 | #ifndef LNGTH_MIN | |
| 404 | #define LNGTH_MIN 0x0800 | |
| 405 | #elif (LNGTH_MIN < 4) | |
| 406 | #undef LNGTH_MIN | |
| 407 | #define LNGTH_MIN 4 | |
| 408 | #elif (LNGTH_MIN > 0x40000) | |
| 409 | #undef LNGTH_MIN | |
| 410 | #define LNGTH_MIN 0x40000 | |
| 411 | #endif | |
| 412 | ||
| 413 | #ifndef PAYLD_MIN | |
| 414 | #define PAYLD_MIN 0x40 | |
| 415 | #endif | |
| 416 | ||
| 417 | #ifndef DOS_MSK | |
| 418 | #define DOS_MSK 0x1ffc | |
| 419 | #endif | |
| 420 | ||
| 421 | #ifndef FIX_OFFSET | |
| 422 | #define FIX_OFFSET 0x800 | |
| 423 | #endif | |
| 424 | ||
| 425 | #ifndef FIX_BCNT | |
| 426 | #define FIX_BCNT 0x40 | |
| 427 | #endif | |
| 428 | ||
| 429 | #ifndef SWCHK_DISABLE | |
| 430 | #define SW_CHK_EN 1 | |
| 431 | #else | |
| 432 | #define SW_CHK_EN 0 | |
| 433 | #endif | |
| 434 | ||
| 435 | #ifndef CAN_SEL | |
| 436 | #define CAN_SEL 0 | |
| 437 | #endif | |
| 438 | ||
| 439 | #ifndef INT_TH | |
| 440 | #define INT_TH 0 | |
| 441 | #endif | |
| 442 | ||
| 443 | #ifndef MASK0 | |
| 444 | #define MASK0 0 | |
| 445 | #endif | |
| 446 | ||
| 447 | #ifndef MASK1 | |
| 448 | #define MASK1 0 | |
| 449 | #endif | |
| 450 | ||
| 451 | #ifndef REQ_DLY_REG | |
| 452 | #define REQ_DLY_REG 0x000f0000 | |
| 453 | #endif | |
| 454 | ||
| 455 | #ifndef PAYLD_MAX | |
| 456 | #define PAYLD_MAX 0x80 | |
| 457 | #endif | |
| 458 | ||
| 459 | #ifndef PAYLD_MSK | |
| 460 | #define PAYLD_MSK 0x7f | |
| 461 | #endif | |
| 462 | ||
| 463 | #ifndef NU0D | |
| 464 | #define NU0D 0 | |
| 465 | #endif | |
| 466 | ||
| 467 | #ifndef NU0E | |
| 468 | #define NU0E 0 | |
| 469 | #endif | |
| 470 | ||
| 471 | #ifndef NU0F | |
| 472 | #define NU0F 0 | |
| 473 | #endif | |
| 474 | ||
| 475 | ||
| 476 | ||
| 477 | ||
| 478 | ||
| 479 | ||
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