projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: dmu_peu_regs.h | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | !! | |
| 39 | !! This file is generated by somePerson using the command: | |
| 40 | !! csr2assembly_reg_defines.pl /import/n2-svl-localdir2/somePerson/n2cdmspp/verif/env/dmu/vera/csrtool /import/n2-svl-localdir2/somePerson/n2cdmspp/verif/env/ilu_peu/vera/csrtool | |
| 41 | !! | |
| 42 | ||
| 43 | !! Register definitions from :/verif/env/dmu/vera/csrtool/cru_a.csr_define.vri 1.1 | |
| 44 | ||
| 45 | ||
| 46 | #define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_ADDR mpeval(0x00653000 + N2_DMU_PEU_BASE_ADDR) | |
| 47 | #define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_WRITE_MASK 0x00000000000003ff | |
| 48 | #define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_POR_VALUE 0x0000000000000000 | |
| 49 | ||
| 50 | #define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_ADDR mpeval(0x00653008 + N2_DMU_PEU_BASE_ADDR) | |
| 51 | #define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_WRITE_MASK 0x00000000000003ff | |
| 52 | #define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_POR_VALUE 0x0000000000000000 | |
| 53 | ||
| 54 | #define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_ADDR mpeval(0x00653100 + N2_DMU_PEU_BASE_ADDR) | |
| 55 | #define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_WRITE_MASK 0x00000000ff00ffff | |
| 56 | #define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_POR_VALUE 0x0000000000000000 | |
| 57 | ||
| 58 | ||
| 59 | !! Register definitions from :/verif/env/dmu/vera/csrtool/csr_a.csr_define.vri 1.3 | |
| 60 | ||
| 61 | ||
| 62 | #define FIRE_DLC_MMU_CSR_A_CTL_ADDR mpeval(0x00640000 + N2_DMU_PEU_BASE_ADDR) | |
| 63 | #define FIRE_DLC_MMU_CSR_A_CTL_WRITE_MASK 0x00000000000f170f | |
| 64 | #define FIRE_DLC_MMU_CSR_A_CTL_POR_VALUE 0x0000000000000000 | |
| 65 | ||
| 66 | #define FIRE_DLC_MMU_CSR_A_TSB_ADDR mpeval(0x00640008 + N2_DMU_PEU_BASE_ADDR) | |
| 67 | #define FIRE_DLC_MMU_CSR_A_TSB_WRITE_MASK 0x0000007fffffe10f | |
| 68 | #define FIRE_DLC_MMU_CSR_A_TSB_POR_VALUE 0x0000000000000000 | |
| 69 | ||
| 70 | #define FIRE_DLC_MMU_CSR_A_FSH_ADDR mpeval(0x00640100 + N2_DMU_PEU_BASE_ADDR) | |
| 71 | #define FIRE_DLC_MMU_CSR_A_FSH_WRITE_MASK 0x0000007fffffffc0 | |
| 72 | #define FIRE_DLC_MMU_CSR_A_FSH_POR_VALUE 0x0000000000000000 | |
| 73 | ||
| 74 | #define FIRE_DLC_MMU_CSR_A_INV_ADDR mpeval(0x00640108 + N2_DMU_PEU_BASE_ADDR) | |
| 75 | #define FIRE_DLC_MMU_CSR_A_INV_WRITE_MASK 0xffffffffffffffff | |
| 76 | #define FIRE_DLC_MMU_CSR_A_INV_POR_VALUE 0x0000000000000000 | |
| 77 | ||
| 78 | #define FIRE_DLC_MMU_CSR_A_LOG_ADDR mpeval(0x00641000 + N2_DMU_PEU_BASE_ADDR) | |
| 79 | #define FIRE_DLC_MMU_CSR_A_LOG_WRITE_MASK 0x00000000001fffff | |
| 80 | #define FIRE_DLC_MMU_CSR_A_LOG_POR_VALUE 0x00000000001fffff | |
| 81 | ||
| 82 | #define FIRE_DLC_MMU_CSR_A_INT_EN_ADDR mpeval(0x00641008 + N2_DMU_PEU_BASE_ADDR) | |
| 83 | #define FIRE_DLC_MMU_CSR_A_INT_EN_WRITE_MASK 0x001fffff001fffff | |
| 84 | #define FIRE_DLC_MMU_CSR_A_INT_EN_POR_VALUE 0x0000000000000000 | |
| 85 | ||
| 86 | #define FIRE_DLC_MMU_CSR_A_EN_ERR_ADDR mpeval(0x00641010 + N2_DMU_PEU_BASE_ADDR) | |
| 87 | #define FIRE_DLC_MMU_CSR_A_EN_ERR_WRITE_MASK 0x0000000000000000 | |
| 88 | #define FIRE_DLC_MMU_CSR_A_EN_ERR_POR_VALUE 0x0000000000000000 | |
| 89 | ||
| 90 | #define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_ADDR mpeval(0x00641018 + N2_DMU_PEU_BASE_ADDR) | |
| 91 | #define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_WRITE_MASK 0x0000000000000000 | |
| 92 | #define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000 | |
| 93 | ||
| 94 | #define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_ADDR mpeval(0x00641020 + N2_DMU_PEU_BASE_ADDR) | |
| 95 | #define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_WRITE_MASK 0x001fffff001fffff | |
| 96 | #define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000 | |
| 97 | ||
| 98 | #define FIRE_DLC_MMU_CSR_A_FLTA_ADDR mpeval(0x00641028 + N2_DMU_PEU_BASE_ADDR) | |
| 99 | #define FIRE_DLC_MMU_CSR_A_FLTA_WRITE_MASK 0xfffffffffffffffc | |
| 100 | #define FIRE_DLC_MMU_CSR_A_FLTA_POR_VALUE 0x0000000000000000 | |
| 101 | ||
| 102 | #define FIRE_DLC_MMU_CSR_A_FLTS_ADDR mpeval(0x00641030 + N2_DMU_PEU_BASE_ADDR) | |
| 103 | #define FIRE_DLC_MMU_CSR_A_FLTS_WRITE_MASK 0x000001ff007fffff | |
| 104 | #define FIRE_DLC_MMU_CSR_A_FLTS_POR_VALUE 0x0000000000000000 | |
| 105 | ||
| 106 | #define FIRE_DLC_MMU_CSR_A_PRFC_ADDR mpeval(0x00642000 + N2_DMU_PEU_BASE_ADDR) | |
| 107 | #define FIRE_DLC_MMU_CSR_A_PRFC_WRITE_MASK 0x000000000000ffff | |
| 108 | #define FIRE_DLC_MMU_CSR_A_PRFC_POR_VALUE 0x0000000000000000 | |
| 109 | ||
| 110 | #define FIRE_DLC_MMU_CSR_A_PRF0_ADDR mpeval(0x00642008 + N2_DMU_PEU_BASE_ADDR) | |
| 111 | #define FIRE_DLC_MMU_CSR_A_PRF0_WRITE_MASK 0xffffffffffffffff | |
| 112 | #define FIRE_DLC_MMU_CSR_A_PRF0_POR_VALUE 0x0000000000000000 | |
| 113 | ||
| 114 | #define FIRE_DLC_MMU_CSR_A_PRF1_ADDR mpeval(0x00642010 + N2_DMU_PEU_BASE_ADDR) | |
| 115 | #define FIRE_DLC_MMU_CSR_A_PRF1_WRITE_MASK 0xffffffffffffffff | |
| 116 | #define FIRE_DLC_MMU_CSR_A_PRF1_POR_VALUE 0x0000000000000000 | |
| 117 | ||
| 118 | #define FIRE_DLC_MMU_CSR_A_VTB_ADDR mpeval(0x00646000 + N2_DMU_PEU_BASE_ADDR) | |
| 119 | !! This register maps to a ram with a depth of: 64 | |
| 120 | #define FIRE_DLC_MMU_CSR_A_VTB_WRITE_MASK 0x01fffffffffff801 | |
| 121 | #define FIRE_DLC_MMU_CSR_A_VTB_POR_VALUE 0x0000000000000000 | |
| 122 | ||
| 123 | #define FIRE_DLC_MMU_CSR_A_PTB_ADDR mpeval(0x00647000 + N2_DMU_PEU_BASE_ADDR) | |
| 124 | !! This register maps to a ram with a depth of: 64 | |
| 125 | #define FIRE_DLC_MMU_CSR_A_PTB_WRITE_MASK 0x0000007fffffffc1 | |
| 126 | #define FIRE_DLC_MMU_CSR_A_PTB_POR_VALUE 0x0000000000000000 | |
| 127 | ||
| 128 | #define FIRE_DLC_MMU_CSR_A_TDB_ADDR mpeval(0x00648000 + N2_DMU_PEU_BASE_ADDR) | |
| 129 | !! This register maps to a ram with a depth of: 512 | |
| 130 | #define FIRE_DLC_MMU_CSR_A_TDB_WRITE_MASK 0xfffff07fffffe03f | |
| 131 | !! contains x #define FIRE_DLC_MMU_CSR_A_TDB_POR_VALUE 0xxxxxxxxxxxxxxxxxxxxx00000xxxxxxxxxxxxxxxxxxxxxxxxxx0000000xxxxxx | |
| 132 | ||
| 133 | #define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR mpeval(0x00649000 + N2_DMU_PEU_BASE_ADDR) | |
| 134 | !! This register maps to a ram with a depth of: 16 | |
| 135 | #define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_WRITE_MASK 0x1f1f1f1f1f1f1f1f | |
| 136 | #define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_POR_VALUE 0x0000000000000000 | |
| 137 | ||
| 138 | #define FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR mpeval(0x00649100 + N2_DMU_PEU_BASE_ADDR) | |
| 139 | !! This register maps to a ram with a depth of: 32 | |
| 140 | #define FIRE_DLC_MMU_CSR_A_IOTSBDESC_WRITE_MASK 0x8fffffffffffffff | |
| 141 | #define FIRE_DLC_MMU_CSR_A_IOTSBDESC_POR_VALUE 0x0000000000000000 | |
| 142 | ||
| 143 | ||
| 144 | !! Register definitions from :/verif/env/dmu/vera/csrtool/eqs_a.csr_define.vri 1.1 | |
| 145 | ||
| 146 | ||
| 147 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_ADDR mpeval(0x00610000 + N2_DMU_PEU_BASE_ADDR) | |
| 148 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_WRITE_MASK 0xfffffffffff80000 | |
| 149 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_POR_VALUE 0x0000000000000000 | |
| 150 | ||
| 151 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_ADDR mpeval(0x00611000 + N2_DMU_PEU_BASE_ADDR) | |
| 152 | !! This register maps to a ram with a depth of: 36 | |
| 153 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_WRITE_MASK 0x0200100000000000 | |
| 154 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_POR_VALUE 0x0000000000000000 | |
| 155 | ||
| 156 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_ADDR mpeval(0x00611200 + N2_DMU_PEU_BASE_ADDR) | |
| 157 | !! This register maps to a ram with a depth of: 36 | |
| 158 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_WRITE_MASK 0x0200900000000000 | |
| 159 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_POR_VALUE 0x0000000000000000 | |
| 160 | ||
| 161 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_ADDR mpeval(0x00611400 + N2_DMU_PEU_BASE_ADDR) | |
| 162 | !! This register maps to a ram with a depth of: 36 | |
| 163 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_WRITE_MASK 0x0000000000000000 | |
| 164 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_POR_VALUE 0x0000000000000001 | |
| 165 | ||
| 166 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_ADDR mpeval(0x00611600 + N2_DMU_PEU_BASE_ADDR) | |
| 167 | !! This register maps to a ram with a depth of: 36 | |
| 168 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_WRITE_MASK 0x000000000000007f | |
| 169 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_POR_VALUE 0x0000000000000000 | |
| 170 | ||
| 171 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_ADDR mpeval(0x00611800 + N2_DMU_PEU_BASE_ADDR) | |
| 172 | !! This register maps to a ram with a depth of: 36 | |
| 173 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_WRITE_MASK 0x000000000000007f | |
| 174 | #define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_POR_VALUE 0x0000000000000000 | |
| 175 | ||
| 176 | ||
| 177 | !! Register definitions from :/verif/env/dmu/vera/csrtool/ics_a.csr_define.vri 1.3 | |
| 178 | ||
| 179 | ||
| 180 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR mpeval(0x00631000 + N2_DMU_PEU_BASE_ADDR) | |
| 181 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_WRITE_MASK 0x0000000000007fff | |
| 182 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_POR_VALUE 0x0000000000007fff | |
| 183 | ||
| 184 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR mpeval(0x00631008 + N2_DMU_PEU_BASE_ADDR) | |
| 185 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_WRITE_MASK 0x00007fff00007fff | |
| 186 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_POR_VALUE 0x0000000000000000 | |
| 187 | ||
| 188 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR mpeval(0x00631010 + N2_DMU_PEU_BASE_ADDR) | |
| 189 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_WRITE_MASK 0x0000000000000000 | |
| 190 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_POR_VALUE 0x0000000000000000 | |
| 191 | ||
| 192 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR mpeval(0x00631018 + N2_DMU_PEU_BASE_ADDR) | |
| 193 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WRITE_MASK 0x0000000000000000 | |
| 194 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_POR_VALUE 0x0000000000000000 | |
| 195 | ||
| 196 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR mpeval(0x00631020 + N2_DMU_PEU_BASE_ADDR) | |
| 197 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_WRITE_MASK 0x00007fff00007fff | |
| 198 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_POR_VALUE 0x0000000000000000 | |
| 199 | ||
| 200 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR mpeval(0x00631028 + N2_DMU_PEU_BASE_ADDR) | |
| 201 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_WRITE_MASK 0xffffffffffffffff | |
| 202 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_POR_VALUE 0x0000000000000000 | |
| 203 | ||
| 204 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_ADDR mpeval(0x00631030 + N2_DMU_PEU_BASE_ADDR) | |
| 205 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_WRITE_MASK 0xffffffffffff003f | |
| 206 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_POR_VALUE 0x0000000000000000 | |
| 207 | ||
| 208 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_ADDR mpeval(0x00631038 + N2_DMU_PEU_BASE_ADDR) | |
| 209 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_WRITE_MASK 0x000000000000003f | |
| 210 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_POR_VALUE 0x0000000000000000 | |
| 211 | ||
| 212 | #define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_ADDR mpeval(0x00631800 + N2_DMU_PEU_BASE_ADDR) | |
| 213 | #define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_WRITE_MASK 0xc000000000000003 | |
| 214 | #define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_POR_VALUE 0x0000000000000000 | |
| 215 | ||
| 216 | #define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_ADDR mpeval(0x00631808 + N2_DMU_PEU_BASE_ADDR) | |
| 217 | #define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_WRITE_MASK 0x0000000000000000 | |
| 218 | #define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_POR_VALUE 0x0000000000000000 | |
| 219 | ||
| 220 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR mpeval(0x00632000 + N2_DMU_PEU_BASE_ADDR) | |
| 221 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_WRITE_MASK 0x000000000000ffff | |
| 222 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_POR_VALUE 0x0000000000000000 | |
| 223 | ||
| 224 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_ADDR mpeval(0x00632008 + N2_DMU_PEU_BASE_ADDR) | |
| 225 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_WRITE_MASK 0xffffffffffffffff | |
| 226 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_POR_VALUE 0x0000000000000000 | |
| 227 | ||
| 228 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_ADDR mpeval(0x00632010 + N2_DMU_PEU_BASE_ADDR) | |
| 229 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_WRITE_MASK 0xffffffffffffffff | |
| 230 | #define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_POR_VALUE 0x0000000000000000 | |
| 231 | ||
| 232 | #define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR mpeval(0x00634000 + N2_DMU_PEU_BASE_ADDR) | |
| 233 | #define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_WRITE_MASK 0x00000000ffff0000 | |
| 234 | #define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_POR_VALUE 0x0000000000000000 | |
| 235 | ||
| 236 | #define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR mpeval(0x00634008 + N2_DMU_PEU_BASE_ADDR) | |
| 237 | #define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_WRITE_MASK 0xffffffffffff0000 | |
| 238 | #define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_POR_VALUE 0x0000000000000000 | |
| 239 | ||
| 240 | #define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR mpeval(0x00634018 + N2_DMU_PEU_BASE_ADDR) | |
| 241 | #define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_WRITE_MASK 0xffffffffffffffff | |
| 242 | #define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_POR_VALUE 0x0000000000000000 | |
| 243 | ||
| 244 | ||
| 245 | !! Register definitions from :/verif/env/dmu/vera/csrtool/intx_a.csr_define.vri 1.1 | |
| 246 | ||
| 247 | ||
| 248 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR mpeval(0x0060b000 + N2_DMU_PEU_BASE_ADDR) | |
| 249 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_WRITE_MASK 0x0000000000000000 | |
| 250 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_POR_VALUE 0x0000000000000000 | |
| 251 | ||
| 252 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_ADDR mpeval(0x0060b008 + N2_DMU_PEU_BASE_ADDR) | |
| 253 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_WRITE_MASK 0x0000000000000000 | |
| 254 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_POR_VALUE 0x0000000000000000 | |
| 255 | ||
| 256 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_ADDR mpeval(0x0060b010 + N2_DMU_PEU_BASE_ADDR) | |
| 257 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_WRITE_MASK 0x0000000000000000 | |
| 258 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_POR_VALUE 0x0000000000000000 | |
| 259 | ||
| 260 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_ADDR mpeval(0x0060b018 + N2_DMU_PEU_BASE_ADDR) | |
| 261 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_WRITE_MASK 0x0000000000000000 | |
| 262 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_POR_VALUE 0x0000000000000000 | |
| 263 | ||
| 264 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_ADDR mpeval(0x0060b020 + N2_DMU_PEU_BASE_ADDR) | |
| 265 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_WRITE_MASK 0x0000000000000000 | |
| 266 | #define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_POR_VALUE 0x0000000000000000 | |
| 267 | ||
| 268 | ||
| 269 | !! Register definitions from :/verif/env/dmu/vera/csrtool/iss_a.csr_define.vri 1.1 | |
| 270 | ||
| 271 | ||
| 272 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_ADDR mpeval(0x006010a0 + N2_DMU_PEU_BASE_ADDR) | |
| 273 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_WRITE_MASK 0x80000000fe0003c0 | |
| 274 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_POR_VALUE 0x0000000000000000 | |
| 275 | ||
| 276 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_ADDR mpeval(0x006010a8 + N2_DMU_PEU_BASE_ADDR) | |
| 277 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_WRITE_MASK 0x80000000fe0003c0 | |
| 278 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_POR_VALUE 0x0000000000000000 | |
| 279 | ||
| 280 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_ADDR mpeval(0x006010b0 + N2_DMU_PEU_BASE_ADDR) | |
| 281 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_WRITE_MASK 0x80000000fe0003c0 | |
| 282 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_POR_VALUE 0x0000000000000000 | |
| 283 | ||
| 284 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_ADDR mpeval(0x006010b8 + N2_DMU_PEU_BASE_ADDR) | |
| 285 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_WRITE_MASK 0x80000000fe0003c0 | |
| 286 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_POR_VALUE 0x0000000000000000 | |
| 287 | ||
| 288 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_ADDR mpeval(0x006010c0 + N2_DMU_PEU_BASE_ADDR) | |
| 289 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_WRITE_MASK 0x80000000fe0003c0 | |
| 290 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_POR_VALUE 0x0000000000000000 | |
| 291 | ||
| 292 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_ADDR mpeval(0x006010c8 + N2_DMU_PEU_BASE_ADDR) | |
| 293 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_WRITE_MASK 0x80000000fe0003c0 | |
| 294 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_POR_VALUE 0x0000000000000000 | |
| 295 | ||
| 296 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_ADDR mpeval(0x006010d0 + N2_DMU_PEU_BASE_ADDR) | |
| 297 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_WRITE_MASK 0x80000000fe0003c0 | |
| 298 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_POR_VALUE 0x0000000000000000 | |
| 299 | ||
| 300 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_ADDR mpeval(0x006010d8 + N2_DMU_PEU_BASE_ADDR) | |
| 301 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_WRITE_MASK 0x80000000fe0003c0 | |
| 302 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_POR_VALUE 0x0000000000000000 | |
| 303 | ||
| 304 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_ADDR mpeval(0x006010e0 + N2_DMU_PEU_BASE_ADDR) | |
| 305 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_WRITE_MASK 0x80000000fe0003c0 | |
| 306 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_POR_VALUE 0x0000000000000000 | |
| 307 | ||
| 308 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_ADDR mpeval(0x006010e8 + N2_DMU_PEU_BASE_ADDR) | |
| 309 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_WRITE_MASK 0x80000000fe0003c0 | |
| 310 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_POR_VALUE 0x0000000000000000 | |
| 311 | ||
| 312 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_ADDR mpeval(0x006010f0 + N2_DMU_PEU_BASE_ADDR) | |
| 313 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_WRITE_MASK 0x80000000fe0003c0 | |
| 314 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_POR_VALUE 0x0000000000000000 | |
| 315 | ||
| 316 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_ADDR mpeval(0x006010f8 + N2_DMU_PEU_BASE_ADDR) | |
| 317 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_WRITE_MASK 0x80000000fe0003c0 | |
| 318 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_POR_VALUE 0x0000000000000000 | |
| 319 | ||
| 320 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_ADDR mpeval(0x00601100 + N2_DMU_PEU_BASE_ADDR) | |
| 321 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_WRITE_MASK 0x80000000fe0003c0 | |
| 322 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_POR_VALUE 0x0000000000000000 | |
| 323 | ||
| 324 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_ADDR mpeval(0x00601108 + N2_DMU_PEU_BASE_ADDR) | |
| 325 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_WRITE_MASK 0x80000000fe0003c0 | |
| 326 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_POR_VALUE 0x0000000000000000 | |
| 327 | ||
| 328 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_ADDR mpeval(0x00601110 + N2_DMU_PEU_BASE_ADDR) | |
| 329 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_WRITE_MASK 0x80000000fe0003c0 | |
| 330 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_POR_VALUE 0x0000000000000000 | |
| 331 | ||
| 332 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_ADDR mpeval(0x00601118 + N2_DMU_PEU_BASE_ADDR) | |
| 333 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_WRITE_MASK 0x80000000fe0003c0 | |
| 334 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_POR_VALUE 0x0000000000000000 | |
| 335 | ||
| 336 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_ADDR mpeval(0x00601120 + N2_DMU_PEU_BASE_ADDR) | |
| 337 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_WRITE_MASK 0x80000000fe0003c0 | |
| 338 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_POR_VALUE 0x0000000000000000 | |
| 339 | ||
| 340 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_ADDR mpeval(0x00601128 + N2_DMU_PEU_BASE_ADDR) | |
| 341 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_WRITE_MASK 0x80000000fe0003c0 | |
| 342 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_POR_VALUE 0x0000000000000000 | |
| 343 | ||
| 344 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_ADDR mpeval(0x00601130 + N2_DMU_PEU_BASE_ADDR) | |
| 345 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_WRITE_MASK 0x80000000fe0003c0 | |
| 346 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_POR_VALUE 0x0000000000000000 | |
| 347 | ||
| 348 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_ADDR mpeval(0x00601138 + N2_DMU_PEU_BASE_ADDR) | |
| 349 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_WRITE_MASK 0x80000000fe0003c0 | |
| 350 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_POR_VALUE 0x0000000000000000 | |
| 351 | ||
| 352 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_ADDR mpeval(0x00601140 + N2_DMU_PEU_BASE_ADDR) | |
| 353 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_WRITE_MASK 0x80000000fe0003c0 | |
| 354 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_POR_VALUE 0x0000000000000000 | |
| 355 | ||
| 356 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_ADDR mpeval(0x00601148 + N2_DMU_PEU_BASE_ADDR) | |
| 357 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_WRITE_MASK 0x80000000fe0003c0 | |
| 358 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_POR_VALUE 0x0000000000000000 | |
| 359 | ||
| 360 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_ADDR mpeval(0x00601150 + N2_DMU_PEU_BASE_ADDR) | |
| 361 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_WRITE_MASK 0x80000000fe0003c0 | |
| 362 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_POR_VALUE 0x0000000000000000 | |
| 363 | ||
| 364 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_ADDR mpeval(0x00601158 + N2_DMU_PEU_BASE_ADDR) | |
| 365 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_WRITE_MASK 0x80000000fe0003c0 | |
| 366 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_POR_VALUE 0x0000000000000000 | |
| 367 | ||
| 368 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_ADDR mpeval(0x00601160 + N2_DMU_PEU_BASE_ADDR) | |
| 369 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_WRITE_MASK 0x80000000fe0003c0 | |
| 370 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_POR_VALUE 0x0000000000000000 | |
| 371 | ||
| 372 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_ADDR mpeval(0x00601168 + N2_DMU_PEU_BASE_ADDR) | |
| 373 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_WRITE_MASK 0x80000000fe0003c0 | |
| 374 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_POR_VALUE 0x0000000000000000 | |
| 375 | ||
| 376 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_ADDR mpeval(0x00601170 + N2_DMU_PEU_BASE_ADDR) | |
| 377 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_WRITE_MASK 0x80000000fe0003c0 | |
| 378 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_POR_VALUE 0x0000000000000000 | |
| 379 | ||
| 380 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_ADDR mpeval(0x00601178 + N2_DMU_PEU_BASE_ADDR) | |
| 381 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_WRITE_MASK 0x80000000fe0003c0 | |
| 382 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_POR_VALUE 0x0000000000000000 | |
| 383 | ||
| 384 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_ADDR mpeval(0x00601180 + N2_DMU_PEU_BASE_ADDR) | |
| 385 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_WRITE_MASK 0x80000000fe0003c0 | |
| 386 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_POR_VALUE 0x0000000000000000 | |
| 387 | ||
| 388 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_ADDR mpeval(0x00601188 + N2_DMU_PEU_BASE_ADDR) | |
| 389 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_WRITE_MASK 0x80000000fe0003c0 | |
| 390 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_POR_VALUE 0x0000000000000000 | |
| 391 | ||
| 392 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_ADDR mpeval(0x00601190 + N2_DMU_PEU_BASE_ADDR) | |
| 393 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_WRITE_MASK 0x80000000fe0003c0 | |
| 394 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_POR_VALUE 0x0000000000000000 | |
| 395 | ||
| 396 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_ADDR mpeval(0x00601198 + N2_DMU_PEU_BASE_ADDR) | |
| 397 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_WRITE_MASK 0x80000000fe0003c0 | |
| 398 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_POR_VALUE 0x0000000000000000 | |
| 399 | ||
| 400 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_ADDR mpeval(0x006011a0 + N2_DMU_PEU_BASE_ADDR) | |
| 401 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_WRITE_MASK 0x80000000fe0003c0 | |
| 402 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_POR_VALUE 0x0000000000000000 | |
| 403 | ||
| 404 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_ADDR mpeval(0x006011a8 + N2_DMU_PEU_BASE_ADDR) | |
| 405 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_WRITE_MASK 0x80000000fe0003c0 | |
| 406 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_POR_VALUE 0x0000000000000000 | |
| 407 | ||
| 408 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_ADDR mpeval(0x006011b0 + N2_DMU_PEU_BASE_ADDR) | |
| 409 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_WRITE_MASK 0x80000000fe0003c0 | |
| 410 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_POR_VALUE 0x0000000000000000 | |
| 411 | ||
| 412 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_ADDR mpeval(0x006011b8 + N2_DMU_PEU_BASE_ADDR) | |
| 413 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_WRITE_MASK 0x80000000fe0003c0 | |
| 414 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_POR_VALUE 0x0000000000000000 | |
| 415 | ||
| 416 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_ADDR mpeval(0x006011c0 + N2_DMU_PEU_BASE_ADDR) | |
| 417 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_WRITE_MASK 0x80000000fe0003c0 | |
| 418 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_POR_VALUE 0x0000000000000000 | |
| 419 | ||
| 420 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_ADDR mpeval(0x006011c8 + N2_DMU_PEU_BASE_ADDR) | |
| 421 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_WRITE_MASK 0x80000000fe0003c0 | |
| 422 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_POR_VALUE 0x0000000000000000 | |
| 423 | ||
| 424 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_ADDR mpeval(0x006011d0 + N2_DMU_PEU_BASE_ADDR) | |
| 425 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_WRITE_MASK 0x80000000fe0003c0 | |
| 426 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_POR_VALUE 0x0000000000000000 | |
| 427 | ||
| 428 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_ADDR mpeval(0x006011d8 + N2_DMU_PEU_BASE_ADDR) | |
| 429 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_WRITE_MASK 0x80000000fe0003c0 | |
| 430 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_POR_VALUE 0x0000000000000000 | |
| 431 | ||
| 432 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_ADDR mpeval(0x006011f0 + N2_DMU_PEU_BASE_ADDR) | |
| 433 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_WRITE_MASK 0x80000000fe0003c0 | |
| 434 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_POR_VALUE 0x0000000000000000 | |
| 435 | ||
| 436 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_ADDR mpeval(0x006011f8 + N2_DMU_PEU_BASE_ADDR) | |
| 437 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_WRITE_MASK 0x80000000fe0003c0 | |
| 438 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_POR_VALUE 0x0000000000000000 | |
| 439 | ||
| 440 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_ADDR mpeval(0x006014a0 + N2_DMU_PEU_BASE_ADDR) | |
| 441 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_WRITE_MASK 0x0000000000000003 | |
| 442 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_POR_VALUE 0x0000000000000000 | |
| 443 | ||
| 444 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_ADDR mpeval(0x006014a8 + N2_DMU_PEU_BASE_ADDR) | |
| 445 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_WRITE_MASK 0x0000000000000003 | |
| 446 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_POR_VALUE 0x0000000000000000 | |
| 447 | ||
| 448 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_ADDR mpeval(0x006014b0 + N2_DMU_PEU_BASE_ADDR) | |
| 449 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_WRITE_MASK 0x0000000000000003 | |
| 450 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_POR_VALUE 0x0000000000000000 | |
| 451 | ||
| 452 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_ADDR mpeval(0x006014b8 + N2_DMU_PEU_BASE_ADDR) | |
| 453 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_WRITE_MASK 0x0000000000000003 | |
| 454 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_POR_VALUE 0x0000000000000000 | |
| 455 | ||
| 456 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_ADDR mpeval(0x006014c0 + N2_DMU_PEU_BASE_ADDR) | |
| 457 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_WRITE_MASK 0x0000000000000003 | |
| 458 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_POR_VALUE 0x0000000000000000 | |
| 459 | ||
| 460 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_ADDR mpeval(0x006014c8 + N2_DMU_PEU_BASE_ADDR) | |
| 461 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_WRITE_MASK 0x0000000000000003 | |
| 462 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_POR_VALUE 0x0000000000000000 | |
| 463 | ||
| 464 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_ADDR mpeval(0x006014d0 + N2_DMU_PEU_BASE_ADDR) | |
| 465 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_WRITE_MASK 0x0000000000000003 | |
| 466 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_POR_VALUE 0x0000000000000000 | |
| 467 | ||
| 468 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_ADDR mpeval(0x006014d8 + N2_DMU_PEU_BASE_ADDR) | |
| 469 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_WRITE_MASK 0x0000000000000003 | |
| 470 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_POR_VALUE 0x0000000000000000 | |
| 471 | ||
| 472 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_ADDR mpeval(0x006014e0 + N2_DMU_PEU_BASE_ADDR) | |
| 473 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_WRITE_MASK 0x0000000000000003 | |
| 474 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_POR_VALUE 0x0000000000000000 | |
| 475 | ||
| 476 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_ADDR mpeval(0x006014e8 + N2_DMU_PEU_BASE_ADDR) | |
| 477 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_WRITE_MASK 0x0000000000000003 | |
| 478 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_POR_VALUE 0x0000000000000000 | |
| 479 | ||
| 480 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_ADDR mpeval(0x006014f0 + N2_DMU_PEU_BASE_ADDR) | |
| 481 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_WRITE_MASK 0x0000000000000003 | |
| 482 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_POR_VALUE 0x0000000000000000 | |
| 483 | ||
| 484 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_ADDR mpeval(0x006014f8 + N2_DMU_PEU_BASE_ADDR) | |
| 485 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_WRITE_MASK 0x0000000000000003 | |
| 486 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_POR_VALUE 0x0000000000000000 | |
| 487 | ||
| 488 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_ADDR mpeval(0x00601500 + N2_DMU_PEU_BASE_ADDR) | |
| 489 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_WRITE_MASK 0x0000000000000003 | |
| 490 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_POR_VALUE 0x0000000000000000 | |
| 491 | ||
| 492 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_ADDR mpeval(0x00601508 + N2_DMU_PEU_BASE_ADDR) | |
| 493 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_WRITE_MASK 0x0000000000000003 | |
| 494 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_POR_VALUE 0x0000000000000000 | |
| 495 | ||
| 496 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_ADDR mpeval(0x00601510 + N2_DMU_PEU_BASE_ADDR) | |
| 497 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_WRITE_MASK 0x0000000000000003 | |
| 498 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_POR_VALUE 0x0000000000000000 | |
| 499 | ||
| 500 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_ADDR mpeval(0x00601518 + N2_DMU_PEU_BASE_ADDR) | |
| 501 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_WRITE_MASK 0x0000000000000003 | |
| 502 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_POR_VALUE 0x0000000000000000 | |
| 503 | ||
| 504 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_ADDR mpeval(0x00601520 + N2_DMU_PEU_BASE_ADDR) | |
| 505 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_WRITE_MASK 0x0000000000000003 | |
| 506 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_POR_VALUE 0x0000000000000000 | |
| 507 | ||
| 508 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_ADDR mpeval(0x00601528 + N2_DMU_PEU_BASE_ADDR) | |
| 509 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_WRITE_MASK 0x0000000000000003 | |
| 510 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_POR_VALUE 0x0000000000000000 | |
| 511 | ||
| 512 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_ADDR mpeval(0x00601530 + N2_DMU_PEU_BASE_ADDR) | |
| 513 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_WRITE_MASK 0x0000000000000003 | |
| 514 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_POR_VALUE 0x0000000000000000 | |
| 515 | ||
| 516 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_ADDR mpeval(0x00601538 + N2_DMU_PEU_BASE_ADDR) | |
| 517 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_WRITE_MASK 0x0000000000000003 | |
| 518 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_POR_VALUE 0x0000000000000000 | |
| 519 | ||
| 520 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_ADDR mpeval(0x00601540 + N2_DMU_PEU_BASE_ADDR) | |
| 521 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_WRITE_MASK 0x0000000000000003 | |
| 522 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_POR_VALUE 0x0000000000000000 | |
| 523 | ||
| 524 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_ADDR mpeval(0x00601548 + N2_DMU_PEU_BASE_ADDR) | |
| 525 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_WRITE_MASK 0x0000000000000003 | |
| 526 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_POR_VALUE 0x0000000000000000 | |
| 527 | ||
| 528 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_ADDR mpeval(0x00601550 + N2_DMU_PEU_BASE_ADDR) | |
| 529 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_WRITE_MASK 0x0000000000000003 | |
| 530 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_POR_VALUE 0x0000000000000000 | |
| 531 | ||
| 532 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_ADDR mpeval(0x00601558 + N2_DMU_PEU_BASE_ADDR) | |
| 533 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_WRITE_MASK 0x0000000000000003 | |
| 534 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_POR_VALUE 0x0000000000000000 | |
| 535 | ||
| 536 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_ADDR mpeval(0x00601560 + N2_DMU_PEU_BASE_ADDR) | |
| 537 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_WRITE_MASK 0x0000000000000003 | |
| 538 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_POR_VALUE 0x0000000000000000 | |
| 539 | ||
| 540 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_ADDR mpeval(0x00601568 + N2_DMU_PEU_BASE_ADDR) | |
| 541 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_WRITE_MASK 0x0000000000000003 | |
| 542 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_POR_VALUE 0x0000000000000000 | |
| 543 | ||
| 544 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_ADDR mpeval(0x00601570 + N2_DMU_PEU_BASE_ADDR) | |
| 545 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_WRITE_MASK 0x0000000000000003 | |
| 546 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_POR_VALUE 0x0000000000000000 | |
| 547 | ||
| 548 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_ADDR mpeval(0x00601578 + N2_DMU_PEU_BASE_ADDR) | |
| 549 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_WRITE_MASK 0x0000000000000003 | |
| 550 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_POR_VALUE 0x0000000000000000 | |
| 551 | ||
| 552 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_ADDR mpeval(0x00601580 + N2_DMU_PEU_BASE_ADDR) | |
| 553 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_WRITE_MASK 0x0000000000000003 | |
| 554 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_POR_VALUE 0x0000000000000000 | |
| 555 | ||
| 556 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_ADDR mpeval(0x00601588 + N2_DMU_PEU_BASE_ADDR) | |
| 557 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_WRITE_MASK 0x0000000000000003 | |
| 558 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_POR_VALUE 0x0000000000000000 | |
| 559 | ||
| 560 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_ADDR mpeval(0x00601590 + N2_DMU_PEU_BASE_ADDR) | |
| 561 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_WRITE_MASK 0x0000000000000003 | |
| 562 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_POR_VALUE 0x0000000000000000 | |
| 563 | ||
| 564 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_ADDR mpeval(0x00601598 + N2_DMU_PEU_BASE_ADDR) | |
| 565 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_WRITE_MASK 0x0000000000000003 | |
| 566 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_POR_VALUE 0x0000000000000000 | |
| 567 | ||
| 568 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_ADDR mpeval(0x006015a0 + N2_DMU_PEU_BASE_ADDR) | |
| 569 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_WRITE_MASK 0x0000000000000003 | |
| 570 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_POR_VALUE 0x0000000000000000 | |
| 571 | ||
| 572 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_ADDR mpeval(0x006015a8 + N2_DMU_PEU_BASE_ADDR) | |
| 573 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_WRITE_MASK 0x0000000000000003 | |
| 574 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_POR_VALUE 0x0000000000000000 | |
| 575 | ||
| 576 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_ADDR mpeval(0x006015b0 + N2_DMU_PEU_BASE_ADDR) | |
| 577 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_WRITE_MASK 0x0000000000000003 | |
| 578 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_POR_VALUE 0x0000000000000000 | |
| 579 | ||
| 580 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_ADDR mpeval(0x006015b8 + N2_DMU_PEU_BASE_ADDR) | |
| 581 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_WRITE_MASK 0x0000000000000003 | |
| 582 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_POR_VALUE 0x0000000000000000 | |
| 583 | ||
| 584 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_ADDR mpeval(0x006015c0 + N2_DMU_PEU_BASE_ADDR) | |
| 585 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_WRITE_MASK 0x0000000000000003 | |
| 586 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_POR_VALUE 0x0000000000000000 | |
| 587 | ||
| 588 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_ADDR mpeval(0x006015c8 + N2_DMU_PEU_BASE_ADDR) | |
| 589 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_WRITE_MASK 0x0000000000000003 | |
| 590 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_POR_VALUE 0x0000000000000000 | |
| 591 | ||
| 592 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_ADDR mpeval(0x006015d0 + N2_DMU_PEU_BASE_ADDR) | |
| 593 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_WRITE_MASK 0x0000000000000003 | |
| 594 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_POR_VALUE 0x0000000000000000 | |
| 595 | ||
| 596 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_ADDR mpeval(0x006015d8 + N2_DMU_PEU_BASE_ADDR) | |
| 597 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_WRITE_MASK 0x0000000000000003 | |
| 598 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_POR_VALUE 0x0000000000000000 | |
| 599 | ||
| 600 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_ADDR mpeval(0x006015f0 + N2_DMU_PEU_BASE_ADDR) | |
| 601 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_WRITE_MASK 0x0000000000000003 | |
| 602 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_POR_VALUE 0x0000000000000000 | |
| 603 | ||
| 604 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_ADDR mpeval(0x006015f8 + N2_DMU_PEU_BASE_ADDR) | |
| 605 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_WRITE_MASK 0x0000000000000003 | |
| 606 | #define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_POR_VALUE 0x0000000000000000 | |
| 607 | ||
| 608 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_ADDR mpeval(0x00601a00 + N2_DMU_PEU_BASE_ADDR) | |
| 609 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_WRITE_MASK 0x0000000001ffffff | |
| 610 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_POR_VALUE 0x0000000000000000 | |
| 611 | ||
| 612 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_ADDR mpeval(0x00601a10 + N2_DMU_PEU_BASE_ADDR) | |
| 613 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_WRITE_MASK 0x0000000000000000 | |
| 614 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_POR_VALUE 0x0000000000000000 | |
| 615 | ||
| 616 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_ADDR mpeval(0x00601a18 + N2_DMU_PEU_BASE_ADDR) | |
| 617 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_WRITE_MASK 0x0000000000000000 | |
| 618 | #define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_POR_VALUE 0x0000000000000000 | |
| 619 | ||
| 620 | ||
| 621 | !! Register definitions from :/verif/env/dmu/vera/csrtool/mess_a.csr_define.vri 1.1 | |
| 622 | ||
| 623 | ||
| 624 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_ADDR mpeval(0x00630000 + N2_DMU_PEU_BASE_ADDR) | |
| 625 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_WRITE_MASK 0x800000000000003f | |
| 626 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_POR_VALUE 0x0000000000000000 | |
| 627 | ||
| 628 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_ADDR mpeval(0x00630008 + N2_DMU_PEU_BASE_ADDR) | |
| 629 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_WRITE_MASK 0x800000000000003f | |
| 630 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_POR_VALUE 0x0000000000000000 | |
| 631 | ||
| 632 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_ADDR mpeval(0x00630010 + N2_DMU_PEU_BASE_ADDR) | |
| 633 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_WRITE_MASK 0x800000000000003f | |
| 634 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_POR_VALUE 0x0000000000000000 | |
| 635 | ||
| 636 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_ADDR mpeval(0x00630018 + N2_DMU_PEU_BASE_ADDR) | |
| 637 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_WRITE_MASK 0x800000000000003f | |
| 638 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_POR_VALUE 0x0000000000000000 | |
| 639 | ||
| 640 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_ADDR mpeval(0x00630020 + N2_DMU_PEU_BASE_ADDR) | |
| 641 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_WRITE_MASK 0x800000000000003f | |
| 642 | #define FIRE_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_POR_VALUE 0x0000000000000000 | |
| 643 | ||
| 644 | ||
| 645 | !! Register definitions from :/verif/env/dmu/vera/csrtool/msi_a.csr_define.vri 1.1 | |
| 646 | ||
| 647 | ||
| 648 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_ADDR mpeval(0x00620000 + N2_DMU_PEU_BASE_ADDR) | |
| 649 | !! This register maps to a ram with a depth of: 256 | |
| 650 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_WRITE_MASK 0x800000000000003f | |
| 651 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_POR_VALUE 0x0000000000000000 | |
| 652 | ||
| 653 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_ADDR mpeval(0x00628000 + N2_DMU_PEU_BASE_ADDR) | |
| 654 | !! This register maps to a ram with a depth of: 256 | |
| 655 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_WRITE_MASK 0x0000000000000000 | |
| 656 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_POR_VALUE 0x0000000000000000 | |
| 657 | ||
| 658 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_ADDR mpeval(0x00628800 + N2_DMU_PEU_BASE_ADDR) | |
| 659 | !! This register maps to a ram with a depth of: 256 | |
| 660 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_WRITE_MASK 0x4000000000000000 | |
| 661 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_POR_VALUE 0x0000000000000000 | |
| 662 | ||
| 663 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_ADDR mpeval(0x0062c000 + N2_DMU_PEU_BASE_ADDR) | |
| 664 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_WRITE_MASK 0xffffffffffffffc0 | |
| 665 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_POR_VALUE 0x0000000000000000 | |
| 666 | ||
| 667 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_ADDR mpeval(0x0062c008 + N2_DMU_PEU_BASE_ADDR) | |
| 668 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_WRITE_MASK 0xffffffffffffffff | |
| 669 | #define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_POR_VALUE 0x0000000000000000 | |
| 670 | ||
| 671 | ||
| 672 | !! Register definitions from :/verif/env/dmu/vera/csrtool/psb_a.csr_define.vri 1.2 | |
| 673 | ||
| 674 | ||
| 675 | #define FIRE_DLC_PSB_CSR_A_PSB_DMA_ADDR mpeval(0x00660000 + N2_DMU_PEU_BASE_ADDR) | |
| 676 | !! This register maps to a ram with a depth of: 32 | |
| 677 | #define FIRE_DLC_PSB_CSR_A_PSB_DMA_WRITE_MASK 0x0000000000000000 | |
| 678 | #define FIRE_DLC_PSB_CSR_A_PSB_DMA_POR_VALUE 0x0000000000000000 | |
| 679 | ||
| 680 | #define FIRE_DLC_PSB_CSR_A_PSB_PIO_ADDR mpeval(0x00664000 + N2_DMU_PEU_BASE_ADDR) | |
| 681 | !! This register maps to a ram with a depth of: 16 | |
| 682 | #define FIRE_DLC_PSB_CSR_A_PSB_PIO_WRITE_MASK 0x0000000000000000 | |
| 683 | #define FIRE_DLC_PSB_CSR_A_PSB_PIO_POR_VALUE 0x0000000000000000 | |
| 684 | ||
| 685 | ||
| 686 | !! Register definitions from :/verif/env/dmu/vera/csrtool/tsb_a.csr_define.vri 1.2 | |
| 687 | ||
| 688 | ||
| 689 | #define FIRE_DLC_TSB_CSR_A_TSB_DMA_ADDR mpeval(0x00670000 + N2_DMU_PEU_BASE_ADDR) | |
| 690 | !! This register maps to a ram with a depth of: 32 | |
| 691 | #define FIRE_DLC_TSB_CSR_A_TSB_DMA_WRITE_MASK 0x0000000000000000 | |
| 692 | #define FIRE_DLC_TSB_CSR_A_TSB_DMA_POR_VALUE 0x0000000000000000 | |
| 693 | ||
| 694 | #define FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR mpeval(0x00670100 + N2_DMU_PEU_BASE_ADDR) | |
| 695 | #define FIRE_DLC_TSB_CSR_A_TSB_STS_WRITE_MASK 0x0000000000000000 | |
| 696 | #define FIRE_DLC_TSB_CSR_A_TSB_STS_POR_VALUE 0x0000000000000001 | |
| 697 | ||
| 698 | ||
| 699 | !! Register definitions from :/verif/env/ilu_peu/vera/csrtool/cib_a.csr_define.vri 1.8 | |
| 700 | ||
| 701 | ||
| 702 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR mpeval(0x00651000 + N2_DMU_PEU_BASE_ADDR) | |
| 703 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_WRITE_MASK 0x00000000000000f0 | |
| 704 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_POR_VALUE 0x00000000000000f0 | |
| 705 | ||
| 706 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR mpeval(0x00651008 + N2_DMU_PEU_BASE_ADDR) | |
| 707 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_WRITE_MASK 0x000000f0000000f0 | |
| 708 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_POR_VALUE 0x0000000000000000 | |
| 709 | ||
| 710 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ADDR mpeval(0x00651010 + N2_DMU_PEU_BASE_ADDR) | |
| 711 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_WRITE_MASK 0x0000000000000000 | |
| 712 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_POR_VALUE 0x0000000000000000 | |
| 713 | ||
| 714 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR mpeval(0x00651018 + N2_DMU_PEU_BASE_ADDR) | |
| 715 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_WRITE_MASK 0x0000000000000000 | |
| 716 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000 | |
| 717 | ||
| 718 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR mpeval(0x00651020 + N2_DMU_PEU_BASE_ADDR) | |
| 719 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_WRITE_MASK 0x000000f0000000f0 | |
| 720 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000 | |
| 721 | ||
| 722 | #define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR mpeval(0x00651800 + N2_DMU_PEU_BASE_ADDR) | |
| 723 | #define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_WRITE_MASK 0x800000000000000f | |
| 724 | #define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_POR_VALUE 0x0000000000000000 | |
| 725 | ||
| 726 | #define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR mpeval(0x00651808 + N2_DMU_PEU_BASE_ADDR) | |
| 727 | #define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_WRITE_MASK 0x0000000000000000 | |
| 728 | #define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_POR_VALUE 0x0000000000000000 | |
| 729 | ||
| 730 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR mpeval(0x00652000 + N2_DMU_PEU_BASE_ADDR) | |
| 731 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_WRITE_MASK 0x00000003ffffff3c | |
| 732 | #define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_POR_VALUE 0x00000003ffff0000 | |
| 733 | ||
| 734 | ||
| 735 | !! Register definitions from :/verif/env/ilu_peu/vera/csrtool/tlr_a.csr_define.vri 1.16 | |
| 736 | ||
| 737 | ||
| 738 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR mpeval(0x00680000 + N2_DMU_PEU_BASE_ADDR) | |
| 739 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_WRITE_MASK 0x00000000ff17ffff | |
| 740 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_POR_VALUE 0x0000000000000101 | |
| 741 | ||
| 742 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR mpeval(0x00680008 + N2_DMU_PEU_BASE_ADDR) | |
| 743 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_WRITE_MASK 0x0000000000000100 | |
| 744 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_POR_VALUE 0x0000000000000001 | |
| 745 | ||
| 746 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_ADDR mpeval(0x00680010 + N2_DMU_PEU_BASE_ADDR) | |
| 747 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_WRITE_MASK 0x0000000000000001 | |
| 748 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_POR_VALUE 0x0000000000000000 | |
| 749 | ||
| 750 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_ADDR mpeval(0x00680018 + N2_DMU_PEU_BASE_ADDR) | |
| 751 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_WRITE_MASK 0x000000ff000fffff | |
| 752 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_POR_VALUE 0x00000010000200c0 | |
| 753 | ||
| 754 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_ADDR mpeval(0x00680100 + N2_DMU_PEU_BASE_ADDR) | |
| 755 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_WRITE_MASK 0x0f00ffffffffff03 | |
| 756 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_POR_VALUE 0x0000000000000000 | |
| 757 | ||
| 758 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_ADDR mpeval(0x00680200 + N2_DMU_PEU_BASE_ADDR) | |
| 759 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_WRITE_MASK 0x0000000000000000 | |
| 760 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_POR_VALUE 0x0000000000000000 | |
| 761 | ||
| 762 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_ADDR mpeval(0x00680208 + N2_DMU_PEU_BASE_ADDR) | |
| 763 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_WRITE_MASK 0x0000000000000000 | |
| 764 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_POR_VALUE 0x0000000000000000 | |
| 765 | ||
| 766 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_ADDR mpeval(0x00680210 + N2_DMU_PEU_BASE_ADDR) | |
| 767 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_WRITE_MASK 0x0000000000000000 | |
| 768 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_POR_VALUE 0x0000000000001000 | |
| 769 | ||
| 770 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_ADDR mpeval(0x00680218 + N2_DMU_PEU_BASE_ADDR) | |
| 771 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_WRITE_MASK 0x0000000000000000 | |
| 772 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_POR_VALUE 0x00000010000200c0 | |
| 773 | ||
| 774 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_ADDR mpeval(0x00680220 + N2_DMU_PEU_BASE_ADDR) | |
| 775 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_WRITE_MASK 0x0000000000000000 | |
| 776 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_POR_VALUE 0x0000000000000000 | |
| 777 | ||
| 778 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR mpeval(0x00681000 + N2_DMU_PEU_BASE_ADDR) | |
| 779 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_WRITE_MASK 0x0000000000ffffff | |
| 780 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_POR_VALUE 0x0000000000ffffff | |
| 781 | ||
| 782 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_ADDR mpeval(0x00681008 + N2_DMU_PEU_BASE_ADDR) | |
| 783 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_WRITE_MASK 0x00ffffff00ffffff | |
| 784 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_POR_VALUE 0x0000000000000000 | |
| 785 | ||
| 786 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_ADDR mpeval(0x00681010 + N2_DMU_PEU_BASE_ADDR) | |
| 787 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_WRITE_MASK 0x0000000000000000 | |
| 788 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_POR_VALUE 0x0000000000000000 | |
| 789 | ||
| 790 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR mpeval(0x00681018 + N2_DMU_PEU_BASE_ADDR) | |
| 791 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_WRITE_MASK 0x0000000000000000 | |
| 792 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000 | |
| 793 | ||
| 794 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_ADDR mpeval(0x00681020 + N2_DMU_PEU_BASE_ADDR) | |
| 795 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_WRITE_MASK 0x00ffffff00ffffff | |
| 796 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000 | |
| 797 | ||
| 798 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_ADDR mpeval(0x00681028 + N2_DMU_PEU_BASE_ADDR) | |
| 799 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_WRITE_MASK 0xffffffffffffffff | |
| 800 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_POR_VALUE 0x0000000000000000 | |
| 801 | ||
| 802 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_ADDR mpeval(0x00681030 + N2_DMU_PEU_BASE_ADDR) | |
| 803 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_WRITE_MASK 0xffffffffffffffff | |
| 804 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_POR_VALUE 0x0000000000000000 | |
| 805 | ||
| 806 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_ADDR mpeval(0x00681038 + N2_DMU_PEU_BASE_ADDR) | |
| 807 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_WRITE_MASK 0xffffffffffffffff | |
| 808 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_POR_VALUE 0x0000000000000000 | |
| 809 | ||
| 810 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_ADDR mpeval(0x00681040 + N2_DMU_PEU_BASE_ADDR) | |
| 811 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_WRITE_MASK 0xffffffffffffffff | |
| 812 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_POR_VALUE 0x0000000000000000 | |
| 813 | ||
| 814 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_ADDR mpeval(0x00682000 + N2_DMU_PEU_BASE_ADDR) | |
| 815 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_WRITE_MASK 0x000000000003ffff | |
| 816 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_POR_VALUE 0x0000000000000000 | |
| 817 | ||
| 818 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_ADDR mpeval(0x00682008 + N2_DMU_PEU_BASE_ADDR) | |
| 819 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_WRITE_MASK 0xffffffffffffffff | |
| 820 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_POR_VALUE 0x0000000000000000 | |
| 821 | ||
| 822 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_ADDR mpeval(0x00682010 + N2_DMU_PEU_BASE_ADDR) | |
| 823 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_WRITE_MASK 0xffffffffffffffff | |
| 824 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_POR_VALUE 0x0000000000000000 | |
| 825 | ||
| 826 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_ADDR mpeval(0x00682018 + N2_DMU_PEU_BASE_ADDR) | |
| 827 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_WRITE_MASK 0x00000000ffffffff | |
| 828 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_POR_VALUE 0x0000000000000000 | |
| 829 | ||
| 830 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_ADDR mpeval(0x00683000 + N2_DMU_PEU_BASE_ADDR) | |
| 831 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_WRITE_MASK 0x00000000000001ff | |
| 832 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_POR_VALUE 0x0000000000000000 | |
| 833 | ||
| 834 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_ADDR mpeval(0x00683008 + N2_DMU_PEU_BASE_ADDR) | |
| 835 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_WRITE_MASK 0x00000000000001ff | |
| 836 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_POR_VALUE 0x0000000000000000 | |
| 837 | ||
| 838 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_ADDR mpeval(0x00690000 + N2_DMU_PEU_BASE_ADDR) | |
| 839 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_WRITE_MASK 0x0000000000000000 | |
| 840 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_POR_VALUE 0x0000000000000002 | |
| 841 | ||
| 842 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR mpeval(0x00690008 + N2_DMU_PEU_BASE_ADDR) | |
| 843 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_WRITE_MASK 0x00000000000000e0 | |
| 844 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_POR_VALUE 0x0000000000000000 | |
| 845 | ||
| 846 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_ADDR mpeval(0x00690010 + N2_DMU_PEU_BASE_ADDR) | |
| 847 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_WRITE_MASK 0x0000000000000000 | |
| 848 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_POR_VALUE 0x0000000000000000 | |
| 849 | ||
| 850 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_ADDR mpeval(0x00690018 + N2_DMU_PEU_BASE_ADDR) | |
| 851 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_WRITE_MASK 0x0000000000000000 | |
| 852 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_POR_VALUE 0x0000000000014c81 | |
| 853 | ||
| 854 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_ADDR mpeval(0x00690020 + N2_DMU_PEU_BASE_ADDR) | |
| 855 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_WRITE_MASK 0x00000000000000f3 | |
| 856 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_POR_VALUE 0x0000000000000000 | |
| 857 | ||
| 858 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_ADDR mpeval(0x00690028 + N2_DMU_PEU_BASE_ADDR) | |
| 859 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_WRITE_MASK 0x0000000000000000 | |
| 860 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_POR_VALUE 0x0000000000000000 | |
| 861 | ||
| 862 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_ADDR mpeval(0x00690030 + N2_DMU_PEU_BASE_ADDR) | |
| 863 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_WRITE_MASK 0x000000000001ff80 | |
| 864 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_POR_VALUE 0x0000000000000000 | |
| 865 | ||
| 866 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_ADDR mpeval(0x00691000 + N2_DMU_PEU_BASE_ADDR) | |
| 867 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_WRITE_MASK 0x00000000001fffff | |
| 868 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_POR_VALUE 0x000000000017f011 | |
| 869 | ||
| 870 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_ADDR mpeval(0x00691008 + N2_DMU_PEU_BASE_ADDR) | |
| 871 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_WRITE_MASK 0x001fffff001fffff | |
| 872 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_POR_VALUE 0x0000000000000000 | |
| 873 | ||
| 874 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_ADDR mpeval(0x00691010 + N2_DMU_PEU_BASE_ADDR) | |
| 875 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_WRITE_MASK 0x0000000000000000 | |
| 876 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_POR_VALUE 0x0000000000000000 | |
| 877 | ||
| 878 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_ADDR mpeval(0x00691018 + N2_DMU_PEU_BASE_ADDR) | |
| 879 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_WRITE_MASK 0x0000000000000000 | |
| 880 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000 | |
| 881 | ||
| 882 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_ADDR mpeval(0x00691020 + N2_DMU_PEU_BASE_ADDR) | |
| 883 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_WRITE_MASK 0x0017f0110017f011 | |
| 884 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000 | |
| 885 | ||
| 886 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_ADDR mpeval(0x00691028 + N2_DMU_PEU_BASE_ADDR) | |
| 887 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_WRITE_MASK 0xffffffffffffffff | |
| 888 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_POR_VALUE 0x0000000000000000 | |
| 889 | ||
| 890 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_ADDR mpeval(0x00691030 + N2_DMU_PEU_BASE_ADDR) | |
| 891 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_WRITE_MASK 0xffffffffffffffff | |
| 892 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_POR_VALUE 0x0000000000000000 | |
| 893 | ||
| 894 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_ADDR mpeval(0x00691038 + N2_DMU_PEU_BASE_ADDR) | |
| 895 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_WRITE_MASK 0xffffffffffffffff | |
| 896 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_POR_VALUE 0x0000000000000000 | |
| 897 | ||
| 898 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_ADDR mpeval(0x00691040 + N2_DMU_PEU_BASE_ADDR) | |
| 899 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_WRITE_MASK 0xffffffffffffffff | |
| 900 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_POR_VALUE 0x0000000000000000 | |
| 901 | ||
| 902 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_ADDR mpeval(0x006a1000 + N2_DMU_PEU_BASE_ADDR) | |
| 903 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_WRITE_MASK 0x0000000000001fff | |
| 904 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_POR_VALUE 0x00000000000011c1 | |
| 905 | ||
| 906 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_ADDR mpeval(0x006a1008 + N2_DMU_PEU_BASE_ADDR) | |
| 907 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_WRITE_MASK 0x00001fff00001fff | |
| 908 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_POR_VALUE 0x0000000000000000 | |
| 909 | ||
| 910 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_ADDR mpeval(0x006a1010 + N2_DMU_PEU_BASE_ADDR) | |
| 911 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_WRITE_MASK 0x0000000000000000 | |
| 912 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_POR_VALUE 0x0000000000000000 | |
| 913 | ||
| 914 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_ADDR mpeval(0x006a1018 + N2_DMU_PEU_BASE_ADDR) | |
| 915 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_WRITE_MASK 0x0000000000000000 | |
| 916 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000 | |
| 917 | ||
| 918 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_ADDR mpeval(0x006a1020 + N2_DMU_PEU_BASE_ADDR) | |
| 919 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_WRITE_MASK 0x000011c1000011c1 | |
| 920 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000 | |
| 921 | ||
| 922 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_PEU_DLPL_SERDES_REV_ADDR mpeval(0x006e2000 + N2_DMU_PEU_BASE_ADDR) | |
| 923 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_PEU_DLPL_SERDES_REV_WRITE_MASK 0x0000000000000000 | |
| 924 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_PEU_DLPL_SERDES_REV_POR_VALUE 0x0000000000000000 | |
| 925 | ||
| 926 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_ADDR mpeval(0x006e2008 + N2_DMU_PEU_BASE_ADDR) | |
| 927 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_WRITE_MASK 0x000000000000ffff | |
| 928 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_POR_VALUE 0x0000000000000043 | |
| 929 | ||
| 930 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_ADDR mpeval(0x006e2010 + N2_DMU_PEU_BASE_ADDR) | |
| 931 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_WRITE_MASK 0x0000000000000000 | |
| 932 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_POR_VALUE 0x0000000000000000 | |
| 933 | ||
| 934 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_ADDR mpeval(0x006e2018 + N2_DMU_PEU_BASE_ADDR) | |
| 935 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_WRITE_MASK 0x000000000000ffff | |
| 936 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_POR_VALUE 0x00000000000000fc | |
| 937 | ||
| 938 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_ADDR mpeval(0x006e2020 + N2_DMU_PEU_BASE_ADDR) | |
| 939 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_WRITE_MASK 0x0000000000000000 | |
| 940 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_POR_VALUE 0x0000000000000000 | |
| 941 | ||
| 942 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_ADDR mpeval(0x006e2040 + N2_DMU_PEU_BASE_ADDR) | |
| 943 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_WRITE_MASK 0x00000000ffffffff | |
| 944 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_POR_VALUE 0x0000000000000000 | |
| 945 | ||
| 946 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_ADDR mpeval(0x006e2050 + N2_DMU_PEU_BASE_ADDR) | |
| 947 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_WRITE_MASK 0x000000000000011f | |
| 948 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_POR_VALUE 0x0000000000000000 | |
| 949 | ||
| 950 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_ADDR mpeval(0x006e2058 + N2_DMU_PEU_BASE_ADDR) | |
| 951 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_WRITE_MASK 0x000000000000ff1f | |
| 952 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_POR_VALUE 0x0000000000000101 | |
| 953 | ||
| 954 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR mpeval(0x006e2060 + N2_DMU_PEU_BASE_ADDR) | |
| 955 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_WRITE_MASK 0x00000000ffff3f1e | |
| 956 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_POR_VALUE 0x00000000001b0800 | |
| 957 | ||
| 958 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_ADDR mpeval(0x006e2068 + N2_DMU_PEU_BASE_ADDR) | |
| 959 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_WRITE_MASK 0x0000000003ffffff | |
| 960 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_POR_VALUE 0x0000000000000000 | |
| 961 | ||
| 962 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_ADDR mpeval(0x006e2070 + N2_DMU_PEU_BASE_ADDR) | |
| 963 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_WRITE_MASK 0x00000000000077ff | |
| 964 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_POR_VALUE 0x00000000000033aa | |
| 965 | ||
| 966 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_ADDR mpeval(0x006e2078 + N2_DMU_PEU_BASE_ADDR) | |
| 967 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_WRITE_MASK 0x00000000000007ff | |
| 968 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_POR_VALUE 0x0000000000000500 | |
| 969 | ||
| 970 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR mpeval(0x006e2100 + N2_DMU_PEU_BASE_ADDR) | |
| 971 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_WRITE_MASK 0x0000000000000000 | |
| 972 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_POR_VALUE 0x0000000000000000 | |
| 973 | ||
| 974 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_ADDR mpeval(0x006e2108 + N2_DMU_PEU_BASE_ADDR) | |
| 975 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_WRITE_MASK 0x00000000ff03ffff | |
| 976 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_POR_VALUE 0x000000000f03ffff | |
| 977 | ||
| 978 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_ADDR mpeval(0x006e2110 + N2_DMU_PEU_BASE_ADDR) | |
| 979 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_WRITE_MASK 0x00000000ff03ffff | |
| 980 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_POR_VALUE 0x0000000000000000 | |
| 981 | ||
| 982 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_ADDR mpeval(0x006e2118 + N2_DMU_PEU_BASE_ADDR) | |
| 983 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_WRITE_MASK 0x0000000000000000 | |
| 984 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_POR_VALUE 0x0000000000000000 | |
| 985 | ||
| 986 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR mpeval(0x006e2120 + N2_DMU_PEU_BASE_ADDR) | |
| 987 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_WRITE_MASK 0x0000000000000000 | |
| 988 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_POR_VALUE 0x0000000000000000 | |
| 989 | ||
| 990 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_ADDR mpeval(0x006e2128 + N2_DMU_PEU_BASE_ADDR) | |
| 991 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_WRITE_MASK 0x00000000ff03ffff | |
| 992 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_POR_VALUE 0x0000000000000000 | |
| 993 | ||
| 994 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_ADDR mpeval(0x006e2130 + N2_DMU_PEU_BASE_ADDR) | |
| 995 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_WRITE_MASK 0x8000000000000000 | |
| 996 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_POR_VALUE 0x0000000000000000 | |
| 997 | ||
| 998 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_ADDR mpeval(0x006e2138 + N2_DMU_PEU_BASE_ADDR) | |
| 999 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_WRITE_MASK 0x0000000000000000 | |
| 1000 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_POR_VALUE 0x0000000000000000 | |
| 1001 | ||
| 1002 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_ADDR mpeval(0x006e2200 + N2_DMU_PEU_BASE_ADDR) | |
| 1003 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_WRITE_MASK 0x00000000000000ff | |
| 1004 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_POR_VALUE 0x0000000000000001 | |
| 1005 | ||
| 1006 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR mpeval(0x006e2300 + N2_DMU_PEU_BASE_ADDR) | |
| 1007 | !! This register maps to a ram with a depth of: 8 | |
| 1008 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_WRITE_MASK 0x000000000000ffff | |
| 1009 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE 0x0000000000000552 | |
| 1010 | ||
| 1011 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_ADDR mpeval(0x006e2380 + N2_DMU_PEU_BASE_ADDR) | |
| 1012 | !! This register maps to a ram with a depth of: 8 | |
| 1013 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_WRITE_MASK 0x0000000000000000 | |
| 1014 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_POR_VALUE 0x0000000000000000 | |
| 1015 | ||
| 1016 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR mpeval(0x006e2400 + N2_DMU_PEU_BASE_ADDR) | |
| 1017 | !! This register maps to a ram with a depth of: 8 | |
| 1018 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_WRITE_MASK 0x00000000000007ff | |
| 1019 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE 0x00000000000001ec | |
| 1020 | ||
| 1021 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_ADDR mpeval(0x006e2480 + N2_DMU_PEU_BASE_ADDR) | |
| 1022 | !! This register maps to a ram with a depth of: 8 | |
| 1023 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_WRITE_MASK 0x0000000000000000 | |
| 1024 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_POR_VALUE 0x0000000000000000 | |
| 1025 | ||
| 1026 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_ADDR mpeval(0x006e2500 + N2_DMU_PEU_BASE_ADDR) | |
| 1027 | !! This register maps to a ram with a depth of: 2 | |
| 1028 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_WRITE_MASK 0x0000000000007fff | |
| 1029 | #define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_POR_VALUE 0x0000000000000003 | |
| 1030 |