projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / hboot_mcuctl_init.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: hboot_mcuctl_init.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38.global mcuctl_init
39mcuctl_init:
40
41#ifdef NEC_AMB
42#ifndef DTM_ENABLED
43#include "mcu_fbdimm_training.s"
44#endif
45#endif
46
47 setx 0x8400000000, %l7, %l6
48 sethi %hi(0x00001000), %g1
49 sethi %hi(0x00002000), %g2
50 sethi %hi(0x00003000), %g3
51!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
52!! For non slam vectors much of this code has been
53!! moved to b4 warm
54!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
55#ifndef DTM_ENABLED
56dimm_init_reg_to_3:
57 add %l6, 0x1a0, %l0 ! DRAM_DIMM_INIT_REG
58 mov 3, %l3 ! Set CKE enable to 1 to assert CKE high to the DIMMs
59 stx %l3, [%l0+%g0] ! (per conversation with Rashid)
60 stx %l3, [%l0+%g1]
61 stx %l3, [%l0+%g2]
62 stx %l3, [%l0+%g3]
63
64! Memory Density Type : 256 Mb, 512 Mb, 1 Gb, 2 Gb
65#if defined(DIMM_SIZE_1G)
66 add %l6, 0x008, %l0 ! DRAM_RAS_ADDR_WIDTH_REG
67 mov 0xe, %l3
68 stx %l3, [%l0+%g0]
69 stx %l3, [%l0+%g1]
70 stx %l3, [%l0+%g2]
71 stx %l3, [%l0+%g3]
72#else
73#if defined(DIMM_SIZE_512)
74 add %l6, 0x008, %l0
75 mov 0xe, %l3
76 stx %l3, [%l0+%g0]
77 stx %l3, [%l0+%g1]
78 stx %l3, [%l0+%g2]
79 stx %l3, [%l0+%g3]
80
81 add %l6, 0x128, %l0 ! 8_BANK_REG
82 mov 0x0, %l3
83 stx %l3, [%l0+%g0]
84 stx %l3, [%l0+%g1]
85 stx %l3, [%l0+%g2]
86 stx %l3, [%l0+%g3]
87#else
88#if defined(DIMM_SIZE_256)
89 add %l6, 0x008, %l0
90 mov 0xd, %l3
91 stx %l3, [%l0+%g0]
92 stx %l3, [%l0+%g1]
93 stx %l3, [%l0+%g2]
94 stx %l3, [%l0+%g3]
95
96 add %l6, 0x128, %l0
97 mov 0x0, %l3
98 stx %l3, [%l0+%g0]
99 stx %l3, [%l0+%g1]
100 stx %l3, [%l0+%g2]
101 stx %l3, [%l0+%g3]
102#else
103!! use default = 2G b
104#endif
105#endif
106#endif
107
108! MEMORY CONFIGURATION SETUP
109
110!! Default !!!
111#define CHNL_TYPE 0
112#define RANK_ADDR 0
113#define RANK 0
114#define NUM_DIMMS 1
115#define AMB_ID 0
116#define CAS_LATENCY 3
117!!
118
119#ifdef SNG_CHANNEL
120#define CHNL_TYPE 1
121#endif
122#ifdef DUAL_CHANNEL
123#define CHNL_TYPE 0
124#endif
125
126#ifdef RANK_LOW
127#define RANK_ADDR 1
128#endif
129
130#ifdef FBDIMMS_1
131#define NUM_DIMMS 1
132#define AMB_ID 0
133#endif
134#ifdef FBDIMMS_2
135#define NUM_DIMMS 2
136#define AMB_ID 8
137#endif
138#ifdef FBDIMMS_4
139#define NUM_DIMMS 4
140#define AMB_ID 24
141#endif
142#ifdef FBDIMMS_6
143#define NUM_DIMMS 6
144#define AMB_ID 40
145#endif
146#ifdef FBDIMMS_8
147#define NUM_DIMMS 0
148#define AMB_ID 56
149#endif
150
151#ifdef STACK_DIMM
152#define RANK 1
153#endif
154
155#ifdef VARY_CAS_LATENCY
156#define CAS_LATENCY VARY_CAS_LATENCY
157#endif
158
159#if defined(SNG_CHANNEL)
160 add %l6, 0x148, %l0 ! SINGLE_CHANNEL_MODE_REG
161 mov CHNL_TYPE, %l3
162 stx %l3, [%l0+%g0]
163 stx %l3, [%l0+%g1]
164 stx %l3, [%l0+%g2]
165 stx %l3, [%l0+%g3]
166#endif
167
168!! HIGH ADDR / SINGLE RANK
169#if !defined(RANK_LOW) && !defined(STACK_DIMM)
170 add %l6, 0x140, %l0 ! DRAM_SEL_LO_ADDR_BITS_REG
171 mov RANK_ADDR, %l3
172 stx %l3, [%l0+%g0]
173 stx %l3, [%l0+%g1]
174 stx %l3, [%l0+%g2]
175 stx %l3, [%l0+%g3]
176
177 add %l6, 0x108, %l0 ! DRAM_DIMM_STACK_REG
178 mov RANK, %l3
179 stx %l3, [%l0+%g0]
180 stx %l3, [%l0+%g1]
181 stx %l3, [%l0+%g2]
182 stx %l3, [%l0+%g3]
183
184#if defined(FBDIMMS_1) || defined(FBDIMMS_2) || defined(FBDIMMS_4) || defined(FBDIMMS_8)
185 add %l6, 0x218, %l0 ! DRAM_DIMM_PRESENT_REG
186 mov NUM_DIMMS, %l3
187 stx %l3, [%l0+%g0]
188 stx %l3, [%l0+%g1]
189 stx %l3, [%l0+%g2]
190 stx %l3, [%l0+%g3]
191
192 add %l6, 0x800, %l0 ! FBD_CHANNEL_STATE_REG
193 mov AMB_ID, %l3
194 stx %l3, [%l0+%g0]
195 stx %l3, [%l0+%g1]
196 stx %l3, [%l0+%g2]
197 stx %l3, [%l0+%g3]
198#endif
199#endif
200
201!! HIGH ADDR / DUAL RANK
202#if !defined(RANK_LOW) && defined(STACK_DIMM)
203 add %l6, 0x140, %l0 ! DRAM_SEL_LO_ADDR_BITS_REG
204 mov RANK_ADDR, %l3
205 stx %l3, [%l0+%g0]
206 stx %l3, [%l0+%g1]
207 stx %l3, [%l0+%g2]
208 stx %l3, [%l0+%g3]
209
210 add %l6, 0x108, %l0 ! DRAM_DIMM_STACK_REG
211 mov RANK, %l3
212 stx %l3, [%l0+%g0]
213 stx %l3, [%l0+%g1]
214 stx %l3, [%l0+%g2]
215 stx %l3, [%l0+%g3]
216
217#if defined(FBDIMMS_1) || defined(FBDIMMS_2) || defined(FBDIMMS_4) || defined(FBDIMMS_8)
218 add %l6, 0x218, %l0 ! DRAM_DIMM_PRESENT_REG
219 mov NUM_DIMMS, %l3
220 stx %l3, [%l0+%g0]
221 stx %l3, [%l0+%g1]
222 stx %l3, [%l0+%g2]
223 stx %l3, [%l0+%g3]
224
225 add %l6, 0x800, %l0 ! FBD_CHANNEL_STATE_REG
226 mov AMB_ID, %l3
227 stx %l3, [%l0+%g0]
228 stx %l3, [%l0+%g1]
229 stx %l3, [%l0+%g2]
230 stx %l3, [%l0+%g3]
231#endif
232#endif
233
234!! LOW ADDR / SINGLE RANK
235#if defined(RANK_LOW) && !defined(STACK_DIMM)
236 add %l6, 0x140, %l0 ! DRAM_SEL_LO_ADDR_BITS_REG
237 mov RANK_ADDR, %l3
238 stx %l3, [%l0+%g0]
239 stx %l3, [%l0+%g1]
240 stx %l3, [%l0+%g2]
241 stx %l3, [%l0+%g3]
242
243 add %l6, 0x108, %l0 ! DRAM_DIMM_STACK_REG
244 mov RANK, %l3
245 stx %l3, [%l0+%g0]
246 stx %l3, [%l0+%g1]
247 stx %l3, [%l0+%g2]
248 stx %l3, [%l0+%g3]
249
250#if defined(FBDIMMS_1) || defined(FBDIMMS_2) || defined(FBDIMMS_4) || defined(FBDIMMS_6) || defined(FBDIMMS_8)
251 add %l6, 0x218, %l0 ! DRAM_DIMM_PRESENT_REG
252 mov NUM_DIMMS, %l3
253 stx %l3, [%l0+%g0]
254 stx %l3, [%l0+%g1]
255 stx %l3, [%l0+%g2]
256 stx %l3, [%l0+%g3]
257
258 add %l6, 0x800, %l0 ! FBD_CHANNEL_STATE_REG
259 mov AMB_ID, %l3
260 stx %l3, [%l0+%g0]
261 stx %l3, [%l0+%g1]
262 stx %l3, [%l0+%g2]
263 stx %l3, [%l0+%g3]
264
265#endif
266#endif
267
268!! LOW ADDR / DUAL RANK
269#if defined(RANK_LOW) && defined(STACK_DIMM)
270 add %l6, 0x140, %l0 ! DRAM_SEL_LO_ADDR_BITS_REG
271 mov RANK_ADDR, %l3
272 stx %l3, [%l0+%g0]
273 stx %l3, [%l0+%g1]
274 stx %l3, [%l0+%g2]
275 stx %l3, [%l0+%g3]
276
277 add %l6, 0x108, %l0 ! DRAM_DIMM_STACK_REG
278 mov RANK, %l3
279 stx %l3, [%l0+%g0]
280 stx %l3, [%l0+%g1]
281 stx %l3, [%l0+%g2]
282 stx %l3, [%l0+%g3]
283
284#if defined(FBDIMMS_1) || defined(FBDIMMS_2) || defined(FBDIMMS_4) || defined(FBDIMMS_6) || defined(FBDIMMS_8)
285 add %l6, 0x218, %l0 ! DRAM_DIMM_PRESENT_REG
286 mov NUM_DIMMS, %l3
287 stx %l3, [%l0+%g0]
288 stx %l3, [%l0+%g1]
289 stx %l3, [%l0+%g2]
290 stx %l3, [%l0+%g3]
291
292 add %l6, 0x800, %l0 ! FBD_CHANNEL_STATE_REG
293 mov AMB_ID, %l3
294 stx %l3, [%l0+%g0]
295 stx %l3, [%l0+%g1]
296 stx %l3, [%l0+%g2]
297 stx %l3, [%l0+%g3]
298
299#endif
300#endif
301
302#ifdef DRAM_SCRUB
303! DRAM_SCRUB_ENABLE
304 add %l6, 0x040, %l0
305 mov 0x1, %l3
306 stx %l3, [%l0+%g0]
307 stx %l3, [%l0+%g1]
308 stx %l3, [%l0+%g2]
309 stx %l3, [%l0+%g3]
310
311! DRAM_SCRUB_FREQ_REG
312 add %l6, 0x018, %l0
313 mov 0x10, %l3
314 stx %l3, [%l0+%g0]
315 stx %l3, [%l0+%g1]
316 stx %l3, [%l0+%g2]
317 stx %l3, [%l0+%g3]
318#endif
319
320!!! Program same values as in mcu_mem_config.v
321
322#ifdef DDR2_533
323ddr2_533_ras_reg_init:
324 add %l6, 0x0b0, %l0 ! DRAM_TRAS_REG
325 mov 0x0c,%l3
326 stx %l3, [%l0+%g0]
327 stx %l3, [%l0+%g1]
328 stx %l3, [%l0+%g2]
329 stx %l3, [%l0+%g3]
330
331!ddr2_533_rp_reg_init:
332! add %l6, 0x0b8, %l0 ! DRAM_TRP_REG - same as POR value
333! mov 0x03,%l3
334! stx %l3, [%l0+%g0]
335! stx %l3, [%l0+%g1]
336! stx %l3, [%l0+%g2]
337! stx %l3, [%l0+%g3]
338
339!ddr2_533_rtp_reg_init:
340! add %l6, 0x0a8, %l0 ! DRAM_TRTP_REG - same as POR value
341! mov 0x02,%l3
342! stx %l3, [%l0+%g0]
343! stx %l3, [%l0+%g1]
344! stx %l3, [%l0+%g2]
345! stx %l3, [%l0+%g3]
346
347ddr2_533_rc_reg_init:
348 add %l6, 0x088, %l0 ! DRAM_TRC_REG
349#if defined(SNG_CHANNEL)
350 mov 0x011,%l3
351#else
352 mov 0x00f,%l3
353#endif
354 stx %l3, [%l0+%g0]
355 stx %l3, [%l0+%g1]
356 stx %l3, [%l0+%g2]
357 stx %l3, [%l0+%g3]
358
359!ddr2_533_rcd_reg_init:
360! add %l6, 0x090, %l0 ! DRAM_TRCD_REG - same as POR value
361! mov 0x03,%l3
362! stx %l3, [%l0+%g0]
363! stx %l3, [%l0+%g1]
364! stx %l3, [%l0+%g2]
365! stx %l3, [%l0+%g3]
366
367ddr2_533_rfc_reg_init:
368 add %l6, 0x0c8, %l0 ! DRAM_TRFC_REG
369 mov 0x014,%l3
370 stx %l3, [%l0+%g0]
371 stx %l3, [%l0+%g1]
372 stx %l3, [%l0+%g2]
373 stx %l3, [%l0+%g3]
374
375ddr2_533_wr_reg_init:
376 add %l6, 0x0c0, %l0 ! DRAM_TWR_REG
377 mov 0x04,%l3
378 stx %l3, [%l0+%g0]
379 stx %l3, [%l0+%g1]
380 stx %l3, [%l0+%g2]
381 stx %l3, [%l0+%g3]
382
383ddr2_533_iwtr_reg_init:
384 add %l6, 0x0e0, %l0 ! DRAM_TIWTR_REG
385 mov 0x03,%l3
386 stx %l3, [%l0+%g0]
387 stx %l3, [%l0+%g1]
388 stx %l3, [%l0+%g2]
389 stx %l3, [%l0+%g3]
390
391ddr2_533_rtw_reg_init:
392 add %l6, 0x0a0, %l0 ! DRAM_TRTW_REG
393#if defined(SNG_CHANNEL)
394 mov 0x0,%l3
395#else
396 mov 0x0,%l3
397#endif
398 stx %l3, [%l0+%g0]
399 stx %l3, [%l0+%g1]
400 stx %l3, [%l0+%g2]
401 stx %l3, [%l0+%g3]
402
403ddr2_533_rrd_reg_init:
404 add %l6, 0x080, %l0 ! DRAM_TRRD_REG
405#if defined(SNG_CHANNEL)
406 mov 5,%l3
407#else
408 mov 3,%l3
409#endif
410 stx %l3, [%l0+%g0]
411 stx %l3, [%l0+%g1]
412 stx %l3, [%l0+%g2]
413 stx %l3, [%l0+%g3]
414
415ddr2_533_faw_reg_init:
416 add %l6, 0x0d8, %l0 ! missing from mcu_defines.h
417 mov 0x0a,%l3
418 stx %l3, [%l0+%g0]
419 stx %l3, [%l0+%g1]
420 stx %l3, [%l0+%g2]
421 stx %l3, [%l0+%g3]
422
423#else // end of #ifdef DDR2_533
424
425ddr2_667_ras_reg_init:
426 add %l6, 0x0b0, %l0 ! DRAM_TRAS_REG
427 mov 0x0f,%l3
428 stx %l3, [%l0+%g0]
429 stx %l3, [%l0+%g1]
430 stx %l3, [%l0+%g2]
431 stx %l3, [%l0+%g3]
432
433ddr2_667_rp_reg_init:
434 add %l6, 0x0b8, %l0 ! DRAM_TRP_REG
435 mov 0x04,%l3
436 stx %l3, [%l0+%g0]
437 stx %l3, [%l0+%g1]
438 stx %l3, [%l0+%g2]
439 stx %l3, [%l0+%g3]
440
441ddr2_667_rtp_reg_init:
442 add %l6, 0x0a8, %l0 ! DRAM_TRTP_REG
443 mov 0x03,%l3
444 stx %l3, [%l0+%g0]
445 stx %l3, [%l0+%g1]
446 stx %l3, [%l0+%g2]
447 stx %l3, [%l0+%g3]
448
449ddr2_667_ref_reg_init:
450 add %l6, 0x020, %l0 ! DRAM_REFRESH_FREQ_REG
451 mov 0xa28,%l3
452 stx %l3, [%l0+%g0]
453 stx %l3, [%l0+%g1]
454 stx %l3, [%l0+%g2]
455 stx %l3, [%l0+%g3]
456
457ddr2_667_rc_reg_init:
458 add %l6, 0x088, %l0 ! DRAM_TRC_REG
459#if defined(SNG_CHANNEL)
460 mov 0x015,%l3
461#else
462 mov 0x013,%l3
463#endif
464 stx %l3, [%l0+%g0]
465 stx %l3, [%l0+%g1]
466 stx %l3, [%l0+%g2]
467 stx %l3, [%l0+%g3]
468
469ddr2_667_rcd_reg_init:
470 add %l6, 0x090, %l0 ! DRAM_TRCD_REG
471 mov 0x04,%l3
472 stx %l3, [%l0+%g0]
473 stx %l3, [%l0+%g1]
474 stx %l3, [%l0+%g2]
475 stx %l3, [%l0+%g3]
476
477ddr2_667_rfc_reg_init:
478 add %l6, 0x0c8, %l0 ! DRAM_TRFC_REG
479 mov 0x019,%l3
480 stx %l3, [%l0+%g0]
481 stx %l3, [%l0+%g1]
482 stx %l3, [%l0+%g2]
483 stx %l3, [%l0+%g3]
484
485ddr2_667_wr_reg_init:
486 add %l6, 0x0c0, %l0 ! DRAM_TWR_REG
487 mov 0x05,%l3
488 stx %l3, [%l0+%g0]
489 stx %l3, [%l0+%g1]
490 stx %l3, [%l0+%g2]
491 stx %l3, [%l0+%g3]
492
493ddr2_667_iwtr_reg_init:
494 add %l6, 0x0e0, %l0 ! DRAM_TIWTR_REG
495 mov 0x03,%l3
496 stx %l3, [%l0+%g0]
497 stx %l3, [%l0+%g1]
498 stx %l3, [%l0+%g2]
499 stx %l3, [%l0+%g3]
500
501ddr2_667_rtw_reg_init:
502 add %l6, 0x0a0, %l0 ! DRAM_TRTW_REG
503#if defined(SNG_CHANNEL)
504 mov 0x0,%l3
505#else
506 mov 0x0,%l3
507#endif
508 stx %l3, [%l0+%g0]
509 stx %l3, [%l0+%g1]
510 stx %l3, [%l0+%g2]
511 stx %l3, [%l0+%g3]
512
513ddr2_667_rrd_reg_init:
514 add %l6, 0x080, %l0 ! DRAM_TRRD_REG
515#if defined(SNG_CHANNEL)
516 mov 5,%l3
517#else
518 mov 3,%l3
519#endif
520 stx %l3, [%l0+%g0]
521 stx %l3, [%l0+%g1]
522 stx %l3, [%l0+%g2]
523 stx %l3, [%l0+%g3]
524
525ddr2_667_faw_reg_init:
526 add %l6, 0x0d8, %l0 ! missing from mcu_defines.h
527 mov 0x0d,%l3
528 stx %l3, [%l0+%g0]
529 stx %l3, [%l0+%g1]
530 stx %l3, [%l0+%g2]
531 stx %l3, [%l0+%g3]
532
533#endif // end of !#ifdef DDR2_533
534
535! DRAM_CAS_LAT_REG
536#ifdef VARY_CAS_LATENCY
537 add %l6, 0x010, %l0
538 mov CAS_LATENCY,%l3
539 stx %l3, [%l0+%g0]
540 stx %l3, [%l0+%g1]
541 stx %l3, [%l0+%g2]
542 stx %l3, [%l0+%g3]
543#endif
544
545
546! AT 04/12/06: Do not reset FBDIMM channel in DTM mode
547#ifndef DTM_ENABLED
548channel_reset_reg_init:
549 add %l6, 0x810, %l0 ! CHANNEL_RESET_REG
550 mov 0x1, %l3
551 stx %l3, [%l0+%g0]
552 stx %l3, [%l0+%g1]
553 stx %l3, [%l0+%g2]
554 stx %l3, [%l0+%g3]
555
556#ifdef POLL_MCU_CHAN_RESET_REG
557mcu0_init_poll:
558 ldx [%l0+%g0], %g4
559 andcc %g4, 1, %i5
560 bz mcu1_init_poll
561 andcc %g4, 2, %i5
562 bz mcu0_init_poll
563 nop
564 EXIT_BAD
565
566mcu1_init_poll:
567 ldx [%l0+%g1], %g4
568 andcc %g4, 1, %i5
569 bz mcu2_init_poll
570 andcc %g4, 2, %i5
571 bz mcu1_init_poll
572 nop
573 EXIT_BAD
574
575mcu2_init_poll:
576 ldx [%l0+%g2], %g4
577 andcc %g4, 1, %i5
578 bz mcu3_init_poll
579 andcc %g4, 2, %i5
580 bz mcu1_init_poll
581 nop
582 EXIT_BAD
583
584mcu3_init_poll:
585 ldx [%l0+%g3], %g4
586 andcc %g4, 1, %i5
587 bz mcu_init_poll_done
588 andcc %g4, 2, %i5
589 bz mcu3_init_poll
590 nop
591 EXIT_BAD
592#endif // ifdef POLL_MCU_CHAN_RESET_REG
593#endif // ifndef DTM_ENABLED
594
595#endif // ifndef NON_SLAM_VECTORS
596
597!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
598!! programm drif_init
599!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
600#ifdef DTM_ENABLED
601
602
603! 04/12/06
604#define DIMM_INIT_DATA 0x0000000000000002
605mcu_init_poll_done:
606 add %l6, 0x1a0, %l0 ! DRAM_DIMM_INIT_REG
607! 04/12/06: need to program DIMM INIT REG to 2.
608 mov DIMM_INIT_DATA, %l3
609#ifdef BANK23
610 stx %l3, [%l0+%g1]
611#endif
612#ifdef BANK45
613 stx %l3, [%l0+%g2]
614#endif
615#ifdef BANK67
616 stx %l3, [%l0+%g3]
617#endif
618! 04/12/06: Enable MCU0 last, which kicks off counters in Sun AMB model
619#ifdef BANK01
620 stx %l3, [%l0+%g0]
621#endif
622
623#endif
624done_mcuctl_init:
625
Full OpenSPARC design & verification tarball including full HDL.