[OpenSPARC-T2-DV] / verif / diag / assembly / include / hred_reset_handler.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: hred_reset_handler.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
.global nc_check_core_master_thread
.global check_core_master_thread
.global nc_chip_master_thread
.global chip_master_thread

#ifdef RESET_CHECK_REG
#include  "spc_por_rdchk.s"
#endif

#ifdef RESET_STAT_CHECK
! Clear %cwp before doing SAVE or using %i/%l/%o, to work around bug
hred_reset_handler_clear_cwp:
    wrpr	0, %cwp
#endif /* RESET_STAT_CHECK */

hred_reset_handler_clear_red_state:
    ! Setup for normal operations
    ! Reset hpstate.red = 0
    rdhpr	%hpstate, %l1
    wrhpr	%l1, 0x820, %hpstate
    wrpr	1, %tl

    ! set hyper trap base addr
    best_set_reg(HV_TRAP_BASE_PA,  %g2, %l7)
    wrhpr %l7, %g0, %htba

    ! Doing this in delay slot of jump from boot prom ...
    !wrpr	0, %g0, %gl

    ! load core id to %g1
    ldxa    [%g0] ASI_INTR_ID, %g1      ! USING this on N2 as a shortcut

    !! CAUTION !! Don't modify G1 until PORTABLE_CORE

#ifndef CMP_THREAD_START
hred_reset_handler_non_cmp_check_master_tid:
    ! Non-cmp thread startup.
#ifndef PORTABLE_CORE
    ! If T0 then chip-master
    brz %g1, nc_chip_master_thread      ! T0 is chip master
#endif
    wr %g0,  ASI_CMP_CORE, %asi
    ! Else figure out if lowest running
    ldxa [0x50]%asi, %g2                ! Who is running ?
    neg %g2, %l1
    xnor %g2, %l1, %l1
    popc %l1, %l1                       ! Get lowest bit set ..
    dec %l1
    cmp %l1, %g1
    bne,a %xcc, nc_check_core_master_thread
    srlx %g1, 3, %l1                    ! Get core-id

nc_chip_master_thread:
                        !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
                        !!!!! System Level Inits in system_inits.s !!!!!
                        !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#include "system_init.s"
nc_core_master_thread:
                        !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
                        !!!!! Core - Level Inits in core_init.s !!!!!
                        !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#include "core_init.s"

    ba,a all_threads

nc_check_core_master_thread:
    mov (CREGS_LSU_CTL_REG_DC << 1 | CREGS_LSU_CTL_REG_IC), %g2
    stxa %g2, [%g0] 0x45                ! Enable L1
    and %g1, 0x7, %l2                   ! Portable core ..
    brz  %l2, nc_core_master_thread     ! T0 is core master
    ldxa [0x50]%asi, %g2                ! Who is running ?
    neg %g2, %l1
    xnor %g2, %l1, %l1
    popc %l1, %l1                       ! Get lowest bit set ..
    dec %l1
    cmp %l1, %g1
    be %xcc, nc_core_master_thread
    nop

#else
    ! CMP thread startup   ! DO NOT MODIFY %G1 until CMP IS Done
    ! Find out if current thread is chip master thread
    !    Use CMP THREAD START and M4 macros for efficiency.
    !    When SIXGUNS is defined, cannot use CMP THREAD START for portability

check_chip_master_thread:
#ifndef SIXGUNS
#ifndef PORTABLE_CORE
changequote([, ])dnl ! The M4_* variables need this
    cmp %g1, M4_master_tid
changequote(`,')dnl ! [] are not quotes anymore
#else
    andcc %g1, 0x7, %g2
#endif
#else
    ! Determine master thread by querying CORE_RUNNING
    mov 0x50, %g3
    ldxa [%g3]ASI_CMP_CORE, %g2         ! Who is running ?
    neg %g2, %l1
    xnor %g2, %l1, %l1
    popc %l1, %l1                       ! Get lowest bit set ..
    dec %l1
    cmp %l1, %g1
#endif
    bne %xcc, check_core_master_thread
    wr %g0,  ASI_CMP_CORE, %asi

chip_master_thread:
                        !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
                        !!!!! System Level Inits in system_inits.s !!!!!
                        !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#include "system_init.s"

start_core_master_threads:
#ifndef PORTABLE_CORE
changequote([, ])dnl ! The M4_* variables need this
    best_set_reg2( M4_core_lsb_mask, %g3, %g4)
changequote(`,')dnl ! [] are not quotes anymore
    ba core_master_thread
    stxa %g4, [ASI_CMP_CORE_RUNNING_RW]%asi      ! Start core_master_threads
#endif

check_core_master_thread:

    ! Find out if current thread is core master thread
    ! by comparing current TID mask with  M4-core-lsb-mask.

#ifndef PORTABLE_CORE
    mov 0x1, %g4
    sllx %g4, %g1, %g4
changequote([, ])dnl ! The M4_* variables need this
    best_set_reg2(M4_core_lsb_mask, %g2, %g3)
changequote(`,')dnl ! [] are not quotes anymore
    mov (CREGS_LSU_CTL_REG_DC << 1 | CREGS_LSU_CTL_REG_IC), %g2
    andcc %g3, %g4, %g0
    bz  %xcc, all_threads
#else
    mov (CREGS_LSU_CTL_REG_DC << 1 | CREGS_LSU_CTL_REG_IC), %g2
    andcc %g1, 0x7, %g4     
    brnz %g4, all_threads
    nop
#endif
    stxa %g2, [%g0] 0x45                ! Enable L1

BOOT_TRACE_TO_SSI
core_master_thread:
                        !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
                        !!!!! Core - Level Inits in core_init.s !!!!!
                        !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#include "core_init.s"

BOOT_TRACE_TO_SSI
start_threads_in_core:
    mov 0xff, %g4
    ! load core id to %g1
    ldxa    [%g0] ASI_INTR_ID, %g1      ! USING this on N2 as a shortcut
    sllx %g4, %g1, %g4
changequote([, ])dnl ! The M4_* variables need this
    best_set_reg2(M4_thread_mask, %g2, %g3)
changequote(`,')dnl  ! Change quote back so all [] are not quoted ..
#ifdef PORTABLE_CORE
    sllx %g3, %g1, %g3
#endif
    and %g3, %g4, %g4
    stxa %g4, [ASI_CMP_CORE_RUNNING_W1S]%asi     ! Start all threads in core


#endif
all_threads:

#ifdef SIXGUNS
#define PORTABLE_CORE
#endif
#ifdef NO_SLAM_INIT
#include "hboot_init.s"
#endif

#ifndef HBOOT_HV_ONLY

hred_reset_handler_setup_partition_id:
    ! %g1 has raw TID
    ! load partition id to %l7
#ifdef PORTABLE_CORE
    mov     0x7, %g2
    and     %g1, %g2, %l7         ! %l7 has TID
#else
    or      %g1, %g0, %l7         ! %l7 has TID
#endif
    setx    part_id_list, %g1, %g2
    sllx    %l7, 3, %l7             ! offset - partition list
    ldx     [%g2 + %l7], %g2	    ! %g2 contains partition ID
                                    ! WARNING DO NOT USE %g2 !!!

    mov	ASI_PARTITION_ID_VAL, %g1
    stxa	%g2, [%g1] ASI_PARTITION_ID


! HWTW setup for real_tange and physical offsets ..
#ifdef MMU_SLAM
#include "mmu_slam.s"
    registerSlam:
    nop
#else

#ifndef NOHWTW
! Set mode for TSB search. The default mode is Sequential
set_tsb_search_mode:
#ifdef TSB_SEARCH_BURST
    mov	ASI_TSB_SEARCH_MODE_ADDR,  %l2
    or	TSB_SEARCH_BURST, %g0, %l1
    stxa	%l1, [%l2] ASI_TSB_SEARCH_MODE_REG
#endif
#ifdef TSB_SEARCH_PREDICTION
    mov	ASI_TSB_SEARCH_MODE_ADDR,  %l2
    or	TSB_SEARCH_PREDICTION, %g0, %l1
    stxa	%l1, [%l2] ASI_TSB_SEARCH_MODE_REG
#endif

hred_physical_offset:
    wr %g0, ASI_MMU_PHYSICAL_OFFSET, %asi
    setx partition_phys_offset_list, %g1, %g3
    umul %g2, 32, %g4
    add %g4, %g3, %g4

! %g2 -> partion ID
! %g3 -> [partition_phys_offset_list]
! %g4 -> [partition_phys_offset_list + PID*32]

hred_physical_offset_0:
    ldx     [%g4], %l1
    stxa    %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi

hred_physical_offset_1:
    ldx     [%g4+8], %l1
    stxa    %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi

hred_physical_offset_2:
    ldx     [%g4+16], %l1
    stxa    %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi

hred_physical_offset_3:
    ldx     [%g4+24], %l1
    stxa    %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi

! Set the ranges as follows
!  3fff - 0
!  3ffff - 4000
!  3fffff - 40000
!  3ffffff - 400000
!
hred_real_range:
    wr %g0, ASI_MMU_REAL_RANGE, %asi
    !!! setx 0x8000048000000800, %g1, %l1
    !!! setx 0x807ffffff8000000, %g1, %l1         ! MAX REAL RANGE !!!

#ifndef MMU_REAL_RANGE_0
    setx    0x800007fff8000000, %g1, %l1
#else
    best_set_reg( MMU_REAL_RANGE_0 , %g1, %l1)
#endif
hred_real_range0:
    stxa    %l1, [ASI_MMU_REAL_RANGE_0] %asi

#ifndef MMU_REAL_RANGE_1
    setx    0x80007ffff8004000, %g1, %l1
#else
    best_set_reg(MMU_REAL_RANGE_1 , %g1, %l1)
#endif
hred_real_range1:
    stxa    %l1, [ASI_MMU_REAL_RANGE_1] %asi

#ifndef MMU_REAL_RANGE_2
    setx    0x8007fffff8040000, %g1, %l1
#else
    best_set_reg(MMU_REAL_RANGE_2 , %g1, %l1)
#endif
hred_real_range2:
    stxa    %l1, [ASI_MMU_REAL_RANGE_2] %asi

#ifndef MMU_REAL_RANGE_3
    setx    0x807ffffff8400000, %g1, %l1
#else
    best_set_reg(MMU_REAL_RANGE_3 , %g1, %l1)
#endif
hred_real_range3:
    stxa    %l1, [ASI_MMU_REAL_RANGE_3] %asi

#endif

hred_tsb_config:
    ! Load tsb config/base from memory
    ! and write to corresponding ASI's
    ! set tsb-config-regs for one partition

    setx    tsb_config_base_list, %l0, %g1
    umul %g2, 80, %g2 		! %g2 contains offset to tsb_config_base_list
    add	%g1, %g2, %g1		! %g1 contains pointer to tsb_config_base_list

    wr %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %asi


hred_tsb_z_config_0:
    !!! Write CONTEXT ZERO, TSB_CONFIG_0 !!!

    ldx [%g1], %g4          ! part_N_z_tsb_config_0
    stxa	%g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi


hred_tsb_nz_config_0:
    !!! Write CONTEXT NON-ZERO, TSB_CONFIG_0 !!!

    ldx [%g1+8], %g4          ! part_N_nz_tsb_config_0
    stxa	%g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi

hred_tsb_z_config_1:
    !!! Write CONTEXT ZERO, TSB_CONFIG_1 !!!

    ldx [%g1+16], %g4          ! part_N_z_tsb_config_1
    stxa	%g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi

hred_tsb_nz_config_1:
    !!! Write CONTEXT NON-ZERO, TSB_CONFIG_1 !!!

    ldx [%g1+24], %g4          ! part_N_nz_tsb_config_1
    stxa	%g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi

hred_tsb_z_config_2:
    !!! Write CONTEXT ZERO, TSB_CONFIG_2 !!!

    ldx [%g1+32], %g4          ! part_N_z_tsb_config_2
    stxa	%g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi

hred_tsb_nz_config_2:
    !!! Write CONTEXT NON-ZERO, TSB_CONFIG_2 !!!

    ldx [%g1+40], %g4          ! part_N_nz_tsb_config_2
    stxa	%g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi


hred_tsb_z_config_3:
    !!! Write CONTEXT ZERO, TSB_CONFIG_3 !!!

    ldx [%g1+48], %g4          ! part_N_z_tsb_config_2
    stxa	%g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi

hred_tsb_nz_config_3:
    !!! Write CONTEXT NON-ZERO, TSB_CONFIG_3 !!!

    ldx [%g1+56], %g4          ! part_N_nz_tsb_config_3
    stxa	%g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi

#endif

#endif

#ifndef NOPMUENABLE
hred_reset_handler_enable_pmu:
    ! Enable PMU for counting instruction types
    set cregs_pcr_reg, %g2
    wr %g2, %g0, %pcr
#endif

    ! Initialize control registers per defines
    ! Added conditionals, assuming that these values init at 0x0..
ctrl_reg_init:
    wr	%g0, cregs_fprs_imm, %fprs
    wr	%g0, cregs_ccr_imm, %ccr
    wr	%g0, cregs_asi_imm, %asi
    best_set_reg(cregs_tick_r64, %g1, %g2)
    wrpr	%g2, %tick
    wrpr	cregs_pil_imm, %pil
#if (NO_SLAM_INIT || CREGS_CANSAVE > 0 || CREGS_CANSAVE > 0x0)
    wrpr	cregs_cansave_imm, %cansave
#endif
#if (NO_SLAM_INIT || CREGS_CANRESTORE > 0 || CREGS_CANRESTORE > 0x0)
    wrpr	cregs_canrestore_imm, %canrestore
#endif
#if (NO_SLAM_INIT || CREGS_OTHERWIN > 0 || CREGS_OTHERWIN > 0x0)
    wrpr	cregs_otherwin_imm, %otherwin
#endif
#if (NO_SLAM_INIT || CREGS_CLEANWIN > 0 || CREGS_CLEANWIN > 0x0)
    wrpr	cregs_cleanwin_imm, %cleanwin
#endif
#if (NO_SLAM_INIT || CREGS_WSTATE > 0 || CREGS_WSTATE > 0x0)
    wrpr	cregs_wstate_imm, %wstate
#endif

    ! Set lsu control reg. enable dcache, icache, immu, dmmu

    best_set_reg(cregs_lsu_ctl_reg_r64, %g1, %l7)
    stxa	%l7, [%g0] ASI_LSU_CTL_REG

    ! Enable error detection
    ! CETER is per thread
#ifndef NOERRCHK
enable_strand_err_traps:
    add %g0, CETER_VA, %g4
    add %g0, CETER_DATA, %g1
    sllx %g1, 60, %g1
    stxa %g1, [%g4]0x4c		!! CETER
#endif

#ifdef RESET_STAT_CHECK
hred_reset_handler_check_reset_stat:
#include "ccu_defines.h"
    setx RESET_STAT, %g1, %g2
    ldx [%g2], %g1
    and %g1, 2, %g1         !! nonzero if WMR
    brz %g1, done_reset_stat_check
    nop
this_is_wmr:
    mov 0x8, %g1
    stxa %g0, [%g1]ASI_PRIMARY_CONTEXT_REG
done_reset_stat_check:
#endif

#ifdef ENABLE_INTR0x60
#include "interrupt0x60_thread_init.s"
#endif /* ENABLE_INTR0x60 */

#ifndef DTM_ENABLED
#if defined(ENABLE_PCIE_LINK_TRAINING) || defined(FC_NO_PEU_VERA)
! ***************************************************************
! PCI Express Link Training included here for the master thread
! ***************************************************************
#ifdef CMP_THREAD_START
    ldxa    [%g0] ASI_INTR_ID, %g1
changequote([, ])dnl
    cmp     %g1, M4_master_tid
changequote(`,')dnl
    bne     %xcc, skip_wait_for_link
    nop
#include "system_init_pcie_wait.s"
#else
#include "system_init_pcie_wait.s"
#endif /* CMP_THREAD_START */

skip_wait_for_link:
    nop
#endif /* (ENABLE_PCIE_LINK_TRAINING) || defined(FC_NO_PEU_VERA) */
#endif /* not DTM_ENABLED */
	
#ifdef SYNC_THREADS
sync_thread:
    cmp_sync_threads
#endif

#ifdef ENABLE_NIU_BACKGROUND_PACKETS_IN_BOOT

#ifndef FC_NO_NIU_T2
#include "niu_start_bg_pkts.s"
#endif

#endif /* ENABLE_NIU_BACKGROUND_PACKETS_IN_BOOT */

#ifndef HBOOT_HV_ONLY
hred_reset_handler_jump_to_priv_reset:
    best_set_reg(PRIV_RESET_VA, %g1, %g2)
    wrhpr  cregs_htstate_r64, %htstate
    mov    0x0, %o0	/* please don't delete this , used in customized */
                        /* IMMU miss trap */
    jmp	%g2
    wrhpr  %g0, 0x0, %hpstate
    nop
    nop

#else
hboot_hv_only:
    !! jump directly to user code - in hpriv mode ..
    setx    start_label_list, %g1, %g2
    ldx     [%g2], %o5        ! %o5 contains start_label
    mov 0x0, %o3
    mov 0x1, %o4
    ta  T_CHANGE_CTX

#endif
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: hred_reset_handler.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	.global nc_check_core_master_thread
	39	.global check_core_master_thread
	40	.global nc_chip_master_thread
	41	.global chip_master_thread
	42
	43	#ifdef RESET_CHECK_REG
	44	#include "spc_por_rdchk.s"
	45	#endif
	46
	47	#ifdef RESET_STAT_CHECK
	48	! Clear %cwp before doing SAVE or using %i/%l/%o, to work around bug
	49	hred_reset_handler_clear_cwp:
	50	wrpr 0, %cwp
	51	#endif /* RESET_STAT_CHECK */
	52
	53	hred_reset_handler_clear_red_state:
	54	! Setup for normal operations
	55	! Reset hpstate.red = 0
	56	rdhpr %hpstate, %l1
	57	wrhpr %l1, 0x820, %hpstate
	58	wrpr 1, %tl
	59
	60	! set hyper trap base addr
	61	best_set_reg(HV_TRAP_BASE_PA, %g2, %l7)
	62	wrhpr %l7, %g0, %htba
	63
	64	! Doing this in delay slot of jump from boot prom ...
65	!wrpr 0, %g0, %gl
66
67	! load core id to %g1
68	ldxa [%g0] ASI_INTR_ID, %g1 ! USING this on N2 as a shortcut
69
70	!! CAUTION !! Don't modify G1 until PORTABLE_CORE
71
72	#ifndef CMP_THREAD_START
73	hred_reset_handler_non_cmp_check_master_tid:
74	! Non-cmp thread startup.
75	#ifndef PORTABLE_CORE
76	! If T0 then chip-master
77	brz %g1, nc_chip_master_thread ! T0 is chip master
78	#endif
79	wr %g0, ASI_CMP_CORE, %asi
80	! Else figure out if lowest running
81	ldxa [0x50]%asi, %g2 ! Who is running ?
82	neg %g2, %l1
83	xnor %g2, %l1, %l1
84	popc %l1, %l1 ! Get lowest bit set ..
85	dec %l1
86	cmp %l1, %g1
87	bne,a %xcc, nc_check_core_master_thread
88	srlx %g1, 3, %l1 ! Get core-id
89
90	nc_chip_master_thread:
91	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
92	!!!!! System Level Inits in system_inits.s !!!!!
93	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
94	#include "system_init.s"
95	nc_core_master_thread:
96	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
97	!!!!! Core - Level Inits in core_init.s !!!!!
98	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
99	#include "core_init.s"
100
101	ba,a all_threads
102
103	nc_check_core_master_thread:
104	mov (CREGS_LSU_CTL_REG_DC << 1 \| CREGS_LSU_CTL_REG_IC), %g2
105	stxa %g2, [%g0] 0x45 ! Enable L1
106	and %g1, 0x7, %l2 ! Portable core ..
107	brz %l2, nc_core_master_thread ! T0 is core master
108	ldxa [0x50]%asi, %g2 ! Who is running ?
109	neg %g2, %l1
110	xnor %g2, %l1, %l1
111	popc %l1, %l1 ! Get lowest bit set ..
112	dec %l1
113	cmp %l1, %g1
114	be %xcc, nc_core_master_thread
115	nop
116
117	#else
118	! CMP thread startup ! DO NOT MODIFY %G1 until CMP IS Done
119	! Find out if current thread is chip master thread
120	! Use CMP THREAD START and M4 macros for efficiency.
121	! When SIXGUNS is defined, cannot use CMP THREAD START for portability
122
123	check_chip_master_thread:
124	#ifndef SIXGUNS
125	#ifndef PORTABLE_CORE
126	changequote([, ])dnl ! The M4_* variables need this
127	cmp %g1, M4_master_tid
128	changequote(`,')dnl ! [] are not quotes anymore
129	#else
130	andcc %g1, 0x7, %g2
131	#endif
132	#else
133	! Determine master thread by querying CORE_RUNNING
134	mov 0x50, %g3
135	ldxa [%g3]ASI_CMP_CORE, %g2 ! Who is running ?
136	neg %g2, %l1
137	xnor %g2, %l1, %l1
138	popc %l1, %l1 ! Get lowest bit set ..
139	dec %l1
140	cmp %l1, %g1
141	#endif
142	bne %xcc, check_core_master_thread
143	wr %g0, ASI_CMP_CORE, %asi
144
145	chip_master_thread:
146	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
147	!!!!! System Level Inits in system_inits.s !!!!!
148	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
149	#include "system_init.s"
150
151	start_core_master_threads:
152	#ifndef PORTABLE_CORE
153	changequote([, ])dnl ! The M4_* variables need this
154	best_set_reg2( M4_core_lsb_mask, %g3, %g4)
155	changequote(`,')dnl ! [] are not quotes anymore
156	ba core_master_thread
157	stxa %g4, [ASI_CMP_CORE_RUNNING_RW]%asi ! Start core_master_threads
158	#endif
159
160	check_core_master_thread:
161
162	! Find out if current thread is core master thread
163	! by comparing current TID mask with M4-core-lsb-mask.
164
165	#ifndef PORTABLE_CORE
166	mov 0x1, %g4
167	sllx %g4, %g1, %g4
168	changequote([, ])dnl ! The M4_* variables need this
169	best_set_reg2(M4_core_lsb_mask, %g2, %g3)
170	changequote(`,')dnl ! [] are not quotes anymore
171	mov (CREGS_LSU_CTL_REG_DC << 1 \| CREGS_LSU_CTL_REG_IC), %g2
172	andcc %g3, %g4, %g0
173	bz %xcc, all_threads
174	#else
175	mov (CREGS_LSU_CTL_REG_DC << 1 \| CREGS_LSU_CTL_REG_IC), %g2
176	andcc %g1, 0x7, %g4
177	brnz %g4, all_threads
178	nop
179	#endif
180	stxa %g2, [%g0] 0x45 ! Enable L1
181
182	BOOT_TRACE_TO_SSI
183	core_master_thread:
184	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
185	!!!!! Core - Level Inits in core_init.s !!!!!
186	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
187	#include "core_init.s"
188
189	BOOT_TRACE_TO_SSI
190	start_threads_in_core:
191	mov 0xff, %g4
192	! load core id to %g1
193	ldxa [%g0] ASI_INTR_ID, %g1 ! USING this on N2 as a shortcut
194	sllx %g4, %g1, %g4
195	changequote([, ])dnl ! The M4_* variables need this
196	best_set_reg2(M4_thread_mask, %g2, %g3)
197	changequote(`,')dnl ! Change quote back so all [] are not quoted ..
198	#ifdef PORTABLE_CORE
199	sllx %g3, %g1, %g3
200	#endif
201	and %g3, %g4, %g4
202	stxa %g4, [ASI_CMP_CORE_RUNNING_W1S]%asi ! Start all threads in core
203
204
205	#endif
206	all_threads:
207
208	#ifdef SIXGUNS
209	#define PORTABLE_CORE
210	#endif
211	#ifdef NO_SLAM_INIT
212	#include "hboot_init.s"
213	#endif
214
215	#ifndef HBOOT_HV_ONLY
216
217	hred_reset_handler_setup_partition_id:
218	! %g1 has raw TID
219	! load partition id to %l7
220	#ifdef PORTABLE_CORE
221	mov 0x7, %g2
222	and %g1, %g2, %l7 ! %l7 has TID
223	#else
224	or %g1, %g0, %l7 ! %l7 has TID
225	#endif
226	setx part_id_list, %g1, %g2
227	sllx %l7, 3, %l7 ! offset - partition list
228	ldx [%g2 + %l7], %g2 ! %g2 contains partition ID
229	! WARNING DO NOT USE %g2 !!!
230
231	mov ASI_PARTITION_ID_VAL, %g1
232	stxa %g2, [%g1] ASI_PARTITION_ID
233
234
235	! HWTW setup for real_tange and physical offsets ..
236	#ifdef MMU_SLAM
237	#include "mmu_slam.s"
238	registerSlam:
239	nop
240	#else
241
242	#ifndef NOHWTW
243	! Set mode for TSB search. The default mode is Sequential
244	set_tsb_search_mode:
245	#ifdef TSB_SEARCH_BURST
246	mov ASI_TSB_SEARCH_MODE_ADDR, %l2
247	or TSB_SEARCH_BURST, %g0, %l1
248	stxa %l1, [%l2] ASI_TSB_SEARCH_MODE_REG
249	#endif
250	#ifdef TSB_SEARCH_PREDICTION
251	mov ASI_TSB_SEARCH_MODE_ADDR, %l2
252	or TSB_SEARCH_PREDICTION, %g0, %l1
253	stxa %l1, [%l2] ASI_TSB_SEARCH_MODE_REG
254	#endif
255
256	hred_physical_offset:
257	wr %g0, ASI_MMU_PHYSICAL_OFFSET, %asi
258	setx partition_phys_offset_list, %g1, %g3
259	umul %g2, 32, %g4
260	add %g4, %g3, %g4
261
262	! %g2 -> partion ID
263	! %g3 -> [partition_phys_offset_list]
264	! %g4 -> [partition_phys_offset_list + PID*32]
265
266	hred_physical_offset_0:
267	ldx [%g4], %l1
268	stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
269
270	hred_physical_offset_1:
271	ldx [%g4+8], %l1
272	stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
273
274	hred_physical_offset_2:
275	ldx [%g4+16], %l1
276	stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
277
278	hred_physical_offset_3:
279	ldx [%g4+24], %l1
280	stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
281
282	! Set the ranges as follows
283	! 3fff - 0
284	! 3ffff - 4000
285	! 3fffff - 40000
286	! 3ffffff - 400000
287	!
288	hred_real_range:
289	wr %g0, ASI_MMU_REAL_RANGE, %asi
290	!!! setx 0x8000048000000800, %g1, %l1
291	!!! setx 0x807ffffff8000000, %g1, %l1 ! MAX REAL RANGE !!!
292
293	#ifndef MMU_REAL_RANGE_0
294	setx 0x800007fff8000000, %g1, %l1
295	#else
296	best_set_reg( MMU_REAL_RANGE_0 , %g1, %l1)
297	#endif
298	hred_real_range0:
299	stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
300
301	#ifndef MMU_REAL_RANGE_1
302	setx 0x80007ffff8004000, %g1, %l1
303	#else
304	best_set_reg(MMU_REAL_RANGE_1 , %g1, %l1)
305	#endif
306	hred_real_range1:
307	stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
308
309	#ifndef MMU_REAL_RANGE_2
310	setx 0x8007fffff8040000, %g1, %l1
311	#else
312	best_set_reg(MMU_REAL_RANGE_2 , %g1, %l1)
313	#endif
314	hred_real_range2:
315	stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
316
317	#ifndef MMU_REAL_RANGE_3
318	setx 0x807ffffff8400000, %g1, %l1
319	#else
320	best_set_reg(MMU_REAL_RANGE_3 , %g1, %l1)
321	#endif
322	hred_real_range3:
323	stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
324
325	#endif
326
327	hred_tsb_config:
328	! Load tsb config/base from memory
329	! and write to corresponding ASI's
330	! set tsb-config-regs for one partition
331
332	setx tsb_config_base_list, %l0, %g1
333	umul %g2, 80, %g2 ! %g2 contains offset to tsb_config_base_list
334	add %g1, %g2, %g1 ! %g1 contains pointer to tsb_config_base_list
335
336	wr %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %asi
337
338
339	hred_tsb_z_config_0:
340	!!! Write CONTEXT ZERO, TSB_CONFIG_0 !!!
341
342	ldx [%g1], %g4 ! part_N_z_tsb_config_0
343	stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
344
345
346	hred_tsb_nz_config_0:
347	!!! Write CONTEXT NON-ZERO, TSB_CONFIG_0 !!!
348
349	ldx [%g1+8], %g4 ! part_N_nz_tsb_config_0
350	stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
351
352	hred_tsb_z_config_1:
353	!!! Write CONTEXT ZERO, TSB_CONFIG_1 !!!
354
355	ldx [%g1+16], %g4 ! part_N_z_tsb_config_1
356	stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
357
358	hred_tsb_nz_config_1:
359	!!! Write CONTEXT NON-ZERO, TSB_CONFIG_1 !!!
360
361	ldx [%g1+24], %g4 ! part_N_nz_tsb_config_1
362	stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
363
364	hred_tsb_z_config_2:
365	!!! Write CONTEXT ZERO, TSB_CONFIG_2 !!!
366
367	ldx [%g1+32], %g4 ! part_N_z_tsb_config_2
368	stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
369
370	hred_tsb_nz_config_2:
371	!!! Write CONTEXT NON-ZERO, TSB_CONFIG_2 !!!
372
373	ldx [%g1+40], %g4 ! part_N_nz_tsb_config_2
374	stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
375
376
377	hred_tsb_z_config_3:
378	!!! Write CONTEXT ZERO, TSB_CONFIG_3 !!!
379
380	ldx [%g1+48], %g4 ! part_N_z_tsb_config_2
381	stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
382
383	hred_tsb_nz_config_3:
384	!!! Write CONTEXT NON-ZERO, TSB_CONFIG_3 !!!
385
386	ldx [%g1+56], %g4 ! part_N_nz_tsb_config_3
387	stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
388
389	#endif
390
391	#endif
392
393	#ifndef NOPMUENABLE
394	hred_reset_handler_enable_pmu:
395	! Enable PMU for counting instruction types
396	set cregs_pcr_reg, %g2
397	wr %g2, %g0, %pcr
398	#endif
399
400	! Initialize control registers per defines
401	! Added conditionals, assuming that these values init at 0x0..
402	ctrl_reg_init:
403	wr %g0, cregs_fprs_imm, %fprs
404	wr %g0, cregs_ccr_imm, %ccr
405	wr %g0, cregs_asi_imm, %asi
406	best_set_reg(cregs_tick_r64, %g1, %g2)
407	wrpr %g2, %tick
408	wrpr cregs_pil_imm, %pil
409	#if (NO_SLAM_INIT \|\| CREGS_CANSAVE > 0 \|\| CREGS_CANSAVE > 0x0)
410	wrpr cregs_cansave_imm, %cansave
411	#endif
412	#if (NO_SLAM_INIT \|\| CREGS_CANRESTORE > 0 \|\| CREGS_CANRESTORE > 0x0)
413	wrpr cregs_canrestore_imm, %canrestore
414	#endif
415	#if (NO_SLAM_INIT \|\| CREGS_OTHERWIN > 0 \|\| CREGS_OTHERWIN > 0x0)
416	wrpr cregs_otherwin_imm, %otherwin
417	#endif
418	#if (NO_SLAM_INIT \|\| CREGS_CLEANWIN > 0 \|\| CREGS_CLEANWIN > 0x0)
419	wrpr cregs_cleanwin_imm, %cleanwin
420	#endif
421	#if (NO_SLAM_INIT \|\| CREGS_WSTATE > 0 \|\| CREGS_WSTATE > 0x0)
422	wrpr cregs_wstate_imm, %wstate
423	#endif
424
425	! Set lsu control reg. enable dcache, icache, immu, dmmu
426
427	best_set_reg(cregs_lsu_ctl_reg_r64, %g1, %l7)
428	stxa %l7, [%g0] ASI_LSU_CTL_REG
429
430	! Enable error detection
431	! CETER is per thread
432	#ifndef NOERRCHK
433	enable_strand_err_traps:
434	add %g0, CETER_VA, %g4
435	add %g0, CETER_DATA, %g1
436	sllx %g1, 60, %g1
437	stxa %g1, [%g4]0x4c !! CETER
438	#endif
439
440	#ifdef RESET_STAT_CHECK
441	hred_reset_handler_check_reset_stat:
442	#include "ccu_defines.h"
443	setx RESET_STAT, %g1, %g2
444	ldx [%g2], %g1
445	and %g1, 2, %g1 !! nonzero if WMR
446	brz %g1, done_reset_stat_check
447	nop
448	this_is_wmr:
449	mov 0x8, %g1
450	stxa %g0, [%g1]ASI_PRIMARY_CONTEXT_REG
451	done_reset_stat_check:
452	#endif
453
454	#ifdef ENABLE_INTR0x60
455	#include "interrupt0x60_thread_init.s"
456	#endif /* ENABLE_INTR0x60 */
457
458	#ifndef DTM_ENABLED
459	#if defined(ENABLE_PCIE_LINK_TRAINING) \|\| defined(FC_NO_PEU_VERA)
460	! ***************************************************************
461	! PCI Express Link Training included here for the master thread
462	! ***************************************************************
463	#ifdef CMP_THREAD_START
464	ldxa [%g0] ASI_INTR_ID, %g1
465	changequote([, ])dnl
466	cmp %g1, M4_master_tid
467	changequote(`,')dnl
468	bne %xcc, skip_wait_for_link
469	nop
470	#include "system_init_pcie_wait.s"
471	#else
472	#include "system_init_pcie_wait.s"
473	#endif /* CMP_THREAD_START */
474
475	skip_wait_for_link:
476	nop
477	#endif /* (ENABLE_PCIE_LINK_TRAINING) \|\| defined(FC_NO_PEU_VERA) */
478	#endif /* not DTM_ENABLED */
479
480	#ifdef SYNC_THREADS
481	sync_thread:
482	cmp_sync_threads
483	#endif
484
485	#ifdef ENABLE_NIU_BACKGROUND_PACKETS_IN_BOOT
486
487	#ifndef FC_NO_NIU_T2
488	#include "niu_start_bg_pkts.s"
489	#endif
490
491	#endif /* ENABLE_NIU_BACKGROUND_PACKETS_IN_BOOT */
492
493	#ifndef HBOOT_HV_ONLY
494	hred_reset_handler_jump_to_priv_reset:
495	best_set_reg(PRIV_RESET_VA, %g1, %g2)
496	wrhpr cregs_htstate_r64, %htstate
497	mov 0x0, %o0 /* please don't delete this , used in customized */
498	/* IMMU miss trap */
499	jmp %g2
500	wrhpr %g0, 0x0, %hpstate
501	nop
502	nop
503
504	#else
505	hboot_hv_only:
506	!! jump directly to user code - in hpriv mode ..
507	setx start_label_list, %g1, %g2
508	ldx [%g2], %o5 ! %o5 contains start_label
509	mov 0x0, %o3
510	mov 0x1, %o4
511	ta T_CHANGE_CTX
512
513	#endif