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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / interrupt0x60_handler.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: interrupt0x60_handler.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#ifdef USE_BOBO
39#include "bobo_defines.h"
40#endif /* USE_BOBO */
41
42SECTION .HTRAPS
43.text
44.global intr0x60_handler
45
46intr0x60_handler:
47 mov %g7, %o7 ! Restore %o7
48 ldxa [%g0] ASI_INTR_ID, %g1 ! Get the thread number
49
50 ldxa [%g0] ASI_INTR_R, %g2 ! Get the interrupt vector number
51
52 setx intr0x60_ivn_to_ig, %g4, %g3
53 ldub [%g3+%g2], %g4
54
55 cmp %g4, INTR0x60_IG_CC
56 be intr0x60_handle_cc
57 nop
58
59#ifdef INTR0x60_NIU_TX_IV_0
60 cmp %g4, INTR0x60_IG_NIU_TX
61 be intr0x60_handle_niu_tx
62 nop
63#endif /* INTR0x60_NIU_TX_IV_0 */
64
65#ifdef INTR0x60_NIU_RX_IV_0
66 cmp %g4, INTR0x60_IG_NIU_RX
67 be intr0x60_handle_niu_rx
68 nop
69#endif /* INTR0x60_NIU_RX_IV_0 */
70
71#ifdef INTR0x60_MONDO_IV
72 cmp %g4, INTR0x60_IG_PIU
73 be intr0x60_handle_piu
74 nop
75#endif /* INTR0x60_MONDO_IV */
76
77#if (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV)
78 cmp %g4, INTR0x60_IG_SSI_ERR
79 be intr0x60_handle_ssi_err
80 nop
81#endif /* (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV) */
82
83#if (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
84 cmp %g4, INTR0x60_IG_SSI_INT
85 be intr0x60_handle_ssi_int
86 nop
87#endif /* (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV) */
88
89/* If we get here, we got an unexpected vector number */
90intr0x60_bad_ivn:
91 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_bad_ivn)) -> printf("ERROR: Bad interrupt vector number",*,1)
92 EXIT_BAD
93
94
95/************************************************************************/
96/* Handle cross-call interrupts */
97
98intr0x60_handle_cc:
99 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_cc)) -> printf("INFO: Cross-call interrupt received",*,1)
100#ifndef INTR0x60_CC_DEST_ALL
101 /* Make sure that this thread is allowed to receive cross-calls */
102 setx intr0x60_handle_cc_thread_table, %g5, %g4
103#ifdef PORTABLE_CORE
104 and %g1, 0x7, %g5
105 ldub [%g4+%g5], %g4
106#else
107 ldub [%g4+%g1], %g4
108#endif
109 brz %g4, intr0x60_handle_cc_bad_thread
110 nop
111#endif /* INTR0x60_CC_DEST_ALL */
112
113 /* Include any extra cross-call handler from the user */
114 /* The code can assume that %g1 is the thread and %g2 is the vector */
115#ifdef INTR0x60_CC_EXTRA_HANDLER
116intr0x60_handle_cc_extra_handler:
117INTR0x60_CC_EXTRA_HANDLER
118#endif /* INTR0x60_CC_EXTRA_HANDLER */
119
120intr0x60_handle_cc_retry:
121 /* Retry the instruction that was trapped */
122 retry
123
124#ifndef INTR0x60_CC_DEST_ALL
125intr0x60_handle_cc_bad_thread:
126 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_cc_bad_thread)) -> printf("ERROR: Cross-call received on unexpected thread",*,1)
127 EXIT_BAD
128
129.data
130intr0x60_handle_cc_thread_table:
131#if defined(INTR0x60_CC_DEST_0)
132 .byte 1
133#else
134 .byte 0
135#endif
136#if defined(INTR0x60_CC_DEST_1)
137 .byte 1
138#else
139 .byte 0
140#endif
141#if defined(INTR0x60_CC_DEST_2)
142 .byte 1
143#else
144 .byte 0
145#endif
146#if defined(INTR0x60_CC_DEST_3)
147 .byte 1
148#else
149 .byte 0
150#endif
151#if defined(INTR0x60_CC_DEST_4)
152 .byte 1
153#else
154 .byte 0
155#endif
156#if defined(INTR0x60_CC_DEST_5)
157 .byte 1
158#else
159 .byte 0
160#endif
161#if defined(INTR0x60_CC_DEST_6)
162 .byte 1
163#else
164 .byte 0
165#endif
166#if defined(INTR0x60_CC_DEST_7)
167 .byte 1
168#else
169 .byte 0
170#endif
171#if defined(INTR0x60_CC_DEST_8)
172 .byte 1
173#else
174 .byte 0
175#endif
176#if defined(INTR0x60_CC_DEST_9)
177 .byte 1
178#else
179 .byte 0
180#endif
181#if defined(INTR0x60_CC_DEST_10)
182 .byte 1
183#else
184 .byte 0
185#endif
186#if defined(INTR0x60_CC_DEST_11)
187 .byte 1
188#else
189 .byte 0
190#endif
191#if defined(INTR0x60_CC_DEST_12)
192 .byte 1
193#else
194 .byte 0
195#endif
196#if defined(INTR0x60_CC_DEST_13)
197 .byte 1
198#else
199 .byte 0
200#endif
201#if defined(INTR0x60_CC_DEST_14)
202 .byte 1
203#else
204 .byte 0
205#endif
206#if defined(INTR0x60_CC_DEST_15)
207 .byte 1
208#else
209 .byte 0
210#endif
211#if defined(INTR0x60_CC_DEST_16)
212 .byte 1
213#else
214 .byte 0
215#endif
216#if defined(INTR0x60_CC_DEST_17)
217 .byte 1
218#else
219 .byte 0
220#endif
221#if defined(INTR0x60_CC_DEST_18)
222 .byte 1
223#else
224 .byte 0
225#endif
226#if defined(INTR0x60_CC_DEST_19)
227 .byte 1
228#else
229 .byte 0
230#endif
231#if defined(INTR0x60_CC_DEST_20)
232 .byte 1
233#else
234 .byte 0
235#endif
236#if defined(INTR0x60_CC_DEST_21)
237 .byte 1
238#else
239 .byte 0
240#endif
241#if defined(INTR0x60_CC_DEST_22)
242 .byte 1
243#else
244 .byte 0
245#endif
246#if defined(INTR0x60_CC_DEST_23)
247 .byte 1
248#else
249 .byte 0
250#endif
251#if defined(INTR0x60_CC_DEST_24)
252 .byte 1
253#else
254 .byte 0
255#endif
256#if defined(INTR0x60_CC_DEST_25)
257 .byte 1
258#else
259 .byte 0
260#endif
261#if defined(INTR0x60_CC_DEST_26)
262 .byte 1
263#else
264 .byte 0
265#endif
266#if defined(INTR0x60_CC_DEST_27)
267 .byte 1
268#else
269 .byte 0
270#endif
271#if defined(INTR0x60_CC_DEST_28)
272 .byte 1
273#else
274 .byte 0
275#endif
276#if defined(INTR0x60_CC_DEST_29)
277 .byte 1
278#else
279 .byte 0
280#endif
281#if defined(INTR0x60_CC_DEST_30)
282 .byte 1
283#else
284 .byte 0
285#endif
286#if defined(INTR0x60_CC_DEST_31)
287 .byte 1
288#else
289 .byte 0
290#endif
291#if defined(INTR0x60_CC_DEST_32)
292 .byte 1
293#else
294 .byte 0
295#endif
296#if defined(INTR0x60_CC_DEST_33)
297 .byte 1
298#else
299 .byte 0
300#endif
301#if defined(INTR0x60_CC_DEST_34)
302 .byte 1
303#else
304 .byte 0
305#endif
306#if defined(INTR0x60_CC_DEST_35)
307 .byte 1
308#else
309 .byte 0
310#endif
311#if defined(INTR0x60_CC_DEST_36)
312 .byte 1
313#else
314 .byte 0
315#endif
316#if defined(INTR0x60_CC_DEST_37)
317 .byte 1
318#else
319 .byte 0
320#endif
321#if defined(INTR0x60_CC_DEST_38)
322 .byte 1
323#else
324 .byte 0
325#endif
326#if defined(INTR0x60_CC_DEST_39)
327 .byte 1
328#else
329 .byte 0
330#endif
331#if defined(INTR0x60_CC_DEST_40)
332 .byte 1
333#else
334 .byte 0
335#endif
336#if defined(INTR0x60_CC_DEST_41)
337 .byte 1
338#else
339 .byte 0
340#endif
341#if defined(INTR0x60_CC_DEST_42)
342 .byte 1
343#else
344 .byte 0
345#endif
346#if defined(INTR0x60_CC_DEST_43)
347 .byte 1
348#else
349 .byte 0
350#endif
351#if defined(INTR0x60_CC_DEST_44)
352 .byte 1
353#else
354 .byte 0
355#endif
356#if defined(INTR0x60_CC_DEST_45)
357 .byte 1
358#else
359 .byte 0
360#endif
361#if defined(INTR0x60_CC_DEST_46)
362 .byte 1
363#else
364 .byte 0
365#endif
366#if defined(INTR0x60_CC_DEST_47)
367 .byte 1
368#else
369 .byte 0
370#endif
371#if defined(INTR0x60_CC_DEST_48)
372 .byte 1
373#else
374 .byte 0
375#endif
376#if defined(INTR0x60_CC_DEST_49)
377 .byte 1
378#else
379 .byte 0
380#endif
381#if defined(INTR0x60_CC_DEST_50)
382 .byte 1
383#else
384 .byte 0
385#endif
386#if defined(INTR0x60_CC_DEST_51)
387 .byte 1
388#else
389 .byte 0
390#endif
391#if defined(INTR0x60_CC_DEST_52)
392 .byte 1
393#else
394 .byte 0
395#endif
396#if defined(INTR0x60_CC_DEST_53)
397 .byte 1
398#else
399 .byte 0
400#endif
401#if defined(INTR0x60_CC_DEST_54)
402 .byte 1
403#else
404 .byte 0
405#endif
406#if defined(INTR0x60_CC_DEST_55)
407 .byte 1
408#else
409 .byte 0
410#endif
411#if defined(INTR0x60_CC_DEST_56)
412 .byte 1
413#else
414 .byte 0
415#endif
416#if defined(INTR0x60_CC_DEST_57)
417 .byte 1
418#else
419 .byte 0
420#endif
421#if defined(INTR0x60_CC_DEST_58)
422 .byte 1
423#else
424 .byte 0
425#endif
426#if defined(INTR0x60_CC_DEST_59)
427 .byte 1
428#else
429 .byte 0
430#endif
431#if defined(INTR0x60_CC_DEST_60)
432 .byte 1
433#else
434 .byte 0
435#endif
436#if defined(INTR0x60_CC_DEST_61)
437 .byte 1
438#else
439 .byte 0
440#endif
441#if defined(INTR0x60_CC_DEST_62)
442 .byte 1
443#else
444 .byte 0
445#endif
446#if defined(INTR0x60_CC_DEST_63)
447 .byte 1
448#else
449 .byte 0
450#endif
451
452.text
453#endif /* INTR0x60_CC_DEST_ALL */
454
455
456#ifdef INTR0x60_NIU_TX_IV_0
457/************************************************************************/
458/* Handle NIU TX interrupts */
459
460intr0x60_handle_niu_tx:
461 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_tx)) -> printf("INFO: NIU TX interrupt received",*,1)
462 /* Make sure that this thread is the right one for this NIU interrupt */
463#ifdef INTR0x60_NIU_TX_IV_0
464intr0x60_handle_niu_tx_check_thread_0:
465 cmp %g2, INTR0x60_NIU_TX_IV_0
466 bnz 1f
467#ifdef PORTABLE_CORE
468 and %g1, 0x7, %g7
469 cmp %g7, INTR0x60_NIU_TX_THREAD_0
470#else
471 cmp %g1, INTR0x60_NIU_TX_THREAD_0
472#endif
473 bnz intr0x60_handle_niu_tx_bad_thread
474 best_set_reg(INTR0x60_NIU_TX_DMA_0, %g7, %g3)
475 ba intr0x60_handle_niu_tx_good_thread
476 nop
4771:
478#endif /* INTR0x60_NIU_TX_IV_0 */
479
480#ifdef INTR0x60_NIU_TX_IV_1
481intr0x60_handle_niu_tx_check_thread_1:
482 cmp %g2, INTR0x60_NIU_TX_IV_1
483 bnz 1f
484#ifdef PORTABLE_CORE
485 and %g1, 0x7, %g7
486 cmp %g7, INTR0x60_NIU_TX_THREAD_1
487#else
488 cmp %g1, INTR0x60_NIU_TX_THREAD_1
489#endif
490 bnz intr0x60_handle_niu_tx_bad_thread
491 best_set_reg(INTR0x60_NIU_TX_DMA_1, %g7, %g3)
492 ba intr0x60_handle_niu_tx_good_thread
493 nop
4941:
495#endif /* INTR0x60_NIU_TX_IV_1 */
496
497#ifdef INTR0x60_NIU_TX_IV_2
498intr0x60_handle_niu_tx_check_thread_2:
499 cmp %g2, INTR0x60_NIU_TX_IV_2
500 bnz 1f
501#ifdef PORTABLE_CORE
502 and %g1, 0x7, %g7
503 cmp %g7, INTR0x60_NIU_TX_THREAD_2
504#else
505 cmp %g1, INTR0x60_NIU_TX_THREAD_2
506#endif
507 bnz intr0x60_handle_niu_tx_bad_thread
508 best_set_reg(INTR0x60_NIU_TX_DMA_2, %g7, %g3)
509 ba intr0x60_handle_niu_tx_good_thread
510 nop
5111:
512#endif /* INTR0x60_NIU_TX_IV_2 */
513
514#ifdef INTR0x60_NIU_TX_IV_3
515intr0x60_handle_niu_tx_check_thread_3:
516 cmp %g2, INTR0x60_NIU_TX_IV_3
517 bnz 1f
518#ifdef PORTABLE_CORE
519 and %g1, 0x7, %g7
520 cmp %g7, INTR0x60_NIU_TX_THREAD_3
521#else
522 cmp %g1, INTR0x60_NIU_TX_THREAD_3
523#endif
524 bnz intr0x60_handle_niu_tx_bad_thread
525 best_set_reg(INTR0x60_NIU_TX_DMA_3, %g7, %g3)
526 ba intr0x60_handle_niu_tx_good_thread
527 nop
5281:
529#endif /* INTR0x60_NIU_TX_IV_3 */
530
531#ifdef INTR0x60_NIU_TX_IV_4
532intr0x60_handle_niu_tx_check_thread_4:
533 cmp %g2, INTR0x60_NIU_TX_IV_4
534 bnz 1f
535#ifdef PORTABLE_CORE
536 and %g1, 0x7, %g7
537 cmp %g7, INTR0x60_NIU_TX_THREAD_4
538#else
539 cmp %g1, INTR0x60_NIU_TX_THREAD_4
540#endif
541 bnz intr0x60_handle_niu_tx_bad_thread
542 best_set_reg(INTR0x60_NIU_TX_DMA_4, %g7, %g3)
543 ba intr0x60_handle_niu_tx_good_thread
544 nop
5451:
546#endif /* INTR0x60_NIU_TX_IV_4 */
547
548#ifdef INTR0x60_NIU_TX_IV_5
549intr0x60_handle_niu_tx_check_thread_5:
550 cmp %g2, INTR0x60_NIU_TX_IV_5
551 bnz 1f
552#ifdef PORTABLE_CORE
553 and %g1, 0x7, %g7
554 cmp %g7, INTR0x60_NIU_TX_THREAD_5
555#else
556 cmp %g1, INTR0x60_NIU_TX_THREAD_5
557#endif
558 bnz intr0x60_handle_niu_tx_bad_thread
559 best_set_reg(INTR0x60_NIU_TX_DMA_5, %g7, %g3)
560 ba intr0x60_handle_niu_tx_good_thread
561 nop
5621:
563#endif /* INTR0x60_NIU_TX_IV_5 */
564
565#ifdef INTR0x60_NIU_TX_IV_6
566intr0x60_handle_niu_tx_check_thread_6:
567 cmp %g2, INTR0x60_NIU_TX_IV_6
568 bnz 1f
569#ifdef PORTABLE_CORE
570 and %g1, 0x7, %g7
571 cmp %g7, INTR0x60_NIU_TX_THREAD_6
572#else
573 cmp %g1, INTR0x60_NIU_TX_THREAD_6
574#endif
575 bnz intr0x60_handle_niu_tx_bad_thread
576 best_set_reg(INTR0x60_NIU_TX_DMA_6, %g7, %g3)
577 ba intr0x60_handle_niu_tx_good_thread
578 nop
5791:
580#endif /* INTR0x60_NIU_TX_IV_6 */
581
582#ifdef INTR0x60_NIU_TX_IV_7
583intr0x60_handle_niu_tx_check_thread_7:
584 cmp %g2, INTR0x60_NIU_TX_IV_7
585 bnz 1f
586#ifdef PORTABLE_CORE
587 and %g1, 0x7, %g7
588 cmp %g7, INTR0x60_NIU_TX_THREAD_7
589#else
590 cmp %g1, INTR0x60_NIU_TX_THREAD_7
591#endif
592 bnz intr0x60_handle_niu_tx_bad_thread
593 best_set_reg(INTR0x60_NIU_TX_DMA_7, %g7, %g3)
594 ba intr0x60_handle_niu_tx_good_thread
595 nop
5961:
597#endif /* INTR0x60_NIU_TX_IV_7 */
598
599#ifdef INTR0x60_NIU_TX_IV_8
600intr0x60_handle_niu_tx_check_thread_8:
601 cmp %g2, INTR0x60_NIU_TX_IV_8
602 bnz 1f
603#ifdef PORTABLE_CORE
604 and %g1, 0x7, %g7
605 cmp %g7, INTR0x60_NIU_TX_THREAD_8
606#else
607 cmp %g1, INTR0x60_NIU_TX_THREAD_8
608#endif
609 bnz intr0x60_handle_niu_tx_bad_thread
610 best_set_reg(INTR0x60_NIU_TX_DMA_8, %g7, %g3)
611 ba intr0x60_handle_niu_tx_good_thread
612 nop
6131:
614#endif /* INTR0x60_NIU_TX_IV_8 */
615
616#ifdef INTR0x60_NIU_TX_IV_9
617intr0x60_handle_niu_tx_check_thread_9:
618 cmp %g2, INTR0x60_NIU_TX_IV_9
619 bnz 1f
620#ifdef PORTABLE_CORE
621 and %g1, 0x7, %g7
622 cmp %g7, INTR0x60_NIU_TX_THREAD_9
623#else
624 cmp %g1, INTR0x60_NIU_TX_THREAD_9
625#endif
626 bnz intr0x60_handle_niu_tx_bad_thread
627 best_set_reg(INTR0x60_NIU_TX_DMA_9, %g7, %g3)
628 ba intr0x60_handle_niu_tx_good_thread
629 nop
6301:
631#endif /* INTR0x60_NIU_TX_IV_9 */
632
633#ifdef INTR0x60_NIU_TX_IV_10
634intr0x60_handle_niu_tx_check_thread_10:
635 cmp %g2, INTR0x60_NIU_TX_IV_10
636 bnz 1f
637#ifdef PORTABLE_CORE
638 and %g1, 0x7, %g7
639 cmp %g7, INTR0x60_NIU_TX_THREAD_10
640#else
641 cmp %g1, INTR0x60_NIU_TX_THREAD_10
642#endif
643 bnz intr0x60_handle_niu_tx_bad_thread
644 best_set_reg(INTR0x60_NIU_TX_DMA_10, %g7, %g3)
645 ba intr0x60_handle_niu_tx_good_thread
646 nop
6471:
648#endif /* INTR0x60_NIU_TX_IV_10 */
649
650#ifdef INTR0x60_NIU_TX_IV_11
651intr0x60_handle_niu_tx_check_thread_11:
652 cmp %g2, INTR0x60_NIU_TX_IV_11
653 bnz 1f
654#ifdef PORTABLE_CORE
655 and %g1, 0x7, %g7
656 cmp %g7, INTR0x60_NIU_TX_THREAD_11
657#else
658 cmp %g1, INTR0x60_NIU_TX_THREAD_11
659#endif
660 bnz intr0x60_handle_niu_tx_bad_thread
661 best_set_reg(INTR0x60_NIU_TX_DMA_11, %g7, %g3)
662 ba intr0x60_handle_niu_tx_good_thread
663 nop
6641:
665#endif /* INTR0x60_NIU_TX_IV_11 */
666
667#ifdef INTR0x60_NIU_TX_IV_12
668intr0x60_handle_niu_tx_check_thread_12:
669 cmp %g2, INTR0x60_NIU_TX_IV_12
670 bnz 1f
671#ifdef PORTABLE_CORE
672 and %g1, 0x7, %g7
673 cmp %g7, INTR0x60_NIU_TX_THREAD_12
674#else
675 cmp %g1, INTR0x60_NIU_TX_THREAD_12
676#endif
677 bnz intr0x60_handle_niu_tx_bad_thread
678 best_set_reg(INTR0x60_NIU_TX_DMA_12, %g7, %g3)
679 ba intr0x60_handle_niu_tx_good_thread
680 nop
6811:
682#endif /* INTR0x60_NIU_TX_IV_12 */
683
684#ifdef INTR0x60_NIU_TX_IV_13
685intr0x60_handle_niu_tx_check_thread_13:
686 cmp %g2, INTR0x60_NIU_TX_IV_13
687 bnz 1f
688#ifdef PORTABLE_CORE
689 and %g1, 0x7, %g7
690 cmp %g7, INTR0x60_NIU_TX_THREAD_13
691#else
692 cmp %g1, INTR0x60_NIU_TX_THREAD_13
693#endif
694 bnz intr0x60_handle_niu_tx_bad_thread
695 best_set_reg(INTR0x60_NIU_TX_DMA_13, %g7, %g3)
696 ba intr0x60_handle_niu_tx_good_thread
697 nop
6981:
699#endif /* INTR0x60_NIU_TX_IV_13 */
700
701#ifdef INTR0x60_NIU_TX_IV_14
702intr0x60_handle_niu_tx_check_thread_14:
703 cmp %g2, INTR0x60_NIU_TX_IV_14
704 bnz 1f
705#ifdef PORTABLE_CORE
706 and %g1, 0x7, %g7
707 cmp %g7, INTR0x60_NIU_TX_THREAD_14
708#else
709 cmp %g1, INTR0x60_NIU_TX_THREAD_14
710#endif
711 bnz intr0x60_handle_niu_tx_bad_thread
712 best_set_reg(INTR0x60_NIU_TX_DMA_14, %g7, %g3)
713 ba intr0x60_handle_niu_tx_good_thread
714 nop
7151:
716#endif /* INTR0x60_NIU_TX_IV_14 */
717
718#ifdef INTR0x60_NIU_TX_IV_15
719intr0x60_handle_niu_tx_check_thread_15:
720 cmp %g2, INTR0x60_NIU_TX_IV_15
721 bnz 1f
722#ifdef PORTABLE_CORE
723 and %g1, 0x7, %g7
724 cmp %g7, INTR0x60_NIU_TX_THREAD_15
725#else
726 cmp %g1, INTR0x60_NIU_TX_THREAD_15
727#endif
728 bnz intr0x60_handle_niu_tx_bad_thread
729 best_set_reg(INTR0x60_NIU_TX_DMA_15, %g7, %g3)
730 ba intr0x60_handle_niu_tx_good_thread
731 nop
7321:
733#endif /* INTR0x60_NIU_TX_IV_15 */
734
735
736 /* If we get here, we have an unknown vector */
737intr0x60_handle_niu_tx_bad_vector:
738 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_tx_bad_vector)) -> printf("interrupt0x60_handler.s ERROR: intr0x60_iv_to_ig said this is an NIU TX interrupt, but it is not defined in INTR0x60_NIU_TX_IV_x",*,1)
739 EXIT_BAD
740
741 /* If we get here, we know we have the right thread for this vector */
742intr0x60_handle_niu_tx_good_thread:
743 /* Clear the source of the interrupt */
744 ! Re-enable the interrupt in the transmit DMA channel
745 best_set_reg(TX_CS, %g7, %g4) ! TX_CS
746 best_set_reg(TDMC_STEP, %g7, %g5)
747 mulx %g5, %g3, %g5 ! %g3 is the DMA TX channel
748 add %g4, %g5, %g4
749 ldxa [%g4]ASI_PRIMARY_LITTLE, %g0 ! Reset MK
750
751 ! Re-enable the interrupt in the NIU
752 best_set_reg(LDGIMGN, %g7, %g4) ! LDGIMGN
753 best_set_reg(LDGIMGN_STEP, %g7, %g5)
754 mulx %g5, %g2, %g5
755 add %g4, %g5, %g4
756 best_set_reg(0x80000001, %g7, %g5)
757 stxa %g5, [%g4]ASI_PRIMARY_LITTLE
758 nop
759
760 /* Include any extra NIU handler from the user */
761 /* The code can assume that %g1 is the thread, %g2 is the vector,
762 * and %g3 is the TX DMA channel */
763#ifdef INTR0x60_NIU_TX_EXTRA_HANDLER
764intr0x60_handle_niu_tx_extra_handler:
765INTR0x60_NIU_TX_EXTRA_HANDLER
766#endif /* INTR0x60_NIU_TX_EXTRA_HANDLER */
767
768intr0x60_handle_niu_tx_retry:
769 /* Retry the instruction that was trapped */
770 retry
771
772intr0x60_handle_niu_tx_bad_thread:
773 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_tx_bad_thread)) -> printf("ERROR: NIU TX interrupt received on unexpected thread",*,1)
774 EXIT_BAD
775#endif /* INTR0x60_NIU_TX_IV_0 */
776
777
778#ifdef INTR0x60_NIU_RX_IV_0
779/************************************************************************/
780/* Handle NIU RX interrupts */
781
782intr0x60_handle_niu_rx:
783 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx)) -> printf("INFO: NIU RX interrupt received",*,1)
784 /* Make sure that this thread is the right one for this NIU interrupt */
785#ifdef INTR0x60_NIU_RX_IV_0
786intr0x60_handle_niu_rx_check_thread_0:
787 cmp %g2, INTR0x60_NIU_RX_IV_0
788 bnz 1f
789#ifdef PORTABLE_CORE
790 and %g1, 0x7, %g7
791 cmp %g7, INTR0x60_NIU_RX_THREAD_0
792#else
793 cmp %g1, INTR0x60_NIU_RX_THREAD_0
794#endif
795 bnz intr0x60_handle_niu_rx_bad_thread
796 best_set_reg(INTR0x60_NIU_RX_DMA_0, %g7, %g3)
797 ba intr0x60_handle_niu_rx_good_thread
798 nop
7991:
800#endif /* INTR0x60_NIU_RX_IV_0 */
801
802#ifdef INTR0x60_NIU_RX_IV_1
803intr0x60_handle_niu_rx_check_thread_1:
804 cmp %g2, INTR0x60_NIU_RX_IV_1
805 bnz 1f
806#ifdef PORTABLE_CORE
807 and %g1, 0x7, %g7
808 cmp %g7, INTR0x60_NIU_RX_THREAD_1
809#else
810 cmp %g1, INTR0x60_NIU_RX_THREAD_1
811#endif
812 bnz intr0x60_handle_niu_rx_bad_thread
813 best_set_reg(INTR0x60_NIU_RX_DMA_1, %g7, %g3)
814 ba intr0x60_handle_niu_rx_good_thread
815 nop
8161:
817#endif /* INTR0x60_NIU_RX_IV_1 */
818
819#ifdef INTR0x60_NIU_RX_IV_2
820intr0x60_handle_niu_rx_check_thread_2:
821 cmp %g2, INTR0x60_NIU_RX_IV_2
822 bnz 1f
823#ifdef PORTABLE_CORE
824 and %g1, 0x7, %g7
825 cmp %g7, INTR0x60_NIU_RX_THREAD_2
826#else
827 cmp %g1, INTR0x60_NIU_RX_THREAD_2
828#endif
829 bnz intr0x60_handle_niu_rx_bad_thread
830 best_set_reg(INTR0x60_NIU_RX_DMA_2, %g7, %g3)
831 ba intr0x60_handle_niu_rx_good_thread
832 nop
8331:
834#endif /* INTR0x60_NIU_RX_IV_2 */
835
836#ifdef INTR0x60_NIU_RX_IV_3
837intr0x60_handle_niu_rx_check_thread_3:
838 cmp %g2, INTR0x60_NIU_RX_IV_3
839 bnz 1f
840#ifdef PORTABLE_CORE
841 and %g1, 0x7, %g7
842 cmp %g7, INTR0x60_NIU_RX_THREAD_3
843#else
844 cmp %g1, INTR0x60_NIU_RX_THREAD_3
845#endif
846 bnz intr0x60_handle_niu_rx_bad_thread
847 best_set_reg(INTR0x60_NIU_RX_DMA_3, %g7, %g3)
848 ba intr0x60_handle_niu_rx_good_thread
849 nop
8501:
851#endif /* INTR0x60_NIU_RX_IV_3 */
852
853#ifdef INTR0x60_NIU_RX_IV_4
854intr0x60_handle_niu_rx_check_thread_4:
855 cmp %g2, INTR0x60_NIU_RX_IV_4
856 bnz 1f
857#ifdef PORTABLE_CORE
858 and %g1, 0x7, %g7
859 cmp %g7, INTR0x60_NIU_RX_THREAD_4
860#else
861 cmp %g1, INTR0x60_NIU_RX_THREAD_4
862#endif
863 bnz intr0x60_handle_niu_rx_bad_thread
864 best_set_reg(INTR0x60_NIU_RX_DMA_4, %g7, %g3)
865 ba intr0x60_handle_niu_rx_good_thread
866 nop
8671:
868#endif /* INTR0x60_NIU_RX_IV_4 */
869
870#ifdef INTR0x60_NIU_RX_IV_5
871intr0x60_handle_niu_rx_check_thread_5:
872 cmp %g2, INTR0x60_NIU_RX_IV_5
873 bnz 1f
874#ifdef PORTABLE_CORE
875 and %g1, 0x7, %g7
876 cmp %g7, INTR0x60_NIU_RX_THREAD_5
877#else
878 cmp %g1, INTR0x60_NIU_RX_THREAD_5
879#endif
880 bnz intr0x60_handle_niu_rx_bad_thread
881 best_set_reg(INTR0x60_NIU_RX_DMA_5, %g7, %g3)
882 ba intr0x60_handle_niu_rx_good_thread
883 nop
8841:
885#endif /* INTR0x60_NIU_RX_IV_5 */
886
887#ifdef INTR0x60_NIU_RX_IV_6
888intr0x60_handle_niu_rx_check_thread_6:
889 cmp %g2, INTR0x60_NIU_RX_IV_6
890 bnz 1f
891#ifdef PORTABLE_CORE
892 and %g1, 0x7, %g7
893 cmp %g7, INTR0x60_NIU_RX_THREAD_6
894#else
895 cmp %g1, INTR0x60_NIU_RX_THREAD_6
896#endif
897 bnz intr0x60_handle_niu_rx_bad_thread
898 best_set_reg(INTR0x60_NIU_RX_DMA_6, %g7, %g3)
899 ba intr0x60_handle_niu_rx_good_thread
900 nop
9011:
902#endif /* INTR0x60_NIU_RX_IV_6 */
903
904#ifdef INTR0x60_NIU_RX_IV_7
905intr0x60_handle_niu_rx_check_thread_7:
906 cmp %g2, INTR0x60_NIU_RX_IV_7
907 bnz 1f
908#ifdef PORTABLE_CORE
909 and %g1, 0x7, %g7
910 cmp %g7, INTR0x60_NIU_RX_THREAD_7
911#else
912 cmp %g1, INTR0x60_NIU_RX_THREAD_7
913#endif
914 bnz intr0x60_handle_niu_rx_bad_thread
915 best_set_reg(INTR0x60_NIU_RX_DMA_7, %g7, %g3)
916 ba intr0x60_handle_niu_rx_good_thread
917 nop
9181:
919#endif /* INTR0x60_NIU_RX_IV_7 */
920
921#ifdef INTR0x60_NIU_RX_IV_8
922intr0x60_handle_niu_rx_check_thread_8:
923 cmp %g2, INTR0x60_NIU_RX_IV_8
924 bnz 1f
925#ifdef PORTABLE_CORE
926 and %g1, 0x7, %g7
927 cmp %g7, INTR0x60_NIU_RX_THREAD_8
928#else
929 cmp %g1, INTR0x60_NIU_RX_THREAD_8
930#endif
931 bnz intr0x60_handle_niu_rx_bad_thread
932 best_set_reg(INTR0x60_NIU_RX_DMA_8, %g7, %g3)
933 ba intr0x60_handle_niu_rx_good_thread
934 nop
9351:
936#endif /* INTR0x60_NIU_RX_IV_8 */
937
938#ifdef INTR0x60_NIU_RX_IV_9
939intr0x60_handle_niu_rx_check_thread_9:
940 cmp %g2, INTR0x60_NIU_RX_IV_9
941 bnz 1f
942#ifdef PORTABLE_CORE
943 and %g1, 0x7, %g7
944 cmp %g7, INTR0x60_NIU_RX_THREAD_9
945#else
946 cmp %g1, INTR0x60_NIU_RX_THREAD_9
947#endif
948 bnz intr0x60_handle_niu_rx_bad_thread
949 best_set_reg(INTR0x60_NIU_RX_DMA_9, %g7, %g3)
950 ba intr0x60_handle_niu_rx_good_thread
951 nop
9521:
953#endif /* INTR0x60_NIU_RX_IV_9 */
954
955#ifdef INTR0x60_NIU_RX_IV_10
956intr0x60_handle_niu_rx_check_thread_10:
957 cmp %g2, INTR0x60_NIU_RX_IV_10
958 bnz 1f
959#ifdef PORTABLE_CORE
960 and %g1, 0x7, %g7
961 cmp %g7, INTR0x60_NIU_RX_THREAD_10
962#else
963 cmp %g1, INTR0x60_NIU_RX_THREAD_10
964#endif
965 bnz intr0x60_handle_niu_rx_bad_thread
966 best_set_reg(INTR0x60_NIU_RX_DMA_10, %g7, %g3)
967 ba intr0x60_handle_niu_rx_good_thread
968 nop
9691:
970#endif /* INTR0x60_NIU_RX_IV_10 */
971
972#ifdef INTR0x60_NIU_RX_IV_11
973intr0x60_handle_niu_rx_check_thread_11:
974 cmp %g2, INTR0x60_NIU_RX_IV_11
975 bnz 1f
976#ifdef PORTABLE_CORE
977 and %g1, 0x7, %g7
978 cmp %g7, INTR0x60_NIU_RX_THREAD_11
979#else
980 cmp %g1, INTR0x60_NIU_RX_THREAD_11
981#endif
982 bnz intr0x60_handle_niu_rx_bad_thread
983 best_set_reg(INTR0x60_NIU_RX_DMA_11, %g7, %g3)
984 ba intr0x60_handle_niu_rx_good_thread
985 nop
9861:
987#endif /* INTR0x60_NIU_RX_IV_11 */
988
989#ifdef INTR0x60_NIU_RX_IV_12
990intr0x60_handle_niu_rx_check_thread_12:
991 cmp %g2, INTR0x60_NIU_RX_IV_12
992 bnz 1f
993#ifdef PORTABLE_CORE
994 and %g1, 0x7, %g7
995 cmp %g7, INTR0x60_NIU_RX_THREAD_12
996#else
997 cmp %g1, INTR0x60_NIU_RX_THREAD_12
998#endif
999 bnz intr0x60_handle_niu_rx_bad_thread
1000 best_set_reg(INTR0x60_NIU_RX_DMA_12, %g7, %g3)
1001 ba intr0x60_handle_niu_rx_good_thread
1002 nop
10031:
1004#endif /* INTR0x60_NIU_RX_IV_12 */
1005
1006#ifdef INTR0x60_NIU_RX_IV_13
1007intr0x60_handle_niu_rx_check_thread_13:
1008 cmp %g2, INTR0x60_NIU_RX_IV_13
1009 bnz 1f
1010#ifdef PORTABLE_CORE
1011 and %g1, 0x7, %g7
1012 cmp %g7, INTR0x60_NIU_RX_THREAD_13
1013#else
1014 cmp %g1, INTR0x60_NIU_RX_THREAD_13
1015#endif
1016 bnz intr0x60_handle_niu_rx_bad_thread
1017 best_set_reg(INTR0x60_NIU_RX_DMA_13, %g7, %g3)
1018 ba intr0x60_handle_niu_rx_good_thread
1019 nop
10201:
1021#endif /* INTR0x60_NIU_RX_IV_13 */
1022
1023#ifdef INTR0x60_NIU_RX_IV_14
1024intr0x60_handle_niu_rx_check_thread_14:
1025 cmp %g2, INTR0x60_NIU_RX_IV_14
1026 bnz 1f
1027#ifdef PORTABLE_CORE
1028 and %g1, 0x7, %g7
1029 cmp %g7, INTR0x60_NIU_RX_THREAD_14
1030#else
1031 cmp %g1, INTR0x60_NIU_RX_THREAD_14
1032#endif
1033 bnz intr0x60_handle_niu_rx_bad_thread
1034 best_set_reg(INTR0x60_NIU_RX_DMA_14, %g7, %g3)
1035 ba intr0x60_handle_niu_rx_good_thread
1036 nop
10371:
1038#endif /* INTR0x60_NIU_RX_IV_14 */
1039
1040#ifdef INTR0x60_NIU_RX_IV_15
1041intr0x60_handle_niu_rx_check_thread_15:
1042 cmp %g2, INTR0x60_NIU_RX_IV_15
1043 bnz 1f
1044#ifdef PORTABLE_CORE
1045 and %g1, 0x7, %g7
1046 cmp %g7, INTR0x60_NIU_RX_THREAD_15
1047#else
1048 cmp %g1, INTR0x60_NIU_RX_THREAD_15
1049#endif
1050 bnz intr0x60_handle_niu_rx_bad_thread
1051 best_set_reg(INTR0x60_NIU_RX_DMA_15, %g7, %g3)
1052 ba intr0x60_handle_niu_rx_good_thread
1053 nop
10541:
1055#endif /* INTR0x60_NIU_RX_IV_15 */
1056
1057
1058 /* If we get here, we have an unknown vector */
1059intr0x60_handle_niu_rx_bad_vector:
1060 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx_bad_vector)) -> printf("interrupt0x60_handler.s ERROR: intr0x60_iv_to_ig said this is an NIU RX interrupt, but it is not defined in INTR0x60_NIU_RX_IV_x",*,1)
1061 EXIT_BAD
1062
1063 /* If we get here, we know we have the right thread for this vector */
1064intr0x60_handle_niu_rx_good_thread:
1065 /* Clear the source of the interrupt */
1066 best_set_reg(RX_DMA_CTL_STAT, %g7, %g4)
1067 mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
1068 add %g4, %g7, %g4 ! Addr of RX DMA Ctl/stat for this channel
1069intr0x60_handle_niu_rx_get_rx_dma_ctl_stat:
1070 ldxa [%g4]ASI_PRIMARY_LITTLE, %g5 ! Get status
1071 mov 0x7, %g7
1072 sllx %g7, 32, %g7 ! Mask for clear-on-reset error bits
1073 and %g5, %g7, %g7
1074 brz %g7, intr0x60_handle_niu_rx_nonfatal
1075 nop
1076
1077intr0x60_handle_niu_rx_fatal_error:
1078#ifdef INTR0x60_NIU_RX_FATAL_HANDLER
1079INTR0x60_NIU_RX_FATAL_HANDLER
1080#else /* INTR0x60_NIU_RX_FATAL_HANDLER */
1081#ifdef INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL
1082/* This code does what is needed for tsotool NIU RX fatal error interrupts */
1083 best_set_reg(RXDMA_CFIG1, %g7, %g4)
1084 mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
1085 add %g4, %g7, %g4
1086intr0x60_handle_niu_rx_fatal_error_disable_dma_channel:
1087 stxa %g0, [%g4]ASI_PRIMARY_LITTLE
1088 membar #Sync
1089 mov 1, %g7
1090 sllx %g7, 30, %g7 ! RST bit in RXDMA_CFIG1
1091intr0x60_handle_niu_rx_fatal_error_reset_dma_channel:
1092 stxa %g7, [%g4]ASI_PRIMARY_LITTLE
1093 srlx %g7, 1, %g7 ! QST bit in RXDMA_CFIG1
1094 mov 10, %g6 ! Timeout
1095intr0x60_handle_niu_rx_fatal_error_wait_for_dma_channel:
1096 ldxa [%g4]ASI_PRIMARY_LITTLE, %g5 ! Get the status
1097 cmp %g5, %g7
1098 beq intr0x60_handle_niu_rx_fatal_error_enable_intr_for_dma_channel
1099 dec %g6
1100 brnz %g6, intr0x60_handle_niu_rx_fatal_error_wait_for_dma_channel
1101 nop
1102intr0x60_handle_niu_rx_fatal_error_timeout_wait_for_dma_channel:
1103 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx_fatal_error_timeout_wait_for_dma_channel)) -> printf("ERROR: NIU RX interrupt received for fatal error and DMA channel reset never completed",*,1)
1104 EXIT_BAD
1105intr0x60_handle_niu_rx_fatal_error_enable_intr_for_dma_channel:
1106 best_set_reg(RX_DMA_ENT_MSK, %g7, %g5)
1107 mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
1108 add %g5, %g7, %g5
1109 stxa %g0, [%g5]ASI_PRIMARY_LITTLE
1110 ba intr0x60_handle_niu_rx_reenable_ldg
1111 membar #Sync
1112#else /* INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL */
1113 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx_fatal_error)) -> printf("ERROR: NIU RX interrupt received for fatal error",*,1)
1114 EXIT_BAD
1115#endif /* INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL */
1116#endif /* INTR0x60_NIU_RX_FATAL_HANDLER */
1117
1118intr0x60_handle_niu_rx_nonfatal:
1119 best_set_reg(0xffffffffffff0000, %g7, %g6)
1120 and %g5, %g6, %g5 ! Only preserve error bits, for RW1C
1121 best_set_reg(RCR_STAT_A, %g7, %g6)
1122 mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
1123 add %g6, %g7, %g6
1124intr0x60_handle_niu_rx_get_rcr_stat_a:
1125 ldxa [%g6]ASI_PRIMARY_LITTLE, %g6 ! Get the number of pkts received
1126 or %g6, %g5, %g6
1127 best_set_reg(THRES_INT, %g7, %g5) ! Bit to enable mailbox (MEX in PRM)
1128 or %g6, %g5, %g6
1129intr0x60_handle_niu_rx_reset_rx_dma_ctl_stat:
1130 stxa %g6, [%g4]ASI_PRIMARY_LITTLE ! RW1C on RCRTHRES, RCRTO, etc., plus
1131 ! set MEX, decrement QLEN by pkt read
1132intr0x60_handle_niu_rx_reenable_ldg:
1133 ! Re-enable the interrupt in the NIU LDG
1134 best_set_reg(LDGIMGN, %g7, %g4) ! LDGIMGN
1135 best_set_reg(LDGIMGN_STEP, %g7, %g5)
1136 mulx %g5, %g2, %g5
1137 add %g4, %g5, %g4
1138 best_set_reg(0x80000001, %g7, %g5)
1139 stxa %g5, [%g4]ASI_PRIMARY_LITTLE ! Arm LDGI, set timer to 1
1140 nop
1141
1142 /* Include any extra NIU handler from the user */
1143 /* The code can assume that %g1 is the thread, %g2 is the vector,
1144 * and %g3 is the RX DMA channel */
1145#ifdef INTR0x60_NIU_RX_EXTRA_HANDLER
1146intr0x60_handle_niu_rx_extra_handler:
1147INTR0x60_NIU_RX_EXTRA_HANDLER
1148#endif /* INTR0x60_NIU_RX_EXTRA_HANDLER */
1149
1150intr0x60_handle_niu_rx_retry:
1151 /* Retry the instruction that was trapped */
1152 retry
1153
1154intr0x60_handle_niu_rx_bad_thread:
1155 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx_bad_thread)) -> printf("ERROR: NIU RX interrupt received on unexpected thread",*,1)
1156 EXIT_BAD
1157#endif /* INTR0x60_NIU_RX_IV_0 */
1158
1159
1160#ifdef INTR0x60_MONDO_IV
1161/************************************************************************/
1162/* Handle PIU interrupts */
1163
1164intr0x60_handle_piu:
1165 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu)) -> printf("INFO: PIU interrupt received",*,1)
1166#ifndef INTR0x60_DO_NOT_READ_ADATA1
1167 /* To reach coverage goals, do a dummy read from ADATA1 */
1168 best_set_reg(MONDO_INT_ADATA1, %g4, %g3)
1169 ldx [%g3], %g3
1170#endif /* INTR0x60_DO_NOT_READ_ADATA1 */
1171 best_set_reg(MONDO_INT_ADATA0, %g4, %g3)
1172 ldx [%g3], %g3
1173 and %g3, 0x3f, %g3 /* WIP: Mask to get INO */
1174#if INTR0x60_MONDO_20_V
1175 cmp %g3, 20
1176 be intr0x60_handle_piu_inta
1177 nop
1178#endif /* INTR0x60_MONDO_20_V */
1179#if INTR0x60_MONDO_21_V
1180 cmp %g3, 21
1181 be intr0x60_handle_piu_intb
1182 nop
1183#endif /* INTR0x60_MONDO_21_V */
1184#if INTR0x60_MONDO_22_V
1185 cmp %g3, 22
1186 be intr0x60_handle_piu_intc
1187 nop
1188#endif /* INTR0x60_MONDO_22_V */
1189#if INTR0x60_MONDO_23_V
1190 cmp %g3, 23
1191 be intr0x60_handle_piu_intd
1192 nop
1193#endif /* INTR0x60_MONDO_23_V */
1194#ifdef INTR0x60_MSI_0_NUM
1195intr0x60_handle_piu_check_msi_0:
1196 cmp %g3, mpeval(INTR0x60_MSI_0_EQN+24)
1197 be intr0x60_handle_piu_msi_0
1198 mov 0, %g4
1199#endif /* INTR0x60_MSI_0_NUM */
1200#ifdef INTR0x60_MSI_1_NUM
1201intr0x60_handle_piu_check_msi_1:
1202 cmp %g3, mpeval(INTR0x60_MSI_1_EQN+24)
1203 be intr0x60_handle_piu_msi_1
1204 mov 1, %g4
1205#endif /* INTR0x60_MSI_1_NUM */
1206#ifdef INTR0x60_MSI_2_NUM
1207intr0x60_handle_piu_check_msi_2:
1208 cmp %g3, mpeval(INTR0x60_MSI_2_EQN+24)
1209 be intr0x60_handle_piu_msi_2
1210 mov 2, %g4
1211#endif /* INTR0x60_MSI_2_NUM */
1212#ifdef INTR0x60_MSI_3_NUM
1213intr0x60_handle_piu_check_msi_3:
1214 cmp %g3, mpeval(INTR0x60_MSI_3_EQN+24)
1215 be intr0x60_handle_piu_msi_3
1216 mov 3, %g4
1217#endif /* INTR0x60_MSI_3_NUM */
1218#ifdef INTR0x60_MSI_4_NUM
1219intr0x60_handle_piu_check_msi_4:
1220 cmp %g3, mpeval(INTR0x60_MSI_4_EQN+24)
1221 be intr0x60_handle_piu_msi_4
1222 mov 4, %g4
1223#endif /* INTR0x60_MSI_4_NUM */
1224#ifdef INTR0x60_MSI_5_NUM
1225intr0x60_handle_piu_check_msi_5:
1226 cmp %g3, mpeval(INTR0x60_MSI_5_EQN+24)
1227 be intr0x60_handle_piu_msi_5
1228 mov 5, %g4
1229#endif /* INTR0x60_MSI_5_NUM */
1230#ifdef INTR0x60_MSI_6_NUM
1231intr0x60_handle_piu_check_msi_6:
1232 cmp %g3, mpeval(INTR0x60_MSI_6_EQN+24)
1233 be intr0x60_handle_piu_msi_6
1234 mov 6, %g4
1235#endif /* INTR0x60_MSI_6_NUM */
1236#ifdef INTR0x60_MSI_7_NUM
1237intr0x60_handle_piu_check_msi_7:
1238 cmp %g3, mpeval(INTR0x60_MSI_7_EQN+24)
1239 be intr0x60_handle_piu_msi_7
1240 mov 7, %g4
1241#endif /* INTR0x60_MSI_7_NUM */
1242#ifdef INTR0x60_PM_PME_EQN
1243intr0x60_handle_piu_check_pm_pme:
1244 cmp %g3, mpeval(INTR0x60_PM_PME_EQN+24)
1245 be intr0x60_handle_piu_pm_pme
1246 nop
1247#endif /* INTR0x60_PM_PME_EQN */
1248#ifdef INTR0x60_PME_TO_ACK_EQN
1249intr0x60_handle_piu_check_pme_to_ack:
1250 cmp %g3, mpeval(INTR0x60_PME_TO_ACK_EQN+24)
1251 be intr0x60_handle_piu_pme_to_ack
1252 nop
1253#endif /* INTR0x60_PME_TO_ACK_EQN */
1254
1255 /* If we get here, we got an unexpected INO */
1256intr0x60_bad_mondo_INO:
1257 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_bad_mondo_INO)) -> printf("ERROR: Bad mondo INO",*,1)
1258 EXIT_BAD
1259
1260#if INTR0x60_MONDO_20_V
1261 /************ Handle INTA ***********/
1262intr0x60_handle_piu_inta:
1263 /* Check whether this thread matches this INO */
1264#ifdef PORTABLE_CORE
1265 and %g1, 0x7, %g7
1266 cmp %g7/*tid*/, INTR0x60_MONDO_20_THREAD
1267#else
1268 cmp %g1/*tid*/, INTR0x60_MONDO_20_THREAD
1269#endif
1270 bne intr0x60_handle_piu_bad_thread
1271 nop
1272 /* Clear the interrupt */
1273intr0x60_handle_piu_inta_deassert:
1274#ifdef FC_NO_PEU_VERA
1275#ifdef USE_BOBO
1276 ! Offset accesses by PCIE_MEM64_OFFSET since
1277 ! BAR is set that way. Physical addresses generated via TSB
1278 ! have this offset so mimic that when accessing directly, as here.
1279 best_set_reg(mpeval(N2_PCIE_BASE_ADDR
1280 + MEM64_OFFSET_BASE_REG_DATA
1281 + PCIE_MEM64_OFFSET
1282 + BOBO_INTR_VECT_STATUS_OFFSET), %g7, %g4)
1283 ! Interrupt type
1284 mov eval(1 << 0), %g5
1285#else /* USE_BOBO */
1286 ! Offset accesses by PCIE_MEM64_OFFSET since
1287 ! BAR is set that way. Physical addresses generated via TSB
1288 ! have this offset so mimic that when accessing directly, as here.
1289 best_set_reg(mpeval(N2_PCIE_BASE_ADDR
1290 + MEM64_OFFSET_BASE_REG_DATA
1291 + PCIE_MEM64_OFFSET
1292 + (INTR0x60_MONDO_20_DMAEPT_ENGINE << 8)
1293 + DMAEPT_INTERRUPT_ACK), %g7, %g4)
1294 ! Interrupt type
1295 best_set_reg(DMAEPT_INTERRUPT_ACK_INTA, %g7, %g5)
1296#endif /* USE_BOBO */
1297 stwa %g5, [%g4] ASI_NL
1298#else /* FC_NO_PEU_VERA */
1299 ! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_inta_deassert)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT", 1, *, 1 )
1300#endif /* FC_NO_PEU_VERA */
1301
1302 /* Loop on the INTX Status Register until the deassert message
1303 * has arrived and been processed. */
1304 best_set_reg(PCI_E_INTX_STATUS_ADDR, %g5, %g4)
1305 best_set_reg(INTR0x60_INTX_DEASSERT_TIMEOUT, %g5, %g6)
1306intr0x60_handle_piu_inta_deassert_loop:
1307 brz %g6, intr0x60_handle_piu_inta_deassert_timeout
1308 dec %g6
1309 ldx [%g4], %g3
1310 and %g3, 8, %g3 ! 8 == bit for INTA
1311 brnz %g3, intr0x60_handle_piu_inta_deassert_loop
1312 set 1, %g3
1313intr0x60_handle_piu_inta_clear:
1314 best_set_reg(PCI_E_INT_A_CLEAR_ADDR, %g5, %g4)
1315 stx %g3, [%g4]
1316 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+0*PCI_E_INT_CLEAR_STEP), %g5, %g4)
1317 stx %g0, [%g4]
1318 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
1319 stx %g0, [%g4]
1320
1321 /* Include any extra INTA handler from the user */
1322 /* The code can assume that %g1 is the thread and %g2 is the vector */
1323#ifdef INTR0x60_INTA_EXTRA_HANDLER
1324intr0x60_handle_inta_extra_handler:
1325INTR0x60_INTA_EXTRA_HANDLER
1326#endif /* INTR0x60_INTA_EXTRA_HANDLER */
1327
1328intr0x60_handle_piu_inta_retry:
1329 /* Retry the instruction that was trapped */
1330 retry
1331#endif /* INTR0x60_MONDO_20_V */
1332
1333 /* If we get here, the interrupt status bit didn't deassert */
1334intr0x60_handle_piu_inta_deassert_timeout:
1335 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_inta_deassert_timeout)) -> printf("ERROR: INTA status bit did not deassert within INTR0x60_INTX_DEASSERT_TIMEOUT iterations",*,1)
1336 EXIT_BAD
1337
1338
1339#if INTR0x60_MONDO_21_V
1340 /************ Handle INTB ***********/
1341intr0x60_handle_piu_intb:
1342 /* Check whether this thread matches this INO */
1343#ifdef PORTABLE_CORE
1344 and %g1, 0x7, %g7
1345 cmp %g7/*tid*/, INTR0x60_MONDO_21_THREAD
1346#else
1347 cmp %g1/*tid*/, INTR0x60_MONDO_21_THREAD
1348#endif
1349 bne intr0x60_handle_piu_bad_thread
1350 nop
1351 /* Clear the interrupt */
1352intr0x60_handle_piu_intb_deassert:
1353#ifdef FC_NO_PEU_VERA
1354#ifdef USE_BOBO
1355 ! Offset accesses by PCIE_MEM64_OFFSET since
1356 ! BAR is set that way. Physical addresses generated via TSB
1357 ! have this offset so mimic that when accessing directly, as here.
1358 best_set_reg(mpeval(N2_PCIE_BASE_ADDR
1359 + MEM64_OFFSET_BASE_REG_DATA
1360 + PCIE_MEM64_OFFSET
1361 + BOBO_INTR_VECT_STATUS_OFFSET), %g7, %g4)
1362 ! Interrupt type
1363 mov eval(1 << 1), %g5
1364#else /* USE_BOBO */
1365 ! Offset accesses by PCIE_MEM64_OFFSET since
1366 ! BAR is set that way. Physical addresses generated via TSB
1367 ! have this offset so mimic that when accessing directly, as here.
1368 best_set_reg(mpeval(N2_PCIE_BASE_ADDR
1369 + MEM64_OFFSET_BASE_REG_DATA
1370 + PCIE_MEM64_OFFSET
1371 + (INTR0x60_MONDO_21_DMAEPT_ENGINE << 8)
1372 + DMAEPT_INTERRUPT_ACK), %g7, %g4)
1373 ! Interrupt type
1374 best_set_reg(DMAEPT_INTERRUPT_ACK_INTB, %g7, %g5)
1375#endif /* USE_BOBO */
1376 stwa %g5, [%g4] ASI_NL
1377#else /* FC_NO_PEU_VERA */
1378 ! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intb_deassert)) -> EnablePCIeIgCmd ("INTB", 0, 0, "DEASSERT", 1, *, 1 )
1379#endif /* FC_NO_PEU_VERA */
1380
1381 /* Loop on the INTX Status Register until the deassert message
1382 * has arrived and been processed. */
1383 best_set_reg(PCI_E_INTX_STATUS_ADDR, %g5, %g4)
1384 best_set_reg(INTR0x60_INTX_DEASSERT_TIMEOUT, %g5, %g6)
1385intr0x60_handle_piu_intb_deassert_loop:
1386 brz %g6, intr0x60_handle_piu_intb_deassert_timeout
1387 dec %g6
1388 ldx [%g4], %g3
1389 and %g3, 4, %g3 ! 4 == bit for INTB
1390 brnz %g3, intr0x60_handle_piu_intb_deassert_loop
1391 set 1, %g3
1392intr0x60_handle_piu_intb_clear:
1393 best_set_reg(PCI_E_INT_B_CLEAR_ADDR, %g5, %g4)
1394 stx %g3, [%g4]
1395 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+1*PCI_E_INT_CLEAR_STEP), %g5, %g4)
1396 stx %g0, [%g4]
1397 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
1398 stx %g0, [%g4]
1399
1400 /* Include any extra INTB handler from the user */
1401 /* The code can assume that %g1 is the thread and %g2 is the vector */
1402#ifdef INTR0x60_INTB_EXTRA_HANDLER
1403intr0x60_handle_intb_extra_handler:
1404INTR0x60_INTB_EXTRA_HANDLER
1405#endif /* INTR0x60_INTB_EXTRA_HANDLER */
1406
1407intr0x60_handle_piu_intb_retry:
1408 /* Retry the instruction that was trapped */
1409 retry
1410#endif /* INTR0x60_MONDO_21_V */
1411
1412 /* If we get here, the interrupt status bit didn't deassert */
1413intr0x60_handle_piu_intb_deassert_timeout:
1414 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intb_deassert_timeout)) -> printf("ERROR: INTB status bit did not deassert within INTR0x60_INTX_DEASSERT_TIMEOUT iterations",*,1)
1415 EXIT_BAD
1416
1417
1418#if INTR0x60_MONDO_22_V
1419 /************ Handle INTC ***********/
1420intr0x60_handle_piu_intc:
1421 /* Check whether this thread matches this INO */
1422#ifdef PORTABLE_CORE
1423 and %g1, 0x7, %g7
1424 cmp %g7/*tid*/, INTR0x60_MONDO_22_THREAD
1425#else
1426 cmp %g1/*tid*/, INTR0x60_MONDO_22_THREAD
1427#endif
1428 bne intr0x60_handle_piu_bad_thread
1429 nop
1430 /* Clear the interrupt */
1431intr0x60_handle_piu_intc_deassert:
1432#ifdef FC_NO_PEU_VERA
1433#ifdef USE_BOBO
1434 ! Offset accesses by PCIE_MEM64_OFFSET since
1435 ! BAR is set that way. Physical addresses generated via TSB
1436 ! have this offset so mimic that when accessing directly, as here.
1437 best_set_reg(mpeval(N2_PCIE_BASE_ADDR
1438 + MEM64_OFFSET_BASE_REG_DATA
1439 + PCIE_MEM64_OFFSET
1440 + BOBO_INTR_VECT_STATUS_OFFSET), %g7, %g4)
1441 ! Interrupt type
1442 mov eval(1 << 2), %g5
1443#else /* USE_BOBO */
1444 ! Offset accesses by PCIE_MEM64_OFFSET since
1445 ! BAR is set that way. Physical addresses generated via TSB
1446 ! have this offset so mimic that when accessing directly, as here.
1447 best_set_reg(mpeval(N2_PCIE_BASE_ADDR
1448 + MEM64_OFFSET_BASE_REG_DATA
1449 + PCIE_MEM64_OFFSET
1450 + (INTR0x60_MONDO_22_DMAEPT_ENGINE << 8)
1451 + DMAEPT_INTERRUPT_ACK), %g7, %g4)
1452 ! Interrupt type
1453 best_set_reg(DMAEPT_INTERRUPT_ACK_INTC, %g7, %g5)
1454#endif /* USE_BOBO */
1455 stwa %g5, [%g4] ASI_NL
1456#else /* FC_NO_PEU_VERA */
1457 ! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intc_deassert)) -> EnablePCIeIgCmd ("INTC", 0, 0, "DEASSERT", 1, *, 1 )
1458#endif /* FC_NO_PEU_VERA */
1459
1460 /* Loop on the INTX Status Register until the deassert message
1461 * has arrived and been processed. */
1462 best_set_reg(PCI_E_INTX_STATUS_ADDR, %g5, %g4)
1463 best_set_reg(INTR0x60_INTX_DEASSERT_TIMEOUT, %g5, %g6)
1464intr0x60_handle_piu_intc_deassert_loop:
1465 brz %g6, intr0x60_handle_piu_intc_deassert_timeout
1466 dec %g6
1467 ldx [%g4], %g3
1468 and %g3, 2, %g3 ! 2 == bit for INTC
1469 brnz %g3, intr0x60_handle_piu_intc_deassert_loop
1470 set 1, %g3
1471intr0x60_handle_piu_intc_clear:
1472 best_set_reg(PCI_E_INT_C_CLEAR_ADDR, %g5, %g4)
1473 stx %g3, [%g4]
1474 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+2*PCI_E_INT_CLEAR_STEP), %g5, %g4)
1475 stx %g0, [%g4]
1476 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
1477 stx %g0, [%g4]
1478
1479 /* Include any extra INTC handler from the user */
1480 /* The code can assume that %g1 is the thread and %g2 is the vector */
1481#ifdef INTR0x60_INTC_EXTRA_HANDLER
1482intr0x60_handle_intc_extra_handler:
1483INTR0x60_INTC_EXTRA_HANDLER
1484#endif /* INTR0x60_INTC_EXTRA_HANDLER */
1485
1486intr0x60_handle_piu_intc_retry:
1487 /* Retry the instruction that was trapped */
1488 retry
1489#endif /* INTR0x60_MONDO_22_V */
1490
1491 /* If we get here, the interrupt status bit didn't deassert */
1492intr0x60_handle_piu_intc_deassert_timeout:
1493 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intc_deassert_timeout)) -> printf("ERROR: INTC status bit did not deassert within INTR0x60_INTX_DEASSERT_TIMEOUT iterations",*,1)
1494 EXIT_BAD
1495
1496
1497#if INTR0x60_MONDO_23_V
1498 /************ Handle INTD ***********/
1499intr0x60_handle_piu_intd:
1500 /* Check whether this thread matches this INO */
1501#ifdef PORTABLE_CORE
1502 and %g1, 0x7, %g7
1503 cmp %g7/*tid*/, INTR0x60_MONDO_23_THREAD
1504#else
1505 cmp %g1/*tid*/, INTR0x60_MONDO_23_THREAD
1506#endif
1507 bne intr0x60_handle_piu_bad_thread
1508 nop
1509 /* Clear the interrupt */
1510intr0x60_handle_piu_intd_deassert:
1511#ifdef FC_NO_PEU_VERA
1512#ifdef USE_BOBO
1513 ! Offset accesses by PCIE_MEM64_OFFSET since
1514 ! BAR is set that way. Physical addresses generated via TSB
1515 ! have this offset so mimic that when accessing directly, as here.
1516 best_set_reg(mpeval(N2_PCIE_BASE_ADDR
1517 + MEM64_OFFSET_BASE_REG_DATA
1518 + PCIE_MEM64_OFFSET
1519 + BOBO_INTR_VECT_STATUS_OFFSET), %g7, %g4)
1520 ! Interrupt type
1521 mov eval(1 << 3), %g5
1522#else /* USE_BOBO */
1523 ! Offset accesses by PCIE_MEM64_OFFSET since
1524 ! BAR is set that way. Physical addresses generated via TSB
1525 ! have this offset so mimic that when accessing directly, as here.
1526 best_set_reg(mpeval(N2_PCIE_BASE_ADDR
1527 + MEM64_OFFSET_BASE_REG_DATA
1528 + PCIE_MEM64_OFFSET
1529 + (INTR0x60_MONDO_23_DMAEPT_ENGINE << 8)
1530 + DMAEPT_INTERRUPT_ACK), %g7, %g4)
1531 ! Interrupt type
1532 best_set_reg(DMAEPT_INTERRUPT_ACK_INTD, %g7, %g5)
1533#endif /* USE_BOBO */
1534 stwa %g5, [%g4] ASI_NL
1535#else /* FC_NO_PEU_VERA */
1536 ! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intd_deassert)) -> EnablePCIeIgCmd ("INTD", 0, 0, "DEASSERT", 1, *, 1 )
1537#endif /* FC_NO_PEU_VERA */
1538
1539 /* Loop on the INTX Status Register until the deassert message
1540 * has arrived and been processed. */
1541 best_set_reg(PCI_E_INTX_STATUS_ADDR, %g5, %g4)
1542 best_set_reg(INTR0x60_INTX_DEASSERT_TIMEOUT, %g5, %g6)
1543intr0x60_handle_piu_intd_deassert_loop:
1544 brz %g6, intr0x60_handle_piu_intd_deassert_timeout
1545 dec %g6
1546 ldx [%g4], %g3
1547 and %g3, 1, %g3 ! 1 == bit for INTD
1548 brnz %g3, intr0x60_handle_piu_intd_deassert_loop
1549 set 1, %g3
1550intr0x60_handle_piu_intd_clear:
1551 best_set_reg(PCI_E_INT_D_CLEAR_ADDR, %g5, %g4)
1552 stx %g3, [%g4]
1553 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+3*PCI_E_INT_CLEAR_STEP), %g5, %g4)
1554 stx %g0, [%g4]
1555 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
1556 stx %g0, [%g4]
1557
1558 /* Include any extra INTD handler from the user */
1559 /* The code can assume that %g1 is the thread and %g2 is the vector */
1560#ifdef INTR0x60_INTD_EXTRA_HANDLER
1561intr0x60_handle_intd_extra_handler:
1562INTR0x60_INTD_EXTRA_HANDLER
1563#endif /* INTR0x60_INTD_EXTRA_HANDLER */
1564
1565intr0x60_handle_piu_intd_retry:
1566 /* Retry the instruction that was trapped */
1567 retry
1568#endif /* INTR0x60_MONDO_23_V */
1569
1570 /* If we get here, the interrupt status bit didn't deassert */
1571intr0x60_handle_piu_intd_deassert_timeout:
1572 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intd_deassert_timeout)) -> printf("ERROR: INTD status bit did not deassert within INTR0x60_INTX_DEASSERT_TIMEOUT iterations",*,1)
1573 EXIT_BAD
1574
1575
1576
1577
1578
1579#ifdef INTR0x60_MSI_0_NUM
1580 /************ Handle MSI 0 ***********/
1581intr0x60_handle_piu_msi_0:
1582!WIP: /* Check whether this thread matches this INO */
1583!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
1584!WIP: bne intr0x60_handle_piu_bad_thread
1585!WIP: nop
1586 /* Clear the interrupt */
1587 /* MSI Clear reg. */
1588intr0x60_handle_piu_msi_0_clear_eqwr:
1589 set 1, %g4
1590 sllx %g4, 62, %g4 ! EQWR_N is bit 62
1591 best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
1592 +PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_0_NUM),
1593 %g7, %g5)
1594 stx %g4, [%g5] ! clear EQWR in MSI map reg.
1595 membar #Sync
1596
1597intr0x60_handle_piu_msi_0_disable_eq:
1598 set 1, %g4
1599 sllx %g4, 44, %g4 ! DIS is bit 44
1600 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
1601 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_0_EQN),
1602 %g7, %g5)
1603 stx %g4, [%g5]
1604
1605 ! Set Event Queue Head = Event Queue Tail
1606intr0x60_handle_piu_msi_0_reset_eq_head:
1607 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
1608 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_0_EQN),
1609 %g7, %g5)
1610 ldx [%g5], %g6
1611 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
1612 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_0_EQN),
1613 %g7, %g5)
1614 stx %g6, [%g5]
1615
1616intr0x60_handle_piu_msi_0_clear_int:
1617 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
1618 +(4+INTR0x60_MSI_0_EQN)*PCI_E_INT_CLEAR_STEP),
1619 %g5, %g4)
1620 stx %g0, [%g4]
1621
1622 /* Include any extra MSI handler from the user that needs to be
1623 * executed while the mondo busy flag is still asserted. */
1624 /* The code can assume that %g1 is the thread,
1625 * %g2 is the vector, and
1626 * %g3 is the INO */
1627#ifdef INTR0x60_MSI_0_EXTRA_HANDLER_WHILE_BUSY
1628intr0x60_handle_msi_0_extra_handler_while_busy:
1629INTR0x60_MSI_0_EXTRA_HANDLER_WHILE_BUSY
1630#endif /* INTR0x60_MSI_0_EXTRA_HANDLER_WHILE_BUSY */
1631
1632intr0x60_handle_piu_msi_0_clear_mondo_busy:
1633 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
1634 stx %g0, [%g4]
1635
1636 /* Include any extra MSI handler from the user that needs to be
1637 * executed while the event queue is disabled. */
1638 /* The code can assume that %g1 is the thread,
1639 * %g2 is the vector, and
1640 * %g3 is the INO */
1641#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1642intr0x60_handle_msi_extra_handler_while_eq_disabled_0:
1643INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1644#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
1645
1646intr0x60_handle_piu_msi_0_enable_eq:
1647 set 1, %g4
1648 sllx %g4, 44, %g4 ! EN is bit 44
1649 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
1650 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_0_EQN),
1651 %g7, %g5)
1652 stx %g4, [%g5]
1653
1654 ba intr0x60_handle_msi_extra_handler
1655 nop
1656#endif /* INTR0x60_MSI_0_NUM */
1657
1658
1659#ifdef INTR0x60_MSI_1_NUM
1660 /************ Handle MSI 1 ***********/
1661intr0x60_handle_piu_msi_1:
1662!WIP: /* Check whether this thread matches this INO */
1663!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
1664!WIP: bne intr0x60_handle_piu_bad_thread
1665!WIP: nop
1666 /* Clear the interrupt */
1667 /* MSI Clear reg. */
1668intr0x60_handle_piu_msi_1_clear_eqwr:
1669 set 1, %g4
1670 sllx %g4, 62, %g4 ! EQWR_N is bit 62
1671 best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
1672 +PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_1_NUM),
1673 %g7, %g5)
1674 stx %g4, [%g5] ! clear EQWR in MSI map reg.
1675 membar #Sync
1676
1677intr0x60_handle_piu_msi_1_disable_eq:
1678 set 1, %g4
1679 sllx %g4, 44, %g4 ! DIS is bit 44
1680 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
1681 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_1_EQN),
1682 %g7, %g5)
1683 stx %g4, [%g5]
1684
1685 ! Set Event Queue Head = Event Queue Tail
1686intr0x60_handle_piu_msi_1_reset_eq_head:
1687 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
1688 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_1_EQN),
1689 %g7, %g5)
1690 ldx [%g5], %g6
1691 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
1692 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_1_EQN),
1693 %g7, %g5)
1694 stx %g6, [%g5]
1695
1696intr0x60_handle_piu_msi_1_clear_int:
1697 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
1698 +(4+INTR0x60_MSI_1_EQN)*PCI_E_INT_CLEAR_STEP),
1699 %g5, %g4)
1700 stx %g0, [%g4]
1701
1702 /* Include any extra MSI handler from the user that needs to be
1703 * executed while the mondo busy flag is still asserted. */
1704 /* The code can assume that %g1 is the thread,
1705 * %g2 is the vector, and
1706 * %g3 is the INO */
1707#ifdef INTR0x60_MSI_1_EXTRA_HANDLER_WHILE_BUSY
1708intr0x60_handle_msi_1_extra_handler_while_busy:
1709INTR0x60_MSI_1_EXTRA_HANDLER_WHILE_BUSY
1710#endif /* INTR0x60_MSI_1_EXTRA_HANDLER_WHILE_BUSY */
1711
1712intr0x60_handle_piu_msi_1_clear_mondo_busy:
1713 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
1714 stx %g0, [%g4]
1715
1716 /* Include any extra MSI handler from the user that needs to be
1717 * executed while the event queue is disabled. */
1718 /* The code can assume that %g1 is the thread,
1719 * %g2 is the vector, and
1720 * %g3 is the INO */
1721#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1722intr0x60_handle_msi_extra_handler_while_eq_disabled_1:
1723INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1724#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
1725
1726intr0x60_handle_piu_msi_1_enable_eq:
1727 set 1, %g4
1728 sllx %g4, 44, %g4 ! EN is bit 44
1729 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
1730 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_1_EQN),
1731 %g7, %g5)
1732 stx %g4, [%g5]
1733
1734 ba intr0x60_handle_msi_extra_handler
1735 nop
1736#endif /* INTR0x60_MSI_1_NUM */
1737
1738
1739#ifdef INTR0x60_MSI_2_NUM
1740 /************ Handle MSI 2 ***********/
1741intr0x60_handle_piu_msi_2:
1742!WIP: /* Check whether this thread matches this INO */
1743!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
1744!WIP: bne intr0x60_handle_piu_bad_thread
1745!WIP: nop
1746 /* Clear the interrupt */
1747 /* MSI Clear reg. */
1748intr0x60_handle_piu_msi_2_clear_eqwr:
1749 set 1, %g4
1750 sllx %g4, 62, %g4 ! EQWR_N is bit 62
1751 best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
1752 +PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_2_NUM),
1753 %g7, %g5)
1754 stx %g4, [%g5] ! clear EQWR in MSI map reg.
1755 membar #Sync
1756
1757intr0x60_handle_piu_msi_2_disable_eq:
1758 set 1, %g4
1759 sllx %g4, 44, %g4 ! DIS is bit 44
1760 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
1761 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_2_EQN),
1762 %g7, %g5)
1763 stx %g4, [%g5]
1764
1765 ! Set Event Queue Head = Event Queue Tail
1766intr0x60_handle_piu_msi_2_reset_eq_head:
1767 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
1768 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_2_EQN),
1769 %g7, %g5)
1770 ldx [%g5], %g6
1771 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
1772 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_2_EQN),
1773 %g7, %g5)
1774 stx %g6, [%g5]
1775
1776intr0x60_handle_piu_msi_2_clear_int:
1777 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
1778 +(4+INTR0x60_MSI_2_EQN)*PCI_E_INT_CLEAR_STEP),
1779 %g5, %g4)
1780 stx %g0, [%g4]
1781
1782 /* Include any extra MSI handler from the user that needs to be
1783 * executed while the mondo busy flag is still asserted. */
1784 /* The code can assume that %g1 is the thread,
1785 * %g2 is the vector, and
1786 * %g3 is the INO */
1787#ifdef INTR0x60_MSI_2_EXTRA_HANDLER_WHILE_BUSY
1788intr0x60_handle_msi_2_extra_handler_while_busy:
1789INTR0x60_MSI_2_EXTRA_HANDLER_WHILE_BUSY
1790#endif /* INTR0x60_MSI_2_EXTRA_HANDLER_WHILE_BUSY */
1791
1792intr0x60_handle_piu_msi_2_clear_mondo_busy:
1793 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
1794 stx %g0, [%g4]
1795
1796 /* Include any extra MSI handler from the user that needs to be
1797 * executed while the event queue is disabled. */
1798 /* The code can assume that %g1 is the thread,
1799 * %g2 is the vector, and
1800 * %g3 is the INO */
1801#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1802intr0x60_handle_msi_extra_handler_while_eq_disabled_2:
1803INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1804#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
1805
1806intr0x60_handle_piu_msi_2_enable_eq:
1807 set 1, %g4
1808 sllx %g4, 44, %g4 ! EN is bit 44
1809 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
1810 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_2_EQN),
1811 %g7, %g5)
1812 stx %g4, [%g5]
1813
1814 ba intr0x60_handle_msi_extra_handler
1815 nop
1816#endif /* INTR0x60_MSI_2_NUM */
1817
1818
1819#ifdef INTR0x60_MSI_3_NUM
1820 /************ Handle MSI 3 ***********/
1821intr0x60_handle_piu_msi_3:
1822!WIP: /* Check whether this thread matches this INO */
1823!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
1824!WIP: bne intr0x60_handle_piu_bad_thread
1825!WIP: nop
1826 /* Clear the interrupt */
1827 /* MSI Clear reg. */
1828intr0x60_handle_piu_msi_3_clear_eqwr:
1829 set 1, %g4
1830 sllx %g4, 62, %g4 ! EQWR_N is bit 62
1831 best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
1832 +PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_3_NUM),
1833 %g7, %g5)
1834 stx %g4, [%g5] ! clear EQWR in MSI map reg.
1835 membar #Sync
1836
1837intr0x60_handle_piu_msi_3_disable_eq:
1838 set 1, %g4
1839 sllx %g4, 44, %g4 ! DIS is bit 44
1840 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
1841 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_3_EQN),
1842 %g7, %g5)
1843 stx %g4, [%g5]
1844
1845 ! Set Event Queue Head = Event Queue Tail
1846intr0x60_handle_piu_msi_3_reset_eq_head:
1847 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
1848 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_3_EQN),
1849 %g7, %g5)
1850 ldx [%g5], %g6
1851 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
1852 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_3_EQN),
1853 %g7, %g5)
1854 stx %g6, [%g5]
1855
1856intr0x60_handle_piu_msi_3_clear_int:
1857 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
1858 +(4+INTR0x60_MSI_3_EQN)*PCI_E_INT_CLEAR_STEP),
1859 %g5, %g4)
1860 stx %g0, [%g4]
1861
1862 /* Include any extra MSI handler from the user that needs to be
1863 * executed while the mondo busy flag is still asserted. */
1864 /* The code can assume that %g1 is the thread,
1865 * %g2 is the vector, and
1866 * %g3 is the INO */
1867#ifdef INTR0x60_MSI_3_EXTRA_HANDLER_WHILE_BUSY
1868intr0x60_handle_msi_3_extra_handler_while_busy:
1869INTR0x60_MSI_3_EXTRA_HANDLER_WHILE_BUSY
1870#endif /* INTR0x60_MSI_3_EXTRA_HANDLER_WHILE_BUSY */
1871
1872intr0x60_handle_piu_msi_3_clear_mondo_busy:
1873 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
1874 stx %g0, [%g4]
1875
1876 /* Include any extra MSI handler from the user that needs to be
1877 * executed while the event queue is disabled. */
1878 /* The code can assume that %g1 is the thread,
1879 * %g2 is the vector, and
1880 * %g3 is the INO */
1881#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1882intr0x60_handle_msi_extra_handler_while_eq_disabled_3:
1883INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1884#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
1885
1886intr0x60_handle_piu_msi_3_enable_eq:
1887 set 1, %g4
1888 sllx %g4, 44, %g4 ! EN is bit 44
1889 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
1890 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_3_EQN),
1891 %g7, %g5)
1892 stx %g4, [%g5]
1893
1894 ba intr0x60_handle_msi_extra_handler
1895 nop
1896#endif /* INTR0x60_MSI_3_NUM */
1897
1898
1899#ifdef INTR0x60_MSI_4_NUM
1900 /************ Handle MSI 4 ***********/
1901intr0x60_handle_piu_msi_4:
1902!WIP: /* Check whether this thread matches this INO */
1903!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
1904!WIP: bne intr0x60_handle_piu_bad_thread
1905!WIP: nop
1906 /* Clear the interrupt */
1907 /* MSI Clear reg. */
1908intr0x60_handle_piu_msi_4_clear_eqwr:
1909 set 1, %g4
1910 sllx %g4, 62, %g4 ! EQWR_N is bit 62
1911 best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
1912 +PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_4_NUM),
1913 %g7, %g5)
1914 stx %g4, [%g5] ! clear EQWR in MSI map reg.
1915 membar #Sync
1916
1917intr0x60_handle_piu_msi_4_disable_eq:
1918 set 1, %g4
1919 sllx %g4, 44, %g4 ! DIS is bit 44
1920 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
1921 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_4_EQN),
1922 %g7, %g5)
1923 stx %g4, [%g5]
1924
1925 ! Set Event Queue Head = Event Queue Tail
1926intr0x60_handle_piu_msi_4_reset_eq_head:
1927 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
1928 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_4_EQN),
1929 %g7, %g5)
1930 ldx [%g5], %g6
1931 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
1932 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_4_EQN),
1933 %g7, %g5)
1934 stx %g6, [%g5]
1935
1936intr0x60_handle_piu_msi_4_clear_int:
1937 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
1938 +(4+INTR0x60_MSI_4_EQN)*PCI_E_INT_CLEAR_STEP),
1939 %g5, %g4)
1940 stx %g0, [%g4]
1941
1942 /* Include any extra MSI handler from the user that needs to be
1943 * executed while the mondo busy flag is still asserted. */
1944 /* The code can assume that %g1 is the thread,
1945 * %g2 is the vector, and
1946 * %g3 is the INO */
1947#ifdef INTR0x60_MSI_4_EXTRA_HANDLER_WHILE_BUSY
1948intr0x60_handle_msi_4_extra_handler_while_busy:
1949INTR0x60_MSI_4_EXTRA_HANDLER_WHILE_BUSY
1950#endif /* INTR0x60_MSI_4_EXTRA_HANDLER_WHILE_BUSY */
1951
1952intr0x60_handle_piu_msi_4_clear_mondo_busy:
1953 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
1954 stx %g0, [%g4]
1955
1956 /* Include any extra MSI handler from the user that needs to be
1957 * executed while the event queue is disabled. */
1958 /* The code can assume that %g1 is the thread,
1959 * %g2 is the vector, and
1960 * %g3 is the INO */
1961#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1962intr0x60_handle_msi_extra_handler_while_eq_disabled_4:
1963INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
1964#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
1965
1966intr0x60_handle_piu_msi_4_enable_eq:
1967 set 1, %g4
1968 sllx %g4, 44, %g4 ! EN is bit 44
1969 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
1970 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_4_EQN),
1971 %g7, %g5)
1972 stx %g4, [%g5]
1973
1974 ba intr0x60_handle_msi_extra_handler
1975 nop
1976#endif /* INTR0x60_MSI_4_NUM */
1977
1978
1979#ifdef INTR0x60_MSI_5_NUM
1980 /************ Handle MSI 5 ***********/
1981intr0x60_handle_piu_msi_5:
1982!WIP: /* Check whether this thread matches this INO */
1983!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
1984!WIP: bne intr0x60_handle_piu_bad_thread
1985!WIP: nop
1986 /* Clear the interrupt */
1987 /* MSI Clear reg. */
1988intr0x60_handle_piu_msi_5_clear_eqwr:
1989 set 1, %g4
1990 sllx %g4, 62, %g4 ! EQWR_N is bit 62
1991 best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
1992 +PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_5_NUM),
1993 %g7, %g5)
1994 stx %g4, [%g5] ! clear EQWR in MSI map reg.
1995 membar #Sync
1996
1997intr0x60_handle_piu_msi_5_disable_eq:
1998 set 1, %g4
1999 sllx %g4, 44, %g4 ! DIS is bit 44
2000 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
2001 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_5_EQN),
2002 %g7, %g5)
2003 stx %g4, [%g5]
2004
2005 ! Set Event Queue Head = Event Queue Tail
2006intr0x60_handle_piu_msi_5_reset_eq_head:
2007 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
2008 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_5_EQN),
2009 %g7, %g5)
2010 ldx [%g5], %g6
2011 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
2012 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_5_EQN),
2013 %g7, %g5)
2014 stx %g6, [%g5]
2015
2016intr0x60_handle_piu_msi_5_clear_int:
2017 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
2018 +(4+INTR0x60_MSI_5_EQN)*PCI_E_INT_CLEAR_STEP),
2019 %g5, %g4)
2020 stx %g0, [%g4]
2021
2022 /* Include any extra MSI handler from the user that needs to be
2023 * executed while the mondo busy flag is still asserted. */
2024 /* The code can assume that %g1 is the thread,
2025 * %g2 is the vector, and
2026 * %g3 is the INO */
2027#ifdef INTR0x60_MSI_5_EXTRA_HANDLER_WHILE_BUSY
2028intr0x60_handle_msi_5_extra_handler_while_busy:
2029INTR0x60_MSI_5_EXTRA_HANDLER_WHILE_BUSY
2030#endif /* INTR0x60_MSI_5_EXTRA_HANDLER_WHILE_BUSY */
2031
2032intr0x60_handle_piu_msi_5_clear_mondo_busy:
2033 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
2034 stx %g0, [%g4]
2035
2036 /* Include any extra MSI handler from the user that needs to be
2037 * executed while the event queue is disabled. */
2038 /* The code can assume that %g1 is the thread,
2039 * %g2 is the vector, and
2040 * %g3 is the INO */
2041#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
2042intr0x60_handle_msi_extra_handler_while_eq_disabled_5:
2043INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
2044#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
2045
2046intr0x60_handle_piu_msi_5_enable_eq:
2047 set 1, %g4
2048 sllx %g4, 44, %g4 ! EN is bit 44
2049 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
2050 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_5_EQN),
2051 %g7, %g5)
2052 stx %g4, [%g5]
2053
2054 ba intr0x60_handle_msi_extra_handler
2055 nop
2056#endif /* INTR0x60_MSI_5_NUM */
2057
2058
2059#ifdef INTR0x60_MSI_6_NUM
2060 /************ Handle MSI 6 ***********/
2061intr0x60_handle_piu_msi_6:
2062!WIP: /* Check whether this thread matches this INO */
2063!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
2064!WIP: bne intr0x60_handle_piu_bad_thread
2065!WIP: nop
2066 /* Clear the interrupt */
2067 /* MSI Clear reg. */
2068intr0x60_handle_piu_msi_6_clear_eqwr:
2069 set 1, %g4
2070 sllx %g4, 62, %g4 ! EQWR_N is bit 62
2071 best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
2072 +PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_6_NUM),
2073 %g7, %g5)
2074 stx %g4, [%g5] ! clear EQWR in MSI map reg.
2075 membar #Sync
2076
2077intr0x60_handle_piu_msi_6_disable_eq:
2078 set 1, %g4
2079 sllx %g4, 44, %g4 ! DIS is bit 44
2080 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
2081 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_6_EQN),
2082 %g7, %g5)
2083 stx %g4, [%g5]
2084
2085 ! Set Event Queue Head = Event Queue Tail
2086intr0x60_handle_piu_msi_6_reset_eq_head:
2087 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
2088 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_6_EQN),
2089 %g7, %g5)
2090 ldx [%g5], %g6
2091 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
2092 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_6_EQN),
2093 %g7, %g5)
2094 stx %g6, [%g5]
2095
2096intr0x60_handle_piu_msi_6_clear_int:
2097 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
2098 +(4+INTR0x60_MSI_6_EQN)*PCI_E_INT_CLEAR_STEP),
2099 %g5, %g4)
2100 stx %g0, [%g4]
2101
2102 /* Include any extra MSI handler from the user that needs to be
2103 * executed while the mondo busy flag is still asserted. */
2104 /* The code can assume that %g1 is the thread,
2105 * %g2 is the vector, and
2106 * %g3 is the INO */
2107#ifdef INTR0x60_MSI_6_EXTRA_HANDLER_WHILE_BUSY
2108intr0x60_handle_msi_6_extra_handler_while_busy:
2109INTR0x60_MSI_6_EXTRA_HANDLER_WHILE_BUSY
2110#endif /* INTR0x60_MSI_6_EXTRA_HANDLER_WHILE_BUSY */
2111
2112intr0x60_handle_piu_msi_6_clear_mondo_busy:
2113 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
2114 stx %g0, [%g4]
2115
2116 /* Include any extra MSI handler from the user that needs to be
2117 * executed while the event queue is disabled. */
2118 /* The code can assume that %g1 is the thread,
2119 * %g2 is the vector, and
2120 * %g3 is the INO */
2121#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
2122intr0x60_handle_msi_extra_handler_while_eq_disabled_6:
2123INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
2124#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
2125
2126intr0x60_handle_piu_msi_6_enable_eq:
2127 set 1, %g4
2128 sllx %g4, 44, %g4 ! EN is bit 44
2129 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
2130 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_6_EQN),
2131 %g7, %g5)
2132 stx %g4, [%g5]
2133
2134 ba intr0x60_handle_msi_extra_handler
2135 nop
2136#endif /* INTR0x60_MSI_6_NUM */
2137
2138
2139#ifdef INTR0x60_MSI_7_NUM
2140 /************ Handle MSI 7 ***********/
2141intr0x60_handle_piu_msi_7:
2142!WIP: /* Check whether this thread matches this INO */
2143!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
2144!WIP: bne intr0x60_handle_piu_bad_thread
2145!WIP: nop
2146 /* Clear the interrupt */
2147 /* MSI Clear reg. */
2148intr0x60_handle_piu_msi_7_clear_eqwr:
2149 set 1, %g4
2150 sllx %g4, 62, %g4 ! EQWR_N is bit 62
2151 best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
2152 +PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_7_NUM),
2153 %g7, %g5)
2154 stx %g4, [%g5] ! clear EQWR in MSI map reg.
2155 membar #Sync
2156
2157intr0x60_handle_piu_msi_7_disable_eq:
2158 set 1, %g4
2159 sllx %g4, 44, %g4 ! DIS is bit 44
2160 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
2161 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_7_EQN),
2162 %g7, %g5)
2163 stx %g4, [%g5]
2164
2165 ! Set Event Queue Head = Event Queue Tail
2166intr0x60_handle_piu_msi_7_reset_eq_head:
2167 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
2168 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_7_EQN),
2169 %g7, %g5)
2170 ldx [%g5], %g6
2171 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
2172 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_7_EQN),
2173 %g7, %g5)
2174 stx %g6, [%g5]
2175
2176intr0x60_handle_piu_msi_7_clear_int:
2177 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
2178 +(4+INTR0x60_MSI_7_EQN)*PCI_E_INT_CLEAR_STEP),
2179 %g5, %g4)
2180 stx %g0, [%g4]
2181
2182 /* Include any extra MSI handler from the user that needs to be
2183 * executed while the mondo busy flag is still asserted. */
2184 /* The code can assume that %g1 is the thread,
2185 * %g2 is the vector, and
2186 * %g3 is the INO */
2187#ifdef INTR0x60_MSI_7_EXTRA_HANDLER_WHILE_BUSY
2188intr0x60_handle_msi_7_extra_handler_while_busy:
2189INTR0x60_MSI_7_EXTRA_HANDLER_WHILE_BUSY
2190#endif /* INTR0x60_MSI_7_EXTRA_HANDLER_WHILE_BUSY */
2191
2192intr0x60_handle_piu_msi_7_clear_mondo_busy:
2193 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
2194 stx %g0, [%g4]
2195
2196 /* Include any extra MSI handler from the user that needs to be
2197 * executed while the event queue is disabled. */
2198 /* The code can assume that %g1 is the thread,
2199 * %g2 is the vector, and
2200 * %g3 is the INO */
2201#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
2202intr0x60_handle_msi_extra_handler_while_eq_disabled_7:
2203INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
2204#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
2205
2206intr0x60_handle_piu_msi_7_enable_eq:
2207 set 1, %g4
2208 sllx %g4, 44, %g4 ! EN is bit 44
2209 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
2210 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_7_EQN),
2211 %g7, %g5)
2212 stx %g4, [%g5]
2213
2214 ba intr0x60_handle_msi_extra_handler
2215 nop
2216#endif /* INTR0x60_MSI_7_NUM */
2217
2218
2219
2220
2221 /* Include any extra MSI handler from the user */
2222 /* The code can assume that %g1 is the thread,
2223 * %g2 is the vector, and
2224 * %g3 is the INO */
2225intr0x60_handle_msi_extra_handler:
2226#ifdef INTR0x60_MSI_EXTRA_HANDLER
2227INTR0x60_MSI_EXTRA_HANDLER
2228#endif /* INTR0x60_MSI_EXTRA_HANDLER */
2229
2230intr0x60_handle_piu_msi_retry:
2231 /* Retry the instruction that was trapped */
2232 retry
2233
2234
2235#ifdef INTR0x60_PM_PME_EQN
2236 /************ Handle PM_PME ***********/
2237intr0x60_handle_piu_pm_pme:
2238!WIP: /* Check whether this thread matches this INO */
2239!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
2240!WIP: bne intr0x60_handle_piu_bad_thread
2241!WIP: nop
2242 /* Clear the interrupt */
2243
2244intr0x60_handle_piu_pm_pme_disable_eq:
2245 set 1, %g4
2246 sllx %g4, 44, %g4 ! DIS is bit 44
2247 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
2248 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_PM_PME_EQN),
2249 %g7, %g5)
2250 stx %g4, [%g5]
2251
2252 ! Set Event Queue Head = Event Queue Tail
2253intr0x60_handle_piu_pm_pme_reset_eq_head:
2254 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
2255 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_PM_PME_EQN),
2256 %g7, %g5)
2257 ldx [%g5], %g6
2258 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
2259 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_PM_PME_EQN),
2260 %g7, %g5)
2261 stx %g6, [%g5]
2262
2263intr0x60_handle_piu_pm_pme_clear_int:
2264 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
2265 +(4+INTR0x60_PM_PME_EQN)*PCI_E_INT_CLEAR_STEP),
2266 %g5, %g4)
2267 stx %g0, [%g4]
2268
2269intr0x60_handle_piu_pm_pme_clear_mondo_busy:
2270 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
2271 stx %g0, [%g4]
2272
2273 /* Include any extra PM_PME handler from the user that needs to be
2274 * executed while the event queue is disabled. */
2275 /* The code can assume that %g1 is the thread,
2276 * %g2 is the vector, and
2277 * %g3 is the INO */
2278#ifdef INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED
2279intr0x60_handle_pm_pme_extra_handler_while_eq_disabled:
2280INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED
2281#endif /* INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED */
2282
2283intr0x60_handle_piu_pm_pme_enable_eq:
2284 set 1, %g4
2285 sllx %g4, 44, %g4 ! EN is bit 44
2286 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
2287 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PM_PME_EQN),
2288 %g7, %g5)
2289 stx %g4, [%g5]
2290
2291 /* Include any extra PM_PME handler from the user */
2292 /* The code can assume that %g1 is the thread,
2293 * %g2 is the vector, and
2294 * %g3 is the INO */
2295intr0x60_handle_pm_pme_extra_handler:
2296#ifdef INTR0x60_PM_PME_EXTRA_HANDLER
2297INTR0x60_PM_PME_EXTRA_HANDLER
2298#endif /* INTR0x60_PM_PME_EXTRA_HANDLER */
2299
2300intr0x60_handle_piu_pm_pme_retry:
2301 /* Retry the instruction that was trapped */
2302 retry
2303#endif /* INTR0x60_PM_PME_EQN */
2304
2305
2306#ifdef INTR0x60_PME_TO_ACK_EQN
2307 /************ Handle PME_TO_ACK ***********/
2308intr0x60_handle_piu_pme_to_ack:
2309!WIP: /* Check whether this thread matches this INO */
2310!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
2311!WIP: bne intr0x60_handle_piu_bad_thread
2312!WIP: nop
2313 /* Clear the interrupt */
2314
2315intr0x60_handle_piu_pme_to_ack_disable_eq:
2316 set 1, %g4
2317 sllx %g4, 44, %g4 ! DIS is bit 44
2318 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
2319 +PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_PME_TO_ACK_EQN),
2320 %g7, %g5)
2321 stx %g4, [%g5]
2322
2323 ! Set Event Queue Head = Event Queue Tail
2324intr0x60_handle_piu_pme_to_ack_reset_eq_head:
2325 best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
2326 +PCI_E_EV_QUE_TAIL_STEP*INTR0x60_PME_TO_ACK_EQN),
2327 %g7, %g5)
2328 ldx [%g5], %g6
2329 best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
2330 +PCI_E_EV_QUE_HEAD_STEP*INTR0x60_PME_TO_ACK_EQN),
2331 %g7, %g5)
2332 stx %g6, [%g5]
2333
2334intr0x60_handle_piu_pme_to_ack_clear_int:
2335 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
2336 +(4+INTR0x60_PME_TO_ACK_EQN)*PCI_E_INT_CLEAR_STEP),
2337 %g5, %g4)
2338 stx %g0, [%g4]
2339
2340intr0x60_handle_piu_pme_to_ack_clear_mondo_busy:
2341 best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
2342 stx %g0, [%g4]
2343
2344 /* Include any extra PME_TO_ACK handler from the user that needs to be
2345 * executed while the event queue is disabled. */
2346 /* The code can assume that %g1 is the thread,
2347 * %g2 is the vector, and
2348 * %g3 is the INO */
2349#ifdef INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED
2350intr0x60_handle_pme_to_ack_extra_handler_while_eq_disabled:
2351INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED
2352#endif /* INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED */
2353
2354intr0x60_handle_piu_pme_to_ack_enable_eq:
2355 set 1, %g4
2356 sllx %g4, 44, %g4 ! EN is bit 44
2357 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
2358 +PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PME_TO_ACK_EQN),
2359 %g7, %g5)
2360 stx %g4, [%g5]
2361
2362 /* Include any extra PME_TO_ACK handler from the user */
2363 /* The code can assume that %g1 is the thread,
2364 * %g2 is the vector, and
2365 * %g3 is the INO */
2366intr0x60_handle_pme_to_ack_extra_handler:
2367#ifdef INTR0x60_PME_TO_ACK_EXTRA_HANDLER
2368INTR0x60_PME_TO_ACK_EXTRA_HANDLER
2369#endif /* INTR0x60_PME_TO_ACK_EXTRA_HANDLER */
2370
2371intr0x60_handle_piu_pme_to_ack_retry:
2372 /* Retry the instruction that was trapped */
2373 retry
2374#endif /* INTR0x60_PME_TO_ACK_EQN */
2375
2376
2377intr0x60_handle_piu_bad_thread:
2378 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_bad_thread)) -> printf("ERROR: Mondo delivered to wrong thread",*,1)
2379 EXIT_BAD
2380#endif /* INTR0x60_MONDO_IV */
2381
2382
2383#if (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV)
2384/************************************************************************/
2385/* Handle SSI parity error interrupts */
2386
2387intr0x60_handle_ssi_err:
2388 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_ssi_err)) -> printf("INFO: SSI parity error interrupt received",*,1)
2389 /* Make sure that this thread is the right one */
2390 best_set_reg(INTR0x60_SSI_ERR_THREAD, %g7, %g4)
2391#ifdef PORTABLE_CORE
2392 and %g1, 0x7, %g7
2393 cmp %g7, %g4
2394#else
2395 cmp %g1, %g4
2396#endif
2397 bne intr0x60_handle_ssi_err_bad_thread
2398 nop
2399
2400 /* Include any extra SSI parity error handler from the user */
2401 /* The code can assume that %g1 is the thread and %g2 is the vector */
2402#ifdef INTR0x60_SSI_ERR_EXTRA_HANDLER
2403intr0x60_handle_ssi_err_extra_handler:
2404INTR0x60_SSI_ERR_EXTRA_HANDLER
2405#endif /* INTR0x60_SSI_ERR_EXTRA_HANDLER */
2406
2407intr0x60_handle_ssi_err_retry:
2408 /* Retry the instruction that was trapped */
2409 retry
2410
2411intr0x60_handle_ssi_err_bad_thread:
2412 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_ssi_err_bad_thread)) -> printf("ERROR: SSI parity error interrupt received on unexpected thread",*,1)
2413 EXIT_BAD
2414#endif /* (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV) */
2415
2416
2417#if (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
2418/************************************************************************/
2419/* Handle SSI_EXT_INT_L interrupts */
2420
2421intr0x60_handle_ssi_int:
2422 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_ssi_int)) -> printf("INFO: SSI_EXT_INT_L interrupt received",*,1)
2423 /* Make sure that this thread is the right one */
2424 best_set_reg(INTR0x60_SSI_INT_THREAD, %g7, %g4)
2425#ifdef PORTABLE_CORE
2426 and %g1, 0x7, %g7
2427 cmp %g7, %g4
2428#else
2429 cmp %g1, %g4
2430#endif
2431 bne intr0x60_handle_ssi_int_bad_thread
2432 nop
2433
2434 /* Include any extra SSI_EXT_INT_L handler from the user */
2435 /* The code can assume that %g1 is the thread and %g2 is the vector */
2436#ifdef INTR0x60_SSI_INT_EXTRA_HANDLER
2437intr0x60_handle_ssi_int_extra_handler:
2438INTR0x60_SSI_INT_EXTRA_HANDLER
2439#endif /* INTR0x60_SSI_INT_EXTRA_HANDLER */
2440
2441intr0x60_handle_ssi_int_retry:
2442 /* Retry the instruction that was trapped */
2443 retry
2444
2445intr0x60_handle_ssi_int_bad_thread:
2446 !$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_ssi_int_bad_thread)) -> printf("ERROR: SSI_EXT_INT_L interrupt received on unexpected thread",*,1)
2447 EXIT_BAD
2448#endif /* (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV) */
2449
2450
2451
2452
2453/*
2454 * Need to have some tables to identify the source of the interrupt
2455 * and whether it is expected for this thread.
2456 *
2457 * intr0x60_ivn_to_ig has one byte per interrupt vector number (0-63),
2458 * which indicates the interrupt group, encoded as
2459 * 0 - unused (error)
2460 * 1 - cross-call
2461 * 2 - SSI error
2462 * 3 - SSI_EXT_INT_L
2463 * 4 - NIU
2464 * 5 - PIU mondo
2465 */
2466
2467.data
2468intr0x60_ivn_to_ig:
2469
2470#ifdef INTR0x60_CC_IV_0
2471#define INTR0x60_CC_IV_0_CHECK (INTR0x60_CC_IV_0 == `$1')
2472#else
2473#define INTR0x60_CC_IV_0_CHECK (0)
2474#endif
2475
2476#ifdef INTR0x60_CC_IV_1
2477#define INTR0x60_CC_IV_1_CHECK (INTR0x60_CC_IV_1 == `$1')
2478#else
2479#define INTR0x60_CC_IV_1_CHECK (0)
2480#endif
2481
2482#ifdef INTR0x60_CC_IV_2
2483#define INTR0x60_CC_IV_2_CHECK (INTR0x60_CC_IV_2 == `$1')
2484#else
2485#define INTR0x60_CC_IV_2_CHECK (0)
2486#endif
2487
2488#ifdef INTR0x60_CC_IV_3
2489#define INTR0x60_CC_IV_3_CHECK (INTR0x60_CC_IV_3 == `$1')
2490#else
2491#define INTR0x60_CC_IV_3_CHECK (0)
2492#endif
2493
2494#ifdef INTR0x60_CC_IV_4
2495#define INTR0x60_CC_IV_4_CHECK (INTR0x60_CC_IV_4 == `$1')
2496#else
2497#define INTR0x60_CC_IV_4_CHECK (0)
2498#endif
2499
2500#ifdef INTR0x60_CC_IV_5
2501#define INTR0x60_CC_IV_5_CHECK (INTR0x60_CC_IV_5 == `$1')
2502#else
2503#define INTR0x60_CC_IV_5_CHECK (0)
2504#endif
2505
2506#ifdef INTR0x60_CC_IV_6
2507#define INTR0x60_CC_IV_6_CHECK (INTR0x60_CC_IV_6 == `$1')
2508#else
2509#define INTR0x60_CC_IV_6_CHECK (0)
2510#endif
2511
2512#ifdef INTR0x60_CC_IV_7
2513#define INTR0x60_CC_IV_7_CHECK (INTR0x60_CC_IV_7 == `$1')
2514#else
2515#define INTR0x60_CC_IV_7_CHECK (0)
2516#endif
2517
2518#ifdef INTR0x60_CC_IV_8
2519#define INTR0x60_CC_IV_8_CHECK (INTR0x60_CC_IV_8 == `$1')
2520#else
2521#define INTR0x60_CC_IV_8_CHECK (0)
2522#endif
2523
2524#ifdef INTR0x60_CC_IV_9
2525#define INTR0x60_CC_IV_9_CHECK (INTR0x60_CC_IV_9 == `$1')
2526#else
2527#define INTR0x60_CC_IV_9_CHECK (0)
2528#endif
2529
2530#ifdef INTR0x60_CC_IV_10
2531#define INTR0x60_CC_IV_10_CHECK (INTR0x60_CC_IV_10 == `$1')
2532#else
2533#define INTR0x60_CC_IV_10_CHECK (0)
2534#endif
2535
2536#ifdef INTR0x60_CC_IV_11
2537#define INTR0x60_CC_IV_11_CHECK (INTR0x60_CC_IV_11 == `$1')
2538#else
2539#define INTR0x60_CC_IV_11_CHECK (0)
2540#endif
2541
2542#ifdef INTR0x60_CC_IV_12
2543#define INTR0x60_CC_IV_12_CHECK (INTR0x60_CC_IV_12 == `$1')
2544#else
2545#define INTR0x60_CC_IV_12_CHECK (0)
2546#endif
2547
2548#ifdef INTR0x60_CC_IV_13
2549#define INTR0x60_CC_IV_13_CHECK (INTR0x60_CC_IV_13 == `$1')
2550#else
2551#define INTR0x60_CC_IV_13_CHECK (0)
2552#endif
2553
2554#ifdef INTR0x60_CC_IV_14
2555#define INTR0x60_CC_IV_14_CHECK (INTR0x60_CC_IV_14 == `$1')
2556#else
2557#define INTR0x60_CC_IV_14_CHECK (0)
2558#endif
2559
2560#ifdef INTR0x60_CC_IV_15
2561#define INTR0x60_CC_IV_15_CHECK (INTR0x60_CC_IV_15 == `$1')
2562#else
2563#define INTR0x60_CC_IV_15_CHECK (0)
2564#endif
2565
2566#ifdef INTR0x60_CC_IV_16
2567#define INTR0x60_CC_IV_16_CHECK (INTR0x60_CC_IV_16 == `$1')
2568#else
2569#define INTR0x60_CC_IV_16_CHECK (0)
2570#endif
2571
2572#ifdef INTR0x60_CC_IV_17
2573#define INTR0x60_CC_IV_17_CHECK (INTR0x60_CC_IV_17 == `$1')
2574#else
2575#define INTR0x60_CC_IV_17_CHECK (0)
2576#endif
2577
2578#ifdef INTR0x60_CC_IV_18
2579#define INTR0x60_CC_IV_18_CHECK (INTR0x60_CC_IV_18 == `$1')
2580#else
2581#define INTR0x60_CC_IV_18_CHECK (0)
2582#endif
2583
2584#ifdef INTR0x60_CC_IV_19
2585#define INTR0x60_CC_IV_19_CHECK (INTR0x60_CC_IV_19 == `$1')
2586#else
2587#define INTR0x60_CC_IV_19_CHECK (0)
2588#endif
2589
2590#ifdef INTR0x60_CC_IV_20
2591#define INTR0x60_CC_IV_20_CHECK (INTR0x60_CC_IV_20 == `$1')
2592#else
2593#define INTR0x60_CC_IV_20_CHECK (0)
2594#endif
2595
2596#ifdef INTR0x60_CC_IV_21
2597#define INTR0x60_CC_IV_21_CHECK (INTR0x60_CC_IV_21 == `$1')
2598#else
2599#define INTR0x60_CC_IV_21_CHECK (0)
2600#endif
2601
2602#ifdef INTR0x60_CC_IV_22
2603#define INTR0x60_CC_IV_22_CHECK (INTR0x60_CC_IV_22 == `$1')
2604#else
2605#define INTR0x60_CC_IV_22_CHECK (0)
2606#endif
2607
2608#ifdef INTR0x60_CC_IV_23
2609#define INTR0x60_CC_IV_23_CHECK (INTR0x60_CC_IV_23 == `$1')
2610#else
2611#define INTR0x60_CC_IV_23_CHECK (0)
2612#endif
2613
2614#ifdef INTR0x60_CC_IV_24
2615#define INTR0x60_CC_IV_24_CHECK (INTR0x60_CC_IV_24 == `$1')
2616#else
2617#define INTR0x60_CC_IV_24_CHECK (0)
2618#endif
2619
2620#ifdef INTR0x60_CC_IV_25
2621#define INTR0x60_CC_IV_25_CHECK (INTR0x60_CC_IV_25 == `$1')
2622#else
2623#define INTR0x60_CC_IV_25_CHECK (0)
2624#endif
2625
2626#ifdef INTR0x60_CC_IV_26
2627#define INTR0x60_CC_IV_26_CHECK (INTR0x60_CC_IV_26 == `$1')
2628#else
2629#define INTR0x60_CC_IV_26_CHECK (0)
2630#endif
2631
2632#ifdef INTR0x60_CC_IV_27
2633#define INTR0x60_CC_IV_27_CHECK (INTR0x60_CC_IV_27 == `$1')
2634#else
2635#define INTR0x60_CC_IV_27_CHECK (0)
2636#endif
2637
2638#ifdef INTR0x60_CC_IV_28
2639#define INTR0x60_CC_IV_28_CHECK (INTR0x60_CC_IV_28 == `$1')
2640#else
2641#define INTR0x60_CC_IV_28_CHECK (0)
2642#endif
2643
2644#ifdef INTR0x60_CC_IV_29
2645#define INTR0x60_CC_IV_29_CHECK (INTR0x60_CC_IV_29 == `$1')
2646#else
2647#define INTR0x60_CC_IV_29_CHECK (0)
2648#endif
2649
2650#ifdef INTR0x60_CC_IV_30
2651#define INTR0x60_CC_IV_30_CHECK (INTR0x60_CC_IV_30 == `$1')
2652#else
2653#define INTR0x60_CC_IV_30_CHECK (0)
2654#endif
2655
2656#ifdef INTR0x60_CC_IV_31
2657#define INTR0x60_CC_IV_31_CHECK (INTR0x60_CC_IV_31 == `$1')
2658#else
2659#define INTR0x60_CC_IV_31_CHECK (0)
2660#endif
2661
2662#ifdef INTR0x60_CC_IV_32
2663#define INTR0x60_CC_IV_32_CHECK (INTR0x60_CC_IV_32 == `$1')
2664#else
2665#define INTR0x60_CC_IV_32_CHECK (0)
2666#endif
2667
2668#ifdef INTR0x60_CC_IV_33
2669#define INTR0x60_CC_IV_33_CHECK (INTR0x60_CC_IV_33 == `$1')
2670#else
2671#define INTR0x60_CC_IV_33_CHECK (0)
2672#endif
2673
2674#ifdef INTR0x60_CC_IV_34
2675#define INTR0x60_CC_IV_34_CHECK (INTR0x60_CC_IV_34 == `$1')
2676#else
2677#define INTR0x60_CC_IV_34_CHECK (0)
2678#endif
2679
2680#ifdef INTR0x60_CC_IV_35
2681#define INTR0x60_CC_IV_35_CHECK (INTR0x60_CC_IV_35 == `$1')
2682#else
2683#define INTR0x60_CC_IV_35_CHECK (0)
2684#endif
2685
2686#ifdef INTR0x60_CC_IV_36
2687#define INTR0x60_CC_IV_36_CHECK (INTR0x60_CC_IV_36 == `$1')
2688#else
2689#define INTR0x60_CC_IV_36_CHECK (0)
2690#endif
2691
2692#ifdef INTR0x60_CC_IV_37
2693#define INTR0x60_CC_IV_37_CHECK (INTR0x60_CC_IV_37 == `$1')
2694#else
2695#define INTR0x60_CC_IV_37_CHECK (0)
2696#endif
2697
2698#ifdef INTR0x60_CC_IV_38
2699#define INTR0x60_CC_IV_38_CHECK (INTR0x60_CC_IV_38 == `$1')
2700#else
2701#define INTR0x60_CC_IV_38_CHECK (0)
2702#endif
2703
2704#ifdef INTR0x60_CC_IV_39
2705#define INTR0x60_CC_IV_39_CHECK (INTR0x60_CC_IV_39 == `$1')
2706#else
2707#define INTR0x60_CC_IV_39_CHECK (0)
2708#endif
2709
2710#ifdef INTR0x60_CC_IV_40
2711#define INTR0x60_CC_IV_40_CHECK (INTR0x60_CC_IV_40 == `$1')
2712#else
2713#define INTR0x60_CC_IV_40_CHECK (0)
2714#endif
2715
2716#ifdef INTR0x60_CC_IV_41
2717#define INTR0x60_CC_IV_41_CHECK (INTR0x60_CC_IV_41 == `$1')
2718#else
2719#define INTR0x60_CC_IV_41_CHECK (0)
2720#endif
2721
2722#ifdef INTR0x60_CC_IV_42
2723#define INTR0x60_CC_IV_42_CHECK (INTR0x60_CC_IV_42 == `$1')
2724#else
2725#define INTR0x60_CC_IV_42_CHECK (0)
2726#endif
2727
2728#ifdef INTR0x60_CC_IV_43
2729#define INTR0x60_CC_IV_43_CHECK (INTR0x60_CC_IV_43 == `$1')
2730#else
2731#define INTR0x60_CC_IV_43_CHECK (0)
2732#endif
2733
2734#ifdef INTR0x60_CC_IV_44
2735#define INTR0x60_CC_IV_44_CHECK (INTR0x60_CC_IV_44 == `$1')
2736#else
2737#define INTR0x60_CC_IV_44_CHECK (0)
2738#endif
2739
2740#ifdef INTR0x60_CC_IV_45
2741#define INTR0x60_CC_IV_45_CHECK (INTR0x60_CC_IV_45 == `$1')
2742#else
2743#define INTR0x60_CC_IV_45_CHECK (0)
2744#endif
2745
2746#ifdef INTR0x60_CC_IV_46
2747#define INTR0x60_CC_IV_46_CHECK (INTR0x60_CC_IV_46 == `$1')
2748#else
2749#define INTR0x60_CC_IV_46_CHECK (0)
2750#endif
2751
2752#ifdef INTR0x60_CC_IV_47
2753#define INTR0x60_CC_IV_47_CHECK (INTR0x60_CC_IV_47 == `$1')
2754#else
2755#define INTR0x60_CC_IV_47_CHECK (0)
2756#endif
2757
2758#ifdef INTR0x60_NIU_RX_IV_0
2759#define INTR0x60_NIU_RX_IV_0_CHECK (INTR0x60_NIU_RX_IV_0 == `$1')
2760#else
2761#define INTR0x60_NIU_RX_IV_0_CHECK (0)
2762#endif
2763
2764#ifdef INTR0x60_NIU_RX_IV_1
2765#define INTR0x60_NIU_RX_IV_1_CHECK (INTR0x60_NIU_RX_IV_1 == `$1')
2766#else
2767#define INTR0x60_NIU_RX_IV_1_CHECK (0)
2768#endif
2769
2770#ifdef INTR0x60_NIU_RX_IV_2
2771#define INTR0x60_NIU_RX_IV_2_CHECK (INTR0x60_NIU_RX_IV_2 == `$1')
2772#else
2773#define INTR0x60_NIU_RX_IV_2_CHECK (0)
2774#endif
2775
2776#ifdef INTR0x60_NIU_RX_IV_3
2777#define INTR0x60_NIU_RX_IV_3_CHECK (INTR0x60_NIU_RX_IV_3 == `$1')
2778#else
2779#define INTR0x60_NIU_RX_IV_3_CHECK (0)
2780#endif
2781
2782#ifdef INTR0x60_NIU_RX_IV_4
2783#define INTR0x60_NIU_RX_IV_4_CHECK (INTR0x60_NIU_RX_IV_4 == `$1')
2784#else
2785#define INTR0x60_NIU_RX_IV_4_CHECK (0)
2786#endif
2787
2788#ifdef INTR0x60_NIU_RX_IV_5
2789#define INTR0x60_NIU_RX_IV_5_CHECK (INTR0x60_NIU_RX_IV_5 == `$1')
2790#else
2791#define INTR0x60_NIU_RX_IV_5_CHECK (0)
2792#endif
2793
2794#ifdef INTR0x60_NIU_RX_IV_6
2795#define INTR0x60_NIU_RX_IV_6_CHECK (INTR0x60_NIU_RX_IV_6 == `$1')
2796#else
2797#define INTR0x60_NIU_RX_IV_6_CHECK (0)
2798#endif
2799
2800#ifdef INTR0x60_NIU_RX_IV_7
2801#define INTR0x60_NIU_RX_IV_7_CHECK (INTR0x60_NIU_RX_IV_7 == `$1')
2802#else
2803#define INTR0x60_NIU_RX_IV_7_CHECK (0)
2804#endif
2805
2806#ifdef INTR0x60_NIU_RX_IV_8
2807#define INTR0x60_NIU_RX_IV_8_CHECK (INTR0x60_NIU_RX_IV_8 == `$1')
2808#else
2809#define INTR0x60_NIU_RX_IV_8_CHECK (0)
2810#endif
2811
2812#ifdef INTR0x60_NIU_RX_IV_9
2813#define INTR0x60_NIU_RX_IV_9_CHECK (INTR0x60_NIU_RX_IV_9 == `$1')
2814#else
2815#define INTR0x60_NIU_RX_IV_9_CHECK (0)
2816#endif
2817
2818#ifdef INTR0x60_NIU_RX_IV_10
2819#define INTR0x60_NIU_RX_IV_10_CHECK (INTR0x60_NIU_RX_IV_10 == `$1')
2820#else
2821#define INTR0x60_NIU_RX_IV_10_CHECK (0)
2822#endif
2823
2824#ifdef INTR0x60_NIU_RX_IV_11
2825#define INTR0x60_NIU_RX_IV_11_CHECK (INTR0x60_NIU_RX_IV_11 == `$1')
2826#else
2827#define INTR0x60_NIU_RX_IV_11_CHECK (0)
2828#endif
2829
2830#ifdef INTR0x60_NIU_RX_IV_12
2831#define INTR0x60_NIU_RX_IV_12_CHECK (INTR0x60_NIU_RX_IV_12 == `$1')
2832#else
2833#define INTR0x60_NIU_RX_IV_12_CHECK (0)
2834#endif
2835
2836#ifdef INTR0x60_NIU_RX_IV_13
2837#define INTR0x60_NIU_RX_IV_13_CHECK (INTR0x60_NIU_RX_IV_13 == `$1')
2838#else
2839#define INTR0x60_NIU_RX_IV_13_CHECK (0)
2840#endif
2841
2842#ifdef INTR0x60_NIU_RX_IV_14
2843#define INTR0x60_NIU_RX_IV_14_CHECK (INTR0x60_NIU_RX_IV_14 == `$1')
2844#else
2845#define INTR0x60_NIU_RX_IV_14_CHECK (0)
2846#endif
2847
2848#ifdef INTR0x60_NIU_RX_IV_15
2849#define INTR0x60_NIU_RX_IV_15_CHECK (INTR0x60_NIU_RX_IV_15 == `$1')
2850#else
2851#define INTR0x60_NIU_RX_IV_15_CHECK (0)
2852#endif
2853
2854#ifdef INTR0x60_NIU_TX_IV_0
2855#define INTR0x60_NIU_TX_IV_0_CHECK (INTR0x60_NIU_TX_IV_0 == `$1')
2856#else
2857#define INTR0x60_NIU_TX_IV_0_CHECK (0)
2858#endif
2859
2860#ifdef INTR0x60_NIU_TX_IV_1
2861#define INTR0x60_NIU_TX_IV_1_CHECK (INTR0x60_NIU_TX_IV_1 == `$1')
2862#else
2863#define INTR0x60_NIU_TX_IV_1_CHECK (0)
2864#endif
2865
2866#ifdef INTR0x60_NIU_TX_IV_2
2867#define INTR0x60_NIU_TX_IV_2_CHECK (INTR0x60_NIU_TX_IV_2 == `$1')
2868#else
2869#define INTR0x60_NIU_TX_IV_2_CHECK (0)
2870#endif
2871
2872#ifdef INTR0x60_NIU_TX_IV_3
2873#define INTR0x60_NIU_TX_IV_3_CHECK (INTR0x60_NIU_TX_IV_3 == `$1')
2874#else
2875#define INTR0x60_NIU_TX_IV_3_CHECK (0)
2876#endif
2877
2878#ifdef INTR0x60_NIU_TX_IV_4
2879#define INTR0x60_NIU_TX_IV_4_CHECK (INTR0x60_NIU_TX_IV_4 == `$1')
2880#else
2881#define INTR0x60_NIU_TX_IV_4_CHECK (0)
2882#endif
2883
2884#ifdef INTR0x60_NIU_TX_IV_5
2885#define INTR0x60_NIU_TX_IV_5_CHECK (INTR0x60_NIU_TX_IV_5 == `$1')
2886#else
2887#define INTR0x60_NIU_TX_IV_5_CHECK (0)
2888#endif
2889
2890#ifdef INTR0x60_NIU_TX_IV_6
2891#define INTR0x60_NIU_TX_IV_6_CHECK (INTR0x60_NIU_TX_IV_6 == `$1')
2892#else
2893#define INTR0x60_NIU_TX_IV_6_CHECK (0)
2894#endif
2895
2896#ifdef INTR0x60_NIU_TX_IV_7
2897#define INTR0x60_NIU_TX_IV_7_CHECK (INTR0x60_NIU_TX_IV_7 == `$1')
2898#else
2899#define INTR0x60_NIU_TX_IV_7_CHECK (0)
2900#endif
2901
2902#ifdef INTR0x60_NIU_TX_IV_8
2903#define INTR0x60_NIU_TX_IV_8_CHECK (INTR0x60_NIU_TX_IV_8 == `$1')
2904#else
2905#define INTR0x60_NIU_TX_IV_8_CHECK (0)
2906#endif
2907
2908#ifdef INTR0x60_NIU_TX_IV_9
2909#define INTR0x60_NIU_TX_IV_9_CHECK (INTR0x60_NIU_TX_IV_9 == `$1')
2910#else
2911#define INTR0x60_NIU_TX_IV_9_CHECK (0)
2912#endif
2913
2914#ifdef INTR0x60_NIU_TX_IV_10
2915#define INTR0x60_NIU_TX_IV_10_CHECK (INTR0x60_NIU_TX_IV_10 == `$1')
2916#else
2917#define INTR0x60_NIU_TX_IV_10_CHECK (0)
2918#endif
2919
2920#ifdef INTR0x60_NIU_TX_IV_11
2921#define INTR0x60_NIU_TX_IV_11_CHECK (INTR0x60_NIU_TX_IV_11 == `$1')
2922#else
2923#define INTR0x60_NIU_TX_IV_11_CHECK (0)
2924#endif
2925
2926#ifdef INTR0x60_NIU_TX_IV_12
2927#define INTR0x60_NIU_TX_IV_12_CHECK (INTR0x60_NIU_TX_IV_12 == `$1')
2928#else
2929#define INTR0x60_NIU_TX_IV_12_CHECK (0)
2930#endif
2931
2932#ifdef INTR0x60_NIU_TX_IV_13
2933#define INTR0x60_NIU_TX_IV_13_CHECK (INTR0x60_NIU_TX_IV_13 == `$1')
2934#else
2935#define INTR0x60_NIU_TX_IV_13_CHECK (0)
2936#endif
2937
2938#ifdef INTR0x60_NIU_TX_IV_14
2939#define INTR0x60_NIU_TX_IV_14_CHECK (INTR0x60_NIU_TX_IV_14 == `$1')
2940#else
2941#define INTR0x60_NIU_TX_IV_14_CHECK (0)
2942#endif
2943
2944#ifdef INTR0x60_NIU_TX_IV_15
2945#define INTR0x60_NIU_TX_IV_15_CHECK (INTR0x60_NIU_TX_IV_15 == `$1')
2946#else
2947#define INTR0x60_NIU_TX_IV_15_CHECK (0)
2948#endif
2949
2950#if (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV)
2951#define INTR0x60_SSI_ERR_IV_CHECK (INTR0x60_SSI_ERR_IV == `$1')
2952#else
2953#define INTR0x60_SSI_ERR_IV_CHECK (0)
2954#endif
2955
2956#if (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
2957#define INTR0x60_SSI_INT_IV_CHECK (INTR0x60_SSI_INT_IV == `$1')
2958#else
2959#define INTR0x60_SSI_INT_IV_CHECK (0)
2960#endif
2961
2962#ifdef INTR0x60_MONDO_IV
2963#define INTR0x60_MONDO_IV_CHECK (INTR0x60_MONDO_IV == `$1')
2964#else
2965#define INTR0x60_MONDO_IV_CHECK (0)
2966#endif
2967
2968/* Note: Need to put INTR0x60_IG_* names on a separate line
2969 * because the *_CHECK macros may contain a half-quote which
2970 * would prevent cpp from doing the macro replacement */
2971define(`INTR0x60_IVN_TO_IG',
2972 `ifelse(eval( INTR0x60_CC_IV_0_CHECK
2973 || INTR0x60_CC_IV_1_CHECK
2974 || INTR0x60_CC_IV_2_CHECK
2975 || INTR0x60_CC_IV_3_CHECK
2976 || INTR0x60_CC_IV_4_CHECK
2977 || INTR0x60_CC_IV_5_CHECK
2978 || INTR0x60_CC_IV_6_CHECK
2979 || INTR0x60_CC_IV_7_CHECK
2980 || INTR0x60_CC_IV_8_CHECK
2981 || INTR0x60_CC_IV_9_CHECK
2982 || INTR0x60_CC_IV_10_CHECK
2983 || INTR0x60_CC_IV_11_CHECK
2984 || INTR0x60_CC_IV_12_CHECK
2985 || INTR0x60_CC_IV_13_CHECK
2986 || INTR0x60_CC_IV_14_CHECK
2987 || INTR0x60_CC_IV_15_CHECK
2988 || INTR0x60_CC_IV_16_CHECK
2989 || INTR0x60_CC_IV_17_CHECK
2990 || INTR0x60_CC_IV_18_CHECK
2991 || INTR0x60_CC_IV_19_CHECK
2992 || INTR0x60_CC_IV_20_CHECK
2993 || INTR0x60_CC_IV_21_CHECK
2994 || INTR0x60_CC_IV_22_CHECK
2995 || INTR0x60_CC_IV_23_CHECK
2996 || INTR0x60_CC_IV_24_CHECK
2997 || INTR0x60_CC_IV_25_CHECK
2998 || INTR0x60_CC_IV_26_CHECK
2999 || INTR0x60_CC_IV_27_CHECK
3000 || INTR0x60_CC_IV_28_CHECK
3001 || INTR0x60_CC_IV_29_CHECK
3002 || INTR0x60_CC_IV_30_CHECK
3003 || INTR0x60_CC_IV_31_CHECK
3004 || INTR0x60_CC_IV_32_CHECK
3005 || INTR0x60_CC_IV_33_CHECK
3006 || INTR0x60_CC_IV_34_CHECK
3007 || INTR0x60_CC_IV_35_CHECK
3008 || INTR0x60_CC_IV_36_CHECK
3009 || INTR0x60_CC_IV_37_CHECK
3010 || INTR0x60_CC_IV_38_CHECK
3011 || INTR0x60_CC_IV_39_CHECK
3012 || INTR0x60_CC_IV_40_CHECK
3013 || INTR0x60_CC_IV_41_CHECK
3014 || INTR0x60_CC_IV_42_CHECK
3015 || INTR0x60_CC_IV_43_CHECK
3016 || INTR0x60_CC_IV_44_CHECK
3017 || INTR0x60_CC_IV_45_CHECK
3018 || INTR0x60_CC_IV_46_CHECK
3019 || INTR0x60_CC_IV_47_CHECK), 1,
3020 INTR0x60_IG_CC,
3021 eval( INTR0x60_SSI_ERR_IV_CHECK ), 1,
3022 INTR0x60_IG_SSI_ERR,
3023 eval( INTR0x60_SSI_INT_IV_CHECK ), 1,
3024 INTR0x60_IG_SSI_INT,
3025 eval( INTR0x60_MONDO_IV_CHECK ), 1,
3026 INTR0x60_IG_PIU,
3027 eval( INTR0x60_NIU_RX_IV_0_CHECK
3028 || INTR0x60_NIU_RX_IV_1_CHECK
3029 || INTR0x60_NIU_RX_IV_2_CHECK
3030 || INTR0x60_NIU_RX_IV_3_CHECK
3031 || INTR0x60_NIU_RX_IV_4_CHECK
3032 || INTR0x60_NIU_RX_IV_5_CHECK
3033 || INTR0x60_NIU_RX_IV_6_CHECK
3034 || INTR0x60_NIU_RX_IV_7_CHECK
3035 || INTR0x60_NIU_RX_IV_8_CHECK
3036 || INTR0x60_NIU_RX_IV_9_CHECK
3037 || INTR0x60_NIU_RX_IV_10_CHECK
3038 || INTR0x60_NIU_RX_IV_11_CHECK
3039 || INTR0x60_NIU_RX_IV_12_CHECK
3040 || INTR0x60_NIU_RX_IV_13_CHECK
3041 || INTR0x60_NIU_RX_IV_14_CHECK
3042 || INTR0x60_NIU_RX_IV_15_CHECK), 1,
3043 INTR0x60_IG_NIU_RX,
3044 eval( INTR0x60_NIU_TX_IV_0_CHECK
3045 || INTR0x60_NIU_TX_IV_1_CHECK
3046 || INTR0x60_NIU_TX_IV_2_CHECK
3047 || INTR0x60_NIU_TX_IV_3_CHECK
3048 || INTR0x60_NIU_TX_IV_4_CHECK
3049 || INTR0x60_NIU_TX_IV_5_CHECK
3050 || INTR0x60_NIU_TX_IV_6_CHECK
3051 || INTR0x60_NIU_TX_IV_7_CHECK
3052 || INTR0x60_NIU_TX_IV_8_CHECK
3053 || INTR0x60_NIU_TX_IV_9_CHECK
3054 || INTR0x60_NIU_TX_IV_10_CHECK
3055 || INTR0x60_NIU_TX_IV_11_CHECK
3056 || INTR0x60_NIU_TX_IV_12_CHECK
3057 || INTR0x60_NIU_TX_IV_13_CHECK
3058 || INTR0x60_NIU_TX_IV_14_CHECK
3059 || INTR0x60_NIU_TX_IV_15_CHECK), 1,
3060 INTR0x60_IG_NIU_TX,
3061 INTR0x60_IG_UNUSED)'
3062 )dnl
3063
3064 .byte INTR0x60_IVN_TO_IG(0)
3065 .byte INTR0x60_IVN_TO_IG(1)
3066 .byte INTR0x60_IVN_TO_IG(2)
3067 .byte INTR0x60_IVN_TO_IG(3)
3068 .byte INTR0x60_IVN_TO_IG(4)
3069 .byte INTR0x60_IVN_TO_IG(5)
3070 .byte INTR0x60_IVN_TO_IG(6)
3071 .byte INTR0x60_IVN_TO_IG(7)
3072 .byte INTR0x60_IVN_TO_IG(8)
3073 .byte INTR0x60_IVN_TO_IG(9)
3074 .byte INTR0x60_IVN_TO_IG(10)
3075 .byte INTR0x60_IVN_TO_IG(11)
3076 .byte INTR0x60_IVN_TO_IG(12)
3077 .byte INTR0x60_IVN_TO_IG(13)
3078 .byte INTR0x60_IVN_TO_IG(14)
3079 .byte INTR0x60_IVN_TO_IG(15)
3080 .byte INTR0x60_IVN_TO_IG(16)
3081 .byte INTR0x60_IVN_TO_IG(17)
3082 .byte INTR0x60_IVN_TO_IG(18)
3083 .byte INTR0x60_IVN_TO_IG(19)
3084 .byte INTR0x60_IVN_TO_IG(20)
3085 .byte INTR0x60_IVN_TO_IG(21)
3086 .byte INTR0x60_IVN_TO_IG(22)
3087 .byte INTR0x60_IVN_TO_IG(23)
3088 .byte INTR0x60_IVN_TO_IG(24)
3089 .byte INTR0x60_IVN_TO_IG(25)
3090 .byte INTR0x60_IVN_TO_IG(26)
3091 .byte INTR0x60_IVN_TO_IG(27)
3092 .byte INTR0x60_IVN_TO_IG(28)
3093 .byte INTR0x60_IVN_TO_IG(29)
3094 .byte INTR0x60_IVN_TO_IG(30)
3095 .byte INTR0x60_IVN_TO_IG(31)
3096 .byte INTR0x60_IVN_TO_IG(32)
3097 .byte INTR0x60_IVN_TO_IG(33)
3098 .byte INTR0x60_IVN_TO_IG(34)
3099 .byte INTR0x60_IVN_TO_IG(35)
3100 .byte INTR0x60_IVN_TO_IG(36)
3101 .byte INTR0x60_IVN_TO_IG(37)
3102 .byte INTR0x60_IVN_TO_IG(38)
3103 .byte INTR0x60_IVN_TO_IG(39)
3104 .byte INTR0x60_IVN_TO_IG(40)
3105 .byte INTR0x60_IVN_TO_IG(41)
3106 .byte INTR0x60_IVN_TO_IG(42)
3107 .byte INTR0x60_IVN_TO_IG(43)
3108 .byte INTR0x60_IVN_TO_IG(44)
3109 .byte INTR0x60_IVN_TO_IG(45)
3110 .byte INTR0x60_IVN_TO_IG(46)
3111 .byte INTR0x60_IVN_TO_IG(47)
3112 .byte INTR0x60_IVN_TO_IG(48)
3113 .byte INTR0x60_IVN_TO_IG(49)
3114 .byte INTR0x60_IVN_TO_IG(50)
3115 .byte INTR0x60_IVN_TO_IG(51)
3116 .byte INTR0x60_IVN_TO_IG(52)
3117 .byte INTR0x60_IVN_TO_IG(53)
3118 .byte INTR0x60_IVN_TO_IG(54)
3119 .byte INTR0x60_IVN_TO_IG(55)
3120 .byte INTR0x60_IVN_TO_IG(56)
3121 .byte INTR0x60_IVN_TO_IG(57)
3122 .byte INTR0x60_IVN_TO_IG(58)
3123 .byte INTR0x60_IVN_TO_IG(59)
3124 .byte INTR0x60_IVN_TO_IG(60)
3125 .byte INTR0x60_IVN_TO_IG(61)
3126 .byte INTR0x60_IVN_TO_IG(62)
3127 .byte INTR0x60_IVN_TO_IG(63)
3128undefine(`INTR0x60_IVN_TO_IG')dnl
Full OpenSPARC design & verification tarball including full HDL.