projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / mmu_hptrap.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: mmu_hptrap.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38SECTION .HTRAPS TEXT_VA=HPTRAP_TEXT_PA
39
40attr_text {
41 Name = .HTRAPS,
42 hypervisor,
43 }
44
45 ta HP_BAD_TRAP
46.align 32 /* 1 */
47 ta HP_BAD_TRAP
48.align 32 /* 2 */
49 ta HP_BAD_TRAP
50.align 32 /* 3 */
51 ta HP_BAD_TRAP
52.align 32 /* 4 */
53 ta HP_BAD_TRAP
54.align 32 /* 5 */
55 ta HP_BAD_TRAP
56.align 32 /* 6 */
57 ta HP_BAD_TRAP
58.align 32 /* 7 */
59 ta HP_BAD_TRAP
60.align 32 /* 8 */
61#ifdef MMU247
62 setx ext_trap_0x8_begin, %g1, %g2
63 jmp %g2
64 nop
65#else
66 ta HP_BAD_TRAP
67#endif
68.align 32 /* 9 */
69#ifdef CUSTOM_TRAP_0X9
70 setx custom_trap_0x9_handler, %g1, %g2
71 jmp %g2
72 nop
73#else
74#ifdef MMU247
75 setx ext_trap_0x9_begin, %g1, %g2
76 jmp %g2
77 nop
78#else
79 ta HP_BAD_TRAP
80#endif
81#endif
82.align 32 /* a */
83 ta HP_BAD_TRAP
84.align 32 /* b */
85#ifdef MMU247
86 setx ext_trap_0x8_begin, %g1, %g2
87 jmp %g2
88 nop
89#else
90 ta HP_BAD_TRAP
91#endif
92.align 32 /* c */
93IAE_NFO_page:
94#ifdef CUSTOM_TRAP_0XC
95 setx custom_trap_0xc_handler, %g1, %g2
96 jmp %g2
97 nop
98#else
99 ta HP_BAD_TRAP
100#endif
101.align 32 /* d */
102Instruction_address_range:
103#ifdef MMU247
104 setx ext_trap_0x8_begin, %g1, %g2
105 jmp %g2
106 nop
107#else
108 ta HP_BAD_TRAP
109#endif
110.align 32 /* e */
111Instruction_real_range:
112#ifdef CUSTOM_TRAP_0XE
113 setx custom_trap_0xe_handler, %g1, %g2
114 jmp %g2
115 nop
116#else
117 ta HP_BAD_TRAP
118#endif
119.align 32 /* f */
120 ta HP_BAD_TRAP
121.align 32 /* 10 */
122Illegal_instruction:
123#ifdef MMU247
124 setx ext_trap_0x8_begin, %g1, %g2
125 jmp %g2
126 nop
127#else
128 ta HP_BAD_TRAP
129#endif
130.align 32 /* 11 */
131 ta HP_BAD_TRAP
132.align 32 /* 12 */
133 ta HP_BAD_TRAP
134.align 32 /* 13 */
135 ta HP_BAD_TRAP
136.align 32 /* 14 */
137DAE_Invalid_ASI:
138 or %g0, 0x20, %g1
139 ldxa [%g1] 0x54, %g2 ! DSFAR
140 done
141.align 32 /* 15 */
142DAE_privilege_violation:
143 or %g0, 0x20, %g1
144 ldxa [%g1] 0x54, %g2 ! DSFAR
145 done
146.align 32 /* 16 */
147DAE_nc_page:
148 or %g0, 0x20, %g1
149 ldxa [%g1] 0x54, %g2 ! DSFAR
150 done
151.align 32 /* 17 */
152DAE_NFO_page:
153 or %g0, 0x20, %g1
154 ldxa [%g1] 0x54, %g2 ! DSFAR
155 done
156.align 32 /* 18 */
157 ta HP_BAD_TRAP
158.align 32 /* 19 */
159 ta HP_BAD_TRAP
160.align 32 /* 1a */
161 ta HP_BAD_TRAP
162.align 32 /* 1b */
163#ifdef MMU247
164 setx ext_trap_0x1b_begin, %g1, %g2
165 jmp %g2
166 nop
167#else
168 ta HP_BAD_TRAP
169#endif
170.align 32 /* 1c */
171 ta HP_BAD_TRAP
172.align 32 /* 1d */
173 ta HP_BAD_TRAP
174.align 32 /* 1e */
175 ta HP_BAD_TRAP
176.align 32 /* 1f */
177 ta HP_BAD_TRAP
178.align 32 /* 20 */
179 ta HP_BAD_TRAP
180.align 32 /* 21 */
181 ta HP_BAD_TRAP
182.align 32 /* 22 */
183 ta HP_BAD_TRAP
184.align 32 /* 23 */
185 ta HP_BAD_TRAP
186.align 32 /* 24 */
187 ta HP_BAD_TRAP
188.align 32 /* 25 */
189 ta HP_BAD_TRAP
190.align 32 /* 26 */
191 ta HP_BAD_TRAP
192.align 32 /* 27 */
193 ta HP_BAD_TRAP
194.align 32 /* 28 */
195 ta HP_BAD_TRAP
196.align 32 /* 29 */
197 ta HP_BAD_TRAP
198.align 32 /* 2a */
199#ifdef CUSTOM_TRAP_0X2A
200 setx custom_trap_0x2a_handler, %g1, %g2
201 jmp %g2
202 nop
203#else
204 setx ext_trap_0x2a_begin, %g1, %g2
205 jmp %g2
206 nop
207#endif
208.align 32 /* 2b */
209#ifdef CUSTOM_TRAP_0X2B
210 setx custom_trap_0x2b_handler, %g1, %g2
211 jmp %g2
212 nop
213#else
214 setx ext_trap_0x2b_begin, %g1, %g2
215 jmp %g2
216 nop
217#endif
218.align 32 /* 2c */
219 ta HP_BAD_TRAP
220.align 32 /* 2d */
221mem_real_range:
222#ifdef CUSTOM_TRAP_0X2D
223 setx custom_trap_0x2d_handler, %g1, %g2
224 jmp %g2
225 nop
226#else
227#ifdef MMU247
228 done
229#else
230 ta HP_BAD_TRAP
231#endif
232#endif
233.align 32 /* 2e */
234#ifdef MMU247
235 done
236#else
237 ta HP_BAD_TRAP
238#endif
239.align 32 /* 2f */
240 ta HP_BAD_TRAP
241.align 32 /* 30 */
242DAE_so_page:
243 or %g0, 0x20, %g1
244 ldxa [%g1] 0x54, %g2 ! DSFAR
245 done
246.align 32 /* 31 */
247#ifdef CUSTOM_TRAP_0X31
248 setx custom_trap_0x31_handler, %g1, %g2
249 jmp %g2
250 nop
251#else
252#ifdef MMU247
253 setx ext_trap_0x31_begin, %g1, %g2
254 jmp %g2
255 nop
256#else
257 ta HP_BAD_TRAP
258#endif
259#endif
260.align 32 /* 32 */
261 ta HP_BAD_TRAP
262.align 32 /* 33 */
263 ta HP_BAD_TRAP
264.align 32 /* 34 */
265mem_address_not_aligned:
266 or %g0, 0x20, %g1
267 ldxa [%g1] 0x54, %g2 ! DSFAR
268 done
269.align 32 /* 35 */
270LDDF_mem_address_not_aligned:
271 or %g0, 0x20, %g1
272 ldxa [%g1] 0x54, %g2 ! DSFAR
273 done
274.align 32 /* 36 */
275STDF_mem_address_not_aligned:
276 or %g0, 0x20, %g1
277 ldxa [%g1] 0x54, %g2 ! DSFAR
278 done
279.align 32 /* 37 */
280privileged_action:
281 or %g0, 0x20, %g1
282 ldxa [%g1] 0x54, %g2 ! DSFAR
283 done
284.align 32 /* 38 */
285LDQF_mem_address_not_aligned:
286 or %g0, 0x20, %g1
287 ldxa [%g1] 0x54, %g2 ! DSFAR
288 done
289.align 32 /* 39 */
290STQF_mem_address_not_aligned:
291 or %g0, 0x20, %g1
292 ldxa [%g1] 0x54, %g2 ! DSFAR
293 done
294.align 32 /* 3a */
295 ta HP_BAD_TRAP
296.align 32 /* 3b */
297unsupported_page_size:
298 or %g0, 0x20, %g1
299 ldxa [%g1] 0x54, %g2 ! DSFAR
300 done
301.align 32 /* 3c */
302 ta HP_BAD_TRAP
303.align 32 /* 3d */
304 ta HP_BAD_TRAP
305.align 32 /* 3e */
306instruction_real_miss:
307#ifdef CUSTOM_TRAP_0X3E
308 ta HP_BAD_TRAP
309#else
310 setx ext_trap_0x3e_begin, %g1, %g2
311 jmp %g2
312 nop
313#endif
314.align 32 /* 3f */
315data_real_miss:
316#ifdef CUSTOM_TRAP_0X3F
317 ta HP_BAD_TRAP
318#else
319 setx ext_trap_0x3f_begin, %g1, %g2
320 jmp %g2
321 nop
322#endif
323.align 32 /* 40 */
324 ta HP_BAD_TRAP
325.align 32 /* 41 */
326 ta HP_BAD_TRAP
327.align 32 /* 42 */
328 ta HP_BAD_TRAP
329.align 32 /* 43 */
330 ta HP_BAD_TRAP
331.align 32 /* 44 */
332 ta HP_BAD_TRAP
333.align 32 /* 45 */
334 ta HP_BAD_TRAP
335.align 32 /* 46 */
336 ta HP_BAD_TRAP
337.align 32 /* 47 */
338 ta HP_BAD_TRAP
339.align 32 /* 48 */
340 ta HP_BAD_TRAP
341.align 32 /* 49 */
342 ta HP_BAD_TRAP
343.align 32 /* 4a */
344 ta HP_BAD_TRAP
345.align 32 /* 4b */
346 ta HP_BAD_TRAP
347.align 32 /* 4c */
348 ta HP_BAD_TRAP
349.align 32 /* 4d */
350 ta HP_BAD_TRAP
351.align 32 /* 4e */
352 ta HP_BAD_TRAP
353.align 32 /* 4f */
354 ta HP_BAD_TRAP
355.align 32 /* 50 */
356 ta HP_BAD_TRAP
357.align 32 /* 51 */
358 ta HP_BAD_TRAP
359.align 32 /* 52 */
360 ta HP_BAD_TRAP
361.align 32 /* 53 */
362 ta HP_BAD_TRAP
363.align 32 /* 54 */
364 ta HP_BAD_TRAP
365.align 32 /* 55 */
366 ta HP_BAD_TRAP
367.align 32 /* 56 */
368 ta HP_BAD_TRAP
369.align 32 /* 57 */
370 ta HP_BAD_TRAP
371.align 32 /* 58 */
372 ta HP_BAD_TRAP
373.align 32 /* 59 */
374 ta HP_BAD_TRAP
375.align 32 /* 5a */
376 ta HP_BAD_TRAP
377.align 32 /* 5b */
378 ta HP_BAD_TRAP
379.align 32 /* 5c */
380 ta HP_BAD_TRAP
381.align 32 /* 5d */
382 ta HP_BAD_TRAP
383.align 32 /* 5e */
384 ta HP_BAD_TRAP
385.align 32 /* 5f */
386 ta HP_BAD_TRAP
387.align 32 /* 60 */
388 ta HP_BAD_TRAP
389.align 32 /* 61 */
390PA_watchpoint:
391 or %g0, 0x20, %g1
392 ldxa [%g1] 0x54, %g2 ! DSFAR
393 done
394.align 32 /* 62 */
395VA_watchpoint:
396 or %g0, 0x20, %g1
397 ldxa [%g1] 0x54, %g2 ! DSFAR
398 done
399.align 32 /* 63 */
400 ta HP_BAD_TRAP
401.align 32 /* 64 */
402#ifdef CUSTOM_TRAP_0X64
403 setx custom_trap_0x64_handler, %g1, %g2
404 jmp %g2
405 nop
406#else
407 setx ext_trap_0x64_begin, %g1, %g2
408 jmp %g2
409 nop
410#endif
411.align 32 /* 65 */
412 ta HP_BAD_TRAP
413.align 32 /* 66 */
414 ta HP_BAD_TRAP
415.align 32 /* 67 */
416 ta HP_BAD_TRAP
417.align 32 /* 68 */
418#ifdef CUSTOM_TRAP_0X68
419 setx custom_trap_0x68_handler, %g1, %g2
420 jmp %g2
421 nop
422#else
423 setx ext_trap_0x68_begin, %g1, %g2
424 jmp %g2
425 nop
426#endif
427.align 32 /* 69 */
428 ta HP_BAD_TRAP
429.align 32 /* 6a */
430 ta HP_BAD_TRAP
431.align 32 /* 6b */
432 ta HP_BAD_TRAP
433.align 32 /* 6c */
434fast_data_access_protection:
435#ifdef MMU247
436 or %g0, 0x20, %g1
437 ldxa [%g1] 0x54, %g2 ! DSFAR
438 done
439#else
440 ta HP_BAD_TRAP
441#endif
442.align 32 /* 6d */
443 ta HP_BAD_TRAP
444.align 32 /* 6e */
445 ta HP_BAD_TRAP
446.align 32 /* 6f */
447 ta HP_BAD_TRAP
448.align 32 /* 70 */
449 ta HP_BAD_TRAP
450.align 32 /* 71 */
451itlb_multiple_hit:
452#ifdef CUSTOM_TRAP_0X71
453 setx custom_trap_0x71_handler, %g1, %g2
454 jmp %g2
455 nop
456#else
457 ta HP_BAD_TRAP
458#endif
459.align 32 /* 72 */
460dtlb_multiple_hit:
461#ifdef CUSTOM_TRAP_0X72
462 setx custom_trap_0x72_handler, %g1, %g2
463 jmp %g2
464 nop
465#else
466 ta HP_BAD_TRAP
467#endif
468.align 32 /* 73 */
469 ta HP_BAD_TRAP
470.align 32 /* 74 */
471 ta HP_BAD_TRAP
472.align 32 /* 75 */
473instruction_VA_watchpoint:
474 or %g0, 0x20, %g1
475 ldxa [%g1] 0x54, %g2 ! DSFAR
476 done
477.align 32 /* 76 */
478 ta HP_BAD_TRAP
479.align 32 /* 77 */
480 ta HP_BAD_TRAP
481.align 32 /* 78 */
482 ta HP_BAD_TRAP
483.align 32 /* 79 */
484 ta HP_BAD_TRAP
485.align 32 /* 7a */
486 ta HP_BAD_TRAP
487.align 32 /* 7b */
488 ta HP_BAD_TRAP
489.align 32 /* 7c */
490 ta HP_BAD_TRAP
491.align 32 /* 7d */
492 ta HP_BAD_TRAP
493.align 32 /* 7e */
494 ta HP_BAD_TRAP
495.align 32 /* 7f */
496 ta HP_BAD_TRAP
497.align 32 /* 80 */
498Spill_n_normal:
499#ifdef MMU247 wrpr 1, %tl !Comment out for now..because handler is too big.
500! Why do we need it????/
501 setx ext_trap_0x8_begin, %g1, %g2
502 jmp %g2
503 nop
504 ta HP_BAD_TRAP ! This is for trap 81, since this one is 1 instruction too long
505#else
506 ta HP_BAD_TRAP
507.align 32
508 ta HP_BAD_TRAP
509#endif
510! Comment out 1 align since the previous trap handler is one instruction too long
511!.align 32 /* 81 */
512! ta HP_BAD_TRAP
513.align 32 /* 82 */
514 ta HP_BAD_TRAP
515.align 32 /* 83 */
516 ta HP_BAD_TRAP
517.align 32 /* 84 */
518 ta HP_BAD_TRAP
519.align 32 /* 85 */
520 ta HP_BAD_TRAP
521.align 32 /* 86 */
522 ta HP_BAD_TRAP
523.align 32 /* 87 */
524 ta HP_BAD_TRAP
525.align 32 /* 88 */
526 ta HP_BAD_TRAP
527.align 32 /* 89 */
528 ta HP_BAD_TRAP
529.align 32 /* 8a */
530 ta HP_BAD_TRAP
531.align 32 /* 8b */
532 ta HP_BAD_TRAP
533.align 32 /* 8c */
534 ta HP_BAD_TRAP
535.align 32 /* 8d */
536 ta HP_BAD_TRAP
537.align 32 /* 8e */
538 ta HP_BAD_TRAP
539.align 32 /* 8f */
540 ta HP_BAD_TRAP
541.align 32 /* 90 */
542 ta HP_BAD_TRAP
543.align 32 /* 91 */
544 ta HP_BAD_TRAP
545.align 32 /* 92 */
546 ta HP_BAD_TRAP
547.align 32 /* 93 */
548 ta HP_BAD_TRAP
549.align 32 /* 94 */
550 ta HP_BAD_TRAP
551.align 32 /* 95 */
552 ta HP_BAD_TRAP
553.align 32 /* 96 */
554 ta HP_BAD_TRAP
555.align 32 /* 97 */
556 ta HP_BAD_TRAP
557.align 32 /* 98 */
558 ta HP_BAD_TRAP
559.align 32 /* 99 */
560 ta HP_BAD_TRAP
561.align 32 /* 9a */
562 ta HP_BAD_TRAP
563.align 32 /* 9b */
564 ta HP_BAD_TRAP
565.align 32 /* 9c */
566 ta HP_BAD_TRAP
567.align 32 /* 9d */
568 ta HP_BAD_TRAP
569.align 32 /* 9e */
570 ta HP_BAD_TRAP
571.align 32 /* 9f */
572 ta HP_BAD_TRAP
573.align 32 /* a0 */
574 ta HP_BAD_TRAP
575.align 32 /* a1 */
576 ta HP_BAD_TRAP
577.align 32 /* a2 */
578 ta HP_BAD_TRAP
579.align 32 /* a3 */
580 ta HP_BAD_TRAP
581.align 32 /* a4 */
582 ta HP_BAD_TRAP
583.align 32 /* a5 */
584 ta HP_BAD_TRAP
585.align 32 /* a6 */
586 ta HP_BAD_TRAP
587.align 32 /* a7 */
588 ta HP_BAD_TRAP
589.align 32 /* a8 */
590 ta HP_BAD_TRAP
591.align 32 /* a9 */
592 ta HP_BAD_TRAP
593.align 32 /* aa */
594 ta HP_BAD_TRAP
595.align 32 /* ab */
596 ta HP_BAD_TRAP
597.align 32 /* ac */
598 ta HP_BAD_TRAP
599.align 32 /* ad */
600 ta HP_BAD_TRAP
601.align 32 /* ae */
602 ta HP_BAD_TRAP
603.align 32 /* af */
604 ta HP_BAD_TRAP
605.align 32 /* b0 */
606 ta HP_BAD_TRAP
607.align 32 /* b1 */
608 ta HP_BAD_TRAP
609.align 32 /* b2 */
610 ta HP_BAD_TRAP
611.align 32 /* b3 */
612 ta HP_BAD_TRAP
613.align 32 /* b4 */
614 ta HP_BAD_TRAP
615.align 32 /* b5 */
616 ta HP_BAD_TRAP
617.align 32 /* b6 */
618 ta HP_BAD_TRAP
619.align 32 /* b7 */
620 ta HP_BAD_TRAP
621.align 32 /* b8 */
622 ta HP_BAD_TRAP
623.align 32 /* b9 */
624 ta HP_BAD_TRAP
625.align 32 /* ba */
626 ta HP_BAD_TRAP
627.align 32 /* bb */
628 ta HP_BAD_TRAP
629.align 32 /* bc */
630 ta HP_BAD_TRAP
631.align 32 /* bd */
632 ta HP_BAD_TRAP
633.align 32 /* be */
634 ta HP_BAD_TRAP
635.align 32 /* bf */
636 ta HP_BAD_TRAP
637.align 32 /* c0 */
638 ta HP_BAD_TRAP
639.align 32 /* c1 */
640 ta HP_BAD_TRAP
641.align 32 /* c2 */
642 ta HP_BAD_TRAP
643.align 32 /* c3 */
644 ta HP_BAD_TRAP
645.align 32 /* c4 */
646 ta HP_BAD_TRAP
647.align 32 /* c5 */
648 ta HP_BAD_TRAP
649.align 32 /* c6 */
650 ta HP_BAD_TRAP
651.align 32 /* c7 */
652 ta HP_BAD_TRAP
653.align 32 /* c8 */
654 ta HP_BAD_TRAP
655.align 32 /* c9 */
656 ta HP_BAD_TRAP
657.align 32 /* ca */
658 ta HP_BAD_TRAP
659.align 32 /* cb */
660 ta HP_BAD_TRAP
661.align 32 /* cc */
662 ta HP_BAD_TRAP
663.align 32 /* cd */
664 ta HP_BAD_TRAP
665.align 32 /* ce */
666 ta HP_BAD_TRAP
667.align 32 /* cf */
668 ta HP_BAD_TRAP
669.align 32 /* d0 */
670 ta HP_BAD_TRAP
671.align 32 /* d1 */
672 ta HP_BAD_TRAP
673.align 32 /* d2 */
674 ta HP_BAD_TRAP
675.align 32 /* d3 */
676 ta HP_BAD_TRAP
677.align 32 /* d4 */
678 ta HP_BAD_TRAP
679.align 32 /* d5 */
680 ta HP_BAD_TRAP
681.align 32 /* d6 */
682 ta HP_BAD_TRAP
683.align 32 /* d7 */
684 ta HP_BAD_TRAP
685.align 32 /* d8 */
686 ta HP_BAD_TRAP
687.align 32 /* d9 */
688 ta HP_BAD_TRAP
689.align 32 /* da */
690 ta HP_BAD_TRAP
691.align 32 /* db */
692 ta HP_BAD_TRAP
693.align 32 /* dc */
694 ta HP_BAD_TRAP
695.align 32 /* dd */
696 ta HP_BAD_TRAP
697.align 32 /* de */
698 ta HP_BAD_TRAP
699.align 32 /* df */
700 ta HP_BAD_TRAP
701.align 32 /* e0 */
702 ta HP_BAD_TRAP
703.align 32 /* e1 */
704 ta HP_BAD_TRAP
705.align 32 /* e2 */
706 ta HP_BAD_TRAP
707.align 32 /* e3 */
708 ta HP_BAD_TRAP
709.align 32 /* e4 */
710 ta HP_BAD_TRAP
711.align 32 /* e5 */
712 ta HP_BAD_TRAP
713.align 32 /* e6 */
714 ta HP_BAD_TRAP
715.align 32 /* e7 */
716 ta HP_BAD_TRAP
717.align 32 /* e8 */
718 ta HP_BAD_TRAP
719.align 32 /* e9 */
720 ta HP_BAD_TRAP
721.align 32 /* ea */
722 ta HP_BAD_TRAP
723.align 32 /* eb */
724 ta HP_BAD_TRAP
725.align 32 /* ec */
726 ta HP_BAD_TRAP
727.align 32 /* ed */
728 ta HP_BAD_TRAP
729.align 32 /* ee */
730 ta HP_BAD_TRAP
731.align 32 /* ef */
732 ta HP_BAD_TRAP
733.align 32 /* f0 */
734 ta HP_BAD_TRAP
735.align 32 /* f1 */
736 ta HP_BAD_TRAP
737.align 32 /* f2 */
738 ta HP_BAD_TRAP
739.align 32 /* f3 */
740 ta HP_BAD_TRAP
741.align 32 /* f4 */
742 ta HP_BAD_TRAP
743.align 32 /* f5 */
744 ta HP_BAD_TRAP
745.align 32 /* f6 */
746 ta HP_BAD_TRAP
747.align 32 /* f7 */
748 ta HP_BAD_TRAP
749.align 32 /* f8 */
750 ta HP_BAD_TRAP
751.align 32 /* f9 */
752 ta HP_BAD_TRAP
753.align 32 /* fa */
754 ta HP_BAD_TRAP
755.align 32 /* fb */
756 ta HP_BAD_TRAP
757.align 32 /* fc */
758 ta HP_BAD_TRAP
759.align 32 /* fd */
760 ta HP_BAD_TRAP
761.align 32 /* fe */
762 ta HP_BAD_TRAP
763.align 32 /* ff */
764 ta HP_BAD_TRAP
765.align 32 /* 100 */
766 wrpr 0, %tl
767 ta HP_GOOD_TRAP
768.align 32 /* 101 */
769 wrpr 0, %tl
770 ta HP_BAD_TRAP
771.align 32 /* 102 */
772 ta HP_BAD_TRAP
773.align 32 /* 103 */
774 ta HP_BAD_TRAP
775.align 32 /* 104 */
776 ta HP_BAD_TRAP
777.align 32 /* 105 */
778 ta HP_BAD_TRAP
779.align 32 /* 106 */
780 ta HP_BAD_TRAP
781.align 32 /* 107 */
782 ta HP_BAD_TRAP
783.align 32 /* 108 */
784 ta HP_BAD_TRAP
785.align 32 /* 109 */
786 ta HP_BAD_TRAP
787.align 32 /* 10a */
788 ta HP_BAD_TRAP
789.align 32 /* 10b */
790 ta HP_BAD_TRAP
791.align 32 /* 10c */
792 ta HP_BAD_TRAP
793.align 32 /* 10d */
794 ta HP_BAD_TRAP
795.align 32 /* 10e */
796 ta HP_BAD_TRAP
797.align 32 /* 10f */
798 ta HP_BAD_TRAP
799.align 32 /* 110 */
800 ta HP_BAD_TRAP
801.align 32 /* 111 */
802 ta HP_BAD_TRAP
803.align 32 /* 112 */
804 ta HP_BAD_TRAP
805.align 32 /* 113 */
806 ta HP_BAD_TRAP
807.align 32 /* 114 */
808 ta HP_BAD_TRAP
809.align 32 /* 115 */
810 ta HP_BAD_TRAP
811.align 32 /* 116 */
812 ta HP_BAD_TRAP
813.align 32 /* 117 */
814 ta HP_BAD_TRAP
815.align 32 /* 118 */
816 ta HP_BAD_TRAP
817.align 32 /* 119 */
818 ta HP_BAD_TRAP
819.align 32 /* 11a */
820 ta HP_BAD_TRAP
821.align 32 /* 11b */
822 ta HP_BAD_TRAP
823.align 32 /* 11c */
824 ta HP_BAD_TRAP
825.align 32 /* 11d */
826 ta HP_BAD_TRAP
827.align 32 /* 11e */
828 ta HP_BAD_TRAP
829.align 32 /* 11f */
830 ta HP_BAD_TRAP
831.align 32 /* 120 */
832 ta HP_BAD_TRAP
833.align 32 /* 121 */
834 ta HP_BAD_TRAP
835.align 32 /* 122 */
836 ta HP_BAD_TRAP
837.align 32 /* 123 */
838 ta HP_BAD_TRAP
839.align 32 /* 124 */
840 ta HP_BAD_TRAP
841.align 32 /* 125 */
842 ta HP_BAD_TRAP
843.align 32 /* 126 */
844 ta HP_BAD_TRAP
845.align 32 /* 127 */
846 ta HP_BAD_TRAP
847.align 32 /* 128 */
848 ta HP_BAD_TRAP
849.align 32 /* 129 */
850 ta HP_BAD_TRAP
851.align 32 /* 12a */
852 ta HP_BAD_TRAP
853.align 32 /* 12b */
854 ta HP_BAD_TRAP
855.align 32 /* 12c */
856 ta HP_BAD_TRAP
857.align 32 /* 12d */
858 ta HP_BAD_TRAP
859.align 32 /* 12e */
860 ta HP_BAD_TRAP
861.align 32 /* 12f */
862 ta HP_BAD_TRAP
863.align 32 /* 130 */
864 ta HP_BAD_TRAP
865.align 32 /* 131 */
866 ta HP_BAD_TRAP
867.align 32 /* 132 */
868 ta HP_BAD_TRAP
869.align 32 /* 133 */
870 ta HP_BAD_TRAP
871.align 32 /* 134 */
872 ta HP_BAD_TRAP
873.align 32 /* 135 */
874 ta HP_BAD_TRAP
875.align 32 /* 136 */
876 ta HP_BAD_TRAP
877.align 32 /* 137 */
878 ta HP_BAD_TRAP
879.align 32 /* 138 */
880 ta HP_BAD_TRAP
881.align 32 /* 139 */
882 ta HP_BAD_TRAP
883.align 32 /* 13a */
884 ta HP_BAD_TRAP
885.align 32 /* 13b */
886 ta HP_BAD_TRAP
887.align 32 /* 13c */
888 ta HP_BAD_TRAP
889.align 32 /* 13d */
890 ta HP_BAD_TRAP
891.align 32 /* 13e */
892 ta HP_BAD_TRAP
893.align 32 /* 13f */
894 ta HP_BAD_TRAP
895.align 32 /* 140 */
896 ta HP_BAD_TRAP
897.align 32 /* 141 */
898 ta HP_BAD_TRAP
899.align 32 /* 142 */
900 ta HP_BAD_TRAP
901.align 32 /* 143 */
902 ta HP_BAD_TRAP
903.align 32 /* 144 */
904 ta HP_BAD_TRAP
905.align 32 /* 145 */
906 ta HP_BAD_TRAP
907.align 32 /* 146 */
908 ta HP_BAD_TRAP
909.align 32 /* 147 */
910 ta HP_BAD_TRAP
911.align 32 /* 148 */
912 ta HP_BAD_TRAP
913.align 32 /* 149 */
914 ta HP_BAD_TRAP
915.align 32 /* 14a */
916 ta HP_BAD_TRAP
917.align 32 /* 14b */
918 ta HP_BAD_TRAP
919.align 32 /* 14c */
920 ta HP_BAD_TRAP
921.align 32 /* 14d */
922 ta HP_BAD_TRAP
923.align 32 /* 14e */
924 ta HP_BAD_TRAP
925.align 32 /* 14f */
926 ta HP_BAD_TRAP
927.align 32 /* 150 */
928 ta HP_BAD_TRAP
929.align 32 /* 151 */
930 ta HP_BAD_TRAP
931.align 32 /* 152 */
932 ta HP_BAD_TRAP
933.align 32 /* 153 */
934 ta HP_BAD_TRAP
935.align 32 /* 154 */
936 ta HP_BAD_TRAP
937.align 32 /* 155 */
938 ta HP_BAD_TRAP
939.align 32 /* 156 */
940 ta HP_BAD_TRAP
941.align 32 /* 157 */
942 ta HP_BAD_TRAP
943.align 32 /* 158 */
944 ta HP_BAD_TRAP
945.align 32 /* 159 */
946 ta HP_BAD_TRAP
947.align 32 /* 15a */
948 ta HP_BAD_TRAP
949.align 32 /* 15b */
950 ta HP_BAD_TRAP
951.align 32 /* 15c */
952 ta HP_BAD_TRAP
953.align 32 /* 15d */
954 ta HP_BAD_TRAP
955.align 32 /* 15e */
956 ta HP_BAD_TRAP
957.align 32 /* 15f */
958 ta HP_BAD_TRAP
959.align 32 /* 160 */
960 ta HP_BAD_TRAP
961.align 32 /* 161 */
962 ta HP_BAD_TRAP
963.align 32 /* 162 */
964 ta HP_BAD_TRAP
965.align 32 /* 163 */
966 ta HP_BAD_TRAP
967.align 32 /* 164 */
968 ta HP_BAD_TRAP
969.align 32 /* 165 */
970 ta HP_BAD_TRAP
971.align 32 /* 166 */
972 ta HP_BAD_TRAP
973.align 32 /* 167 */
974 ta HP_BAD_TRAP
975.align 32 /* 168 */
976 ta HP_BAD_TRAP
977.align 32 /* 169 */
978 ta HP_BAD_TRAP
979.align 32 /* 16a */
980 ta HP_BAD_TRAP
981.align 32 /* 16b */
982 ta HP_BAD_TRAP
983.align 32 /* 16c */
984 ta HP_BAD_TRAP
985.align 32 /* 16d */
986 ta HP_BAD_TRAP
987.align 32 /* 16e */
988 ta HP_BAD_TRAP
989.align 32 /* 16f */
990 ta HP_BAD_TRAP
991.align 32 /* 170 */
992 ta HP_BAD_TRAP
993.align 32 /* 171 */
994 ta HP_BAD_TRAP
995.align 32 /* 172 */
996 ta HP_BAD_TRAP
997.align 32 /* 173 */
998 ta HP_BAD_TRAP
999.align 32 /* 174 */
1000 ta HP_BAD_TRAP
1001.align 32 /* 175 */
1002 ta HP_BAD_TRAP
1003.align 32 /* 176 */
1004 ta HP_BAD_TRAP
1005.align 32 /* 177 */
1006 ta HP_BAD_TRAP
1007.align 32 /* 178 */
1008 ta HP_BAD_TRAP
1009.align 32 /* 179 */
1010 ta HP_BAD_TRAP
1011.align 32 /* 17a */
1012 ta HP_BAD_TRAP
1013.align 32 /* 17b */
1014 ta HP_BAD_TRAP
1015.align 32 /* 17c */
1016 ta HP_BAD_TRAP
1017.align 32 /* 17d */
1018 ta HP_BAD_TRAP
1019.align 32 /* 17e */
1020 ta HP_BAD_TRAP
1021.align 32 /* 17f */
1022 ta HP_BAD_TRAP
1023.align 32 /* 180 */
1024 ! For all demaps, assume register %i7 = {VA[63:13],13'h0}
1025hptrap_I_demap_all:
1026 or 0x80, %g0, %g1
1027 stxa %g0, [%g1] ASI_IMMU_DEMAP
1028 done
1029.align 32 /* 181 */
1030hptrap_I_demap_pctx:
1031 or 0x40, %g0, %g1
1032 stxa %g0, [%g1] ASI_IMMU_DEMAP
1033 done
1034.align 32 /* 182 */
1035 ta HP_BAD_TRAP
1036.align 32 /* 183 */
1037hptrap_I_demap_nctx:
1038 or 0x60, %g0, %g1
1039 stxa %g0, [%g1] ASI_IMMU_DEMAP
1040 done
1041.align 32 /* 184 */
1042hptrap_I_demap_page:
1043 andn %i7, 0x0c7, %g1
1044 stxa %g0, [%g1] ASI_IMMU_DEMAP
1045 done
1046.align 32 /* 185 */
1047hptrap_I_demap_rpage:
1048 or 0x400, %i7, %g1
1049 andn %g1, 0x0c7, %g1
1050 stxa %g0, [%g1] ASI_IMMU_DEMAP
1051 done
1052.align 32 /* 186 */
1053 ta HP_BAD_TRAP
1054.align 32 /* 187 */
1055hptrap_D_demap_all:
1056 or 0x80, %g0, %g1
1057 stxa %g0, [%g1] ASI_DMMU_DEMAP
1058 done
1059.align 32 /* 188 */
1060hptrap_D_demap_pctx:
1061 or 0x40, %g0, %g1
1062 stxa %g0, [%g1] ASI_DMMU_DEMAP
1063 done
1064.align 32 /* 189 */
1065hptrap_D_demap_sctx:
1066 or 0x50, %g0, %g1
1067 stxa %g0, [%g1] ASI_DMMU_DEMAP
1068 done
1069.align 32 /* 18a */
1070hptrap_D_demap_nctx:
1071 or 0x60, %g0, %g1
1072 stxa %g0, [%g1] ASI_DMMU_DEMAP
1073 done
1074.align 32 /* 18b */
1075hptrap_D_demap_page:
1076 andn %i7, 0x0c7, %g1
1077 stxa %g0, [%g1] ASI_DMMU_DEMAP
1078 done
1079.align 32 /* 18c */
1080hptrap_D_demap_rpage:
1081 or 0x400, %i7, %g1
1082 andn %g1, 0x0c7, %g1
1083 stxa %g0, [%g1] ASI_DMMU_DEMAP
1084 done
1085.align 32 /* 18d */
1086 ta HP_BAD_TRAP
1087.align 32 /* 18e */
1088 ta HP_BAD_TRAP
1089.align 32 /* 18f */
1090 ta HP_BAD_TRAP
1091.align 32 /* 190 */
1092 ta HP_BAD_TRAP
1093.align 32 /* 191 */
1094hptrap_change_pid:
1095 mov ASI_PARTITION_ID_VAL, %g1
1096 ldxa [%g1] ASI_PARTITION_ID, %g2
1097 add %g2, 1, %g2
1098 and %g2, 7, %g2
1099 stxa %g2, [%g1] ASI_PARTITION_ID
1100 done
1101.align 32 /* 192 */
1102hptrap_incr_tsb_size:
1103 ta HP_BAD_TRAP
1104 !setx ext_trap_0x192_begin, %g1, %g2
1105 !jmp %g2
1106 !nop
1107.align 32 /* 193 */
1108clear_lsu_immu:
1109 or %g0, 0x4, %g1
1110 ldxa [%g0] 0x45, %g2
1111 xor %g2, %g1, %g3
1112 stxa %g3, [%g0] 0x45
1113 done
1114.align 32 /* 194 */
1115clear_lsu_dmmu:
1116 or %g0, 0x8, %g1
1117 ldxa [%g0] 0x45, %g2
1118 xor %g2, %g1, %g3
1119 stxa %g3, [%g0] 0x45
1120 done
1121.align 32 /* 195 */
1122delay_loop: /* %i7 = loop count */
1123 brnz,a %i7, delay_loop
1124 sub %i7, 1, %i7
1125 done
1126.align 32 /* 196 */
1127 setx ext_trap_sem_lock_begin, %g1, %g2
1128 jmp %g2
1129 nop
1130.align 32 /* 197 */
1131 setx ext_trap_sem_release_begin, %g1, %g2
1132 jmp %g2
1133 nop
1134.align 32 /* 198 */
1135 setx sem_data, %g5, %g4 ! %g4 = sem_data
1136 ldx [%g4+8], %i7
1137 done
1138.align 32 /* 199 */
1139 setx sem_data, %g5, %g4 ! %g4 = sem_data
1140 stx %i7, [%g4+8]
1141 done
1142.align 32 /* 19a */
1143goto_supervisor0:
1144 ! %i7 = target address for supervisor code
1145 rdhpr %hpstate, %i6
1146 rdpr %pstate, %g2
1147 wrpr %g2, 4, %pstate
1148 wrpr 0, %tl
1149 wrpr 0, %gl
1150 jmp %i7
1151 wrhpr %i6, 4, %hpstate
1152.align 32 /* 19b */
1153goto_supervisor1:
1154 ! %i7 = target address for supervisor code
1155 rdhpr %hpstate, %i6
1156 rdpr %pstate, %g2
1157 wrpr %g2, 4, %pstate
1158 wrpr 1, %tl
1159 wrpr 0, %gl
1160 jmp %i7
1161 wrhpr %i6, 4, %hpstate
1162.align 32 /* 19c */
1163hptrap_I_demap_all_pages:
1164 or 0x0c0, %g0, %g1
1165 stxa %g0, [%g1] ASI_IMMU_DEMAP
1166 done
1167.align 32 /* 19d */
1168hptrap_I_demap_all_rpages:
1169 or 0x4c0, %g0, %g1
1170 stxa %g0, [%g1] ASI_IMMU_DEMAP
1171 done
1172.align 32 /* 19e */
1173hptrap_D_demap_all_pages:
1174 or 0xc0, %g0, %g1
1175 stxa %g0, [%g1] ASI_DMMU_DEMAP
1176 done
1177.align 32 /* 19f */
1178hptrap_D_demap_all_rpages:
1179 or 0x8c0, %g0, %g1
1180 stxa %g0, [%g1] ASI_DMMU_DEMAP
1181 done
1182.align 32 /* 1a0 */
1183
1184trap_handler_1a0:
1185.global good_trap
1186good_trap:
1187 ba good_trap
1188 nop
1189 nop
1190 nop
1191
1192.align 32
1193trap_handler_1a1:
1194.global bad_trap
1195bad_trap:
1196 ba bad_trap
1197 nop
1198 nop
1199 nop
1200
1201.align 32 /* 1a2 */
1202hptrap_access_itsb_ptr:
1203 setx ext_trap_access_itsb_ptr, %g1, %g2
1204 jmp %g2
1205 nop
1206.align 32 /* 1a3 */
1207hptrap_access_dtsb_ptr:
1208 setx ext_trap_access_dtsb_ptr, %g1, %g2
1209 jmp %g2
1210 nop
1211.align 32 /* 1a4 */
1212hptrap_toggle_lsu_im:
1213 ldxa [%g0] 0x45, %g1
1214 xor %g1, 4, %g1
1215 stxa %g1, [%g0] 0x45
1216 done
1217.align 32 /* 1a5 */
1218hptrap_toggle_lsu_dm:
1219 ldxa [%g0] 0x45, %g1
1220 xor %g1, 8, %g1
1221 stxa %g1, [%g0] 0x45
1222 done
1223.align 32 /* 1a6 */
1224hptrap_load_idata_in:
1225#ifdef CUSTOM_TRAP_0XA6
1226 setx custom_trap_load_idata_in, %g1, %g2
1227 jmp %g2
1228 nop
1229#else
1230#ifdef MMU247
1231 setx ext_trap_load_idata_in, %g1, %g2
1232 jmp %g2
1233 nop
1234#else
1235 ta HP_BAD_TRAP
1236#endif
1237#endif
1238.align 32 /* 1a7 */
1239hptrap_load_ddata_in:
1240#ifdef CUSTOM_TRAP_0XA7
1241 setx custom_trap_load_ddata_in, %g1, %g2
1242 jmp %g2
1243 nop
1244#else
1245#ifdef MMU247
1246 setx ext_trap_load_ddata_in, %g1, %g2
1247 jmp %g2
1248 nop
1249#else
1250 ta HP_BAD_TRAP
1251#endif
1252#endif
1253
1254.align 32 /* 1a8 */
1255hptrap_read_idata_access:
1256#ifdef CUSTOM_TRAP_0XA8
1257 setx custom_trap_read_idata_access, %g1, %g2
1258 jmp %g2
1259 nop
1260#else
1261#ifdef MMU247
1262 ! We assume the index is in %i7
1263 ldxa [%i7] 0x55, %g1
1264 done
1265#else
1266 ta HP_BAD_TRAP
1267#endif
1268#endif
1269
1270.align 32 /* 1a9 */
1271hptrap_read_ddata_access:
1272#ifdef CUSTOM_TRAP_0XA9
1273 setx custom_trap_read_ddata_access, %g1, %g2
1274 jmp %g2
1275 nop
1276#else
1277#ifdef MMU247
1278 ! We assume the index is in %i7
1279 ldxa [%i7] 0x5d, %g1
1280 done
1281#else
1282 ta HP_BAD_TRAP
1283#endif
1284#endif
1285
1286.align 32 /* 1aa */
1287hptrap_user_trap:
1288#ifdef CUSTOM_TRAP_0XAA
1289 setx custom_user_trap, %g1, %g2
1290 jmp %g2
1291 nop
1292#else
1293#ifdef MMU247
1294 ta HP_BAD_TRAP
1295#else
1296 ta HP_BAD_TRAP
1297#endif
1298#endif
1299
1300.align 32 /* 1ab */
1301hptrap_load_idata_access:
1302#ifdef CUSTOM_TRAP_0XAB
1303 setx custom_trap_load_idata_access, %g1, %g2
1304 jmp %g2
1305 nop
1306#else
1307#ifdef MMU247
1308 ! We assume the index is in %i7
1309 setx ext_trap_load_idata_access, %g1, %g2
1310 jmp %g2
1311 nop
1312#else
1313 ta HP_BAD_TRAP
1314#endif
1315#endif
1316
1317.align 32 /* 1ac */
1318hptrap_load_ddata_access:
1319#ifdef CUSTOM_TRAP_0XAC
1320 setx custom_trap_load_ddata_access, %g1, %g2
1321 jmp %g2
1322 nop
1323#else
1324#ifdef MMU247
1325 ! We assume the index is in %i7
1326 setx ext_trap_load_ddata_access, %g1, %g2
1327 jmp %g2
1328 nop
1329#else
1330 ta HP_BAD_TRAP
1331#endif
1332#endif
1333
1334.align 32 /* 1ad */
1335hptrap_itlb_probe:
1336 ! We assume the VA is in %i7
1337 ldxa [%i7] 0x53, %i7
1338 done
1339
1340.align 32 /* 1ae */
1341toggle_hwtw_demap:
1342 setx ext_trap_toggle_hwtw_demap, %g1, %g2
1343 jmp %g2
1344 nop
1345
1346.align 32 /* 1af */
1347hptrap_itlb_tag_read:
1348#ifdef MMU247
1349 ! We assume the index is in %i7
1350 ldxa [%i7] MMU_ASI_I_TAG_READ_REG, %g1
1351 done
1352#else
1353 ta HP_BAD_TRAP
1354#endif
1355
1356.align 32 /* 1b0 */
1357hptrap_dtlb_tag_read:
1358#ifdef MMU247
1359 ! We assume the index is in %i7
1360 ldxa [%i7] MMU_ASI_D_TAG_READ_REG, %g1
1361 done
1362#else
1363 ta HP_BAD_TRAP
1364#endif
1365
1366.align 32 /* 1b1 */
1367#ifdef MMU247
1368 wrpr %g0, %tl
1369 wrpr %g0, %gl
1370 wrpr %i6, %pstate
1371 rdhpr %hpstate, %i6
1372 jmp %i7
1373 wrhpr %i6, 4, %hpstate
1374#else
1375 ta HP_BAD_TRAP
1376#endif
1377
1378!******************************************************************************************
1379SECTION .HPTRAPS_EXT_SECT TEXT_VA=HPTRAPS_EXT_TEXT_PA, DATA_VA=HPTRAPS_EXT_DATA_PA
1380
1381attr_text {
1382 Name=.HPTRAPS_EXT_SECT,
1383 hypervisor
1384}
1385
1386.text
1387.global ext_trap_0x2a_begin
1388.global ext_trap_0x2b_begin
1389.global ext_trap_0x3e_begin
1390.global ext_trap_0x3f_begin
1391.global ext_trap_0x64_begin
1392.global ext_trap_0x68_begin
1393.global ext_trap_0x192_begin
1394.global ext_trap_sem_lock_begin
1395.global ext_trap_sem_release_begin
1396.global ext_trap_access_itsb_ptr
1397.global ext_trap_access_dtsb_ptr
1398.global ext_trap_0x8_begin
1399.global ext_trap_0x9_begin
1400.global ext_trap_0x1b_begin
1401.global ext_trap_0x31_begin
1402.global function_tsb_ptr_calc
1403.global ext_trap_load_idata_in
1404.global ext_trap_load_ddata_in
1405.global ext_trap_load_idata_access
1406.global ext_trap_load_ddata_access
1407.global ext_trap_toggle_hwtw_demap
1408
1409ext_trap_toggle_hwtw_demap:
1410 or %g0, MMU_ASI_TSB_CONFIG_REG, %g1
1411 wr %g1, 0x0, %asi
1412 or %g0, 1, %g1
1413 sllx %g1, 63, %g1
1414 ldxa [MMU_ASI_Z_CTX_TSB_CONFIG_0_ADDR] %asi, %g2
1415 xor %g2, %g1, %g2
1416 stxa %g2, [MMU_ASI_Z_CTX_TSB_CONFIG_0_ADDR] %asi
1417 ldxa [MMU_ASI_Z_CTX_TSB_CONFIG_1_ADDR] %asi, %g2
1418 xor %g2, %g1, %g2
1419 stxa %g2, [MMU_ASI_Z_CTX_TSB_CONFIG_1_ADDR] %asi
1420 ldxa [MMU_ASI_Z_CTX_TSB_CONFIG_2_ADDR] %asi, %g2
1421 xor %g2, %g1, %g2
1422 stxa %g2, [MMU_ASI_Z_CTX_TSB_CONFIG_2_ADDR] %asi
1423 ldxa [MMU_ASI_Z_CTX_TSB_CONFIG_3_ADDR] %asi, %g2
1424 xor %g2, %g1, %g2
1425 stxa %g2, [MMU_ASI_Z_CTX_TSB_CONFIG_3_ADDR] %asi
1426 ldxa [MMU_ASI_NZ_CTX_TSB_CONFIG_0_ADDR] %asi, %g2
1427 xor %g2, %g1, %g2
1428 stxa %g2, [MMU_ASI_NZ_CTX_TSB_CONFIG_0_ADDR] %asi
1429 ldxa [MMU_ASI_NZ_CTX_TSB_CONFIG_1_ADDR] %asi, %g2
1430 xor %g2, %g1, %g2
1431 stxa %g2, [MMU_ASI_NZ_CTX_TSB_CONFIG_1_ADDR] %asi
1432 ldxa [MMU_ASI_NZ_CTX_TSB_CONFIG_2_ADDR] %asi, %g2
1433 xor %g2, %g1, %g2
1434 stxa %g2, [MMU_ASI_NZ_CTX_TSB_CONFIG_2_ADDR] %asi
1435 ldxa [MMU_ASI_NZ_CTX_TSB_CONFIG_3_ADDR] %asi, %g2
1436 xor %g2, %g1, %g2
1437 stxa %g2, [MMU_ASI_NZ_CTX_TSB_CONFIG_3_ADDR] %asi
1438 andcc %g2, 0x70, %g0
1439 be,a %xcc, ext_trap_toggle_hwtw_no_demap
1440 nop
1441 ! Demap all
1442 or %g0, 0x0c0, %g3
1443 stxa %g0, [%g3] MMU_ASI_I_DEMAP
1444 stxa %g0, [%g3] MMU_ASI_D_DEMAP
1445ext_trap_toggle_hwtw_no_demap:
1446 done
1447
1448!****************************************************************************************
1449ext_trap_access_itsb_ptr:
1450 ! we use %l1 to determine which register to access
1451 srlx %l1, 40, %g7
1452 and %g7, 0x78, %g1
1453 cmp %g1, 0x50
1454 bne,a %xcc, ext_trap_access_itsb_ptr_58
1455 cmp %g1, 0x58
1456 ldxa [%g1] 0x54, %g2
1457 done
1458ext_trap_access_itsb_ptr_58:
1459 bne,a %xcc, ext_trap_access_itsb_ptr_60
1460 cmp %g1, 0x60
1461 ldxa [%g1] 0x54, %g2
1462 done
1463ext_trap_access_itsb_ptr_60:
1464 bne,a %xcc, ext_trap_access_itsb_ptr_68
1465 cmp %g1, 0x68
1466 ldxa [%g1] 0x54, %g2
1467 done
1468ext_trap_access_itsb_ptr_68:
1469 bne,a %xcc, ext_trap_access_itsb_ptr_all
1470 or %g0, 0x50, %g1
1471 ldxa [%g1] 0x54, %g2
1472 done
1473ext_trap_access_itsb_ptr_all:
1474 ldxa [%g1] 0x54, %g2
1475 or %g0, 0x58, %g1
1476 ldxa [%g1] 0x54, %g2
1477 or %g0, 0x60, %g1
1478 ldxa [%g1] 0x54, %g2
1479 or %g0, 0x68, %g1
1480 ldxa [%g1] 0x54, %g2
1481 done
1482
1483!****************************************************************************************
1484ext_trap_access_dtsb_ptr:
1485 ! we use %l1 to determine which register to access
1486 srlx %l1, 40, %g7
1487 and %g7, 0x78, %g1
1488 cmp %g1, 0x70
1489 bne,a %xcc, ext_trap_access_dtsb_ptr_78
1490 cmp %g1, 0x78
1491 ldxa [%g1] 0x54, %g2
1492 done
1493ext_trap_access_dtsb_ptr_78:
1494 bne,a %xcc, ext_trap_access_dtsb_ptr_80
1495 cmp %g1, 0x80
1496 ldxa [%g1] 0x54, %g2
1497 done
1498ext_trap_access_dtsb_ptr_80:
1499 bne,a %xcc, ext_trap_access_dtsb_ptr_88
1500 cmp %g1, 0x88
1501 ldxa [%g1] 0x54, %g2
1502 done
1503ext_trap_access_dtsb_ptr_88:
1504 bne,a %xcc, ext_trap_access_dtsb_ptr_all
1505 or %g0, 0x70, %g1
1506 ldxa [%g1] 0x54, %g2
1507 done
1508ext_trap_access_dtsb_ptr_all:
1509 ldxa [%g1] 0x54, %g2
1510 or %g0, 0x78, %g1
1511 ldxa [%g1] 0x54, %g2
1512 or %g0, 0x80, %g1
1513 ldxa [%g1] 0x54, %g2
1514 or %g0, 0x88, %g1
1515 ldxa [%g1] 0x54, %g2
1516 done
1517
1518!****************************************************************************************
1519ext_trap_sem_lock_begin:
1520 or %i7, %g0, %g7 ! save %i7
1521 wr %g0, ASI_CORE_ID, %asi
1522 ldxa [ASI_CORE_ID_VA] %asi, %g1 ! %g1 = core id + tid
1523ext_trap_sem_lock_loop:
1524 or %g0, 0x100, %i7
1525 or %g0, %g1, %g2
1526 or %g0, 0x0fff, %g3 ! %g3 = compare value
1527 setx sem_data, %g5, %g4 ! %g4 = sem_data
1528 casxa [%g4] 0x80, %g3, %g2
1529 cmp %g2, 0x0fff
1530 bne,a %xcc, ext_trap_sem_lock_loop
1531 ta HPTRAP_DELAY_LOOP
1532 or %g7, %g0, %i7 ! restore %i7
1533 done
1534
1535ext_trap_sem_release_begin:
1536 wr %g0, ASI_CORE_ID, %asi
1537 ldxa [ASI_CORE_ID_VA] %asi, %g1 ! %g1 = core id + tid
1538 or %g0, 0x0fff, %g3 ! %g3 = compare value
1539 setx sem_data, %g5, %g4 ! %g4 = sem_data
1540 casxa [%g4] 0x80, %g1, %g3
1541 done
1542
1543
1544!****************************************************************************************
1545ext_trap_0x2a_begin:
1546 ta HP_BAD_TRAP
1547
1548!****************************************************************************************
1549ext_trap_0x2b_begin:
1550 ta HP_BAD_TRAP
1551
1552!****************************************************************************************
1553ext_trap_0x3e_begin:
1554 save ! Save %l2 and %l4 to be used in code below
1555
1556 ldxa [%g0] 0x50, %g1 ! %g1 = immu tag target
1557 ! Mask out context before comparing tags
1558 sethi 0x1fff, %g3
1559 sllx %g3, 38, %g3
1560 andn %g1, %g3, %g1 ! %g1 = masked tag target
1561 !
1562 ! Randomly pick zero or non-zero ctx to start with. We use context[0] as random seed
1563 ! context[0] = 0 ==> zero ctx is picked first
1564 ! context[0] = 1 ==> non-zero ctx is picked first
1565 !
1566 ! The other consideration is we need to write the correct context (zero or non-zero)
1567 ! to the tag access register in order to get the correct tsb pointer. If we pick the
1568 ! zero context first, then we need to program the tag access register with a zero
1569 ! context. Otherwise, we will program the tag access register with a non-zero context.
1570 !
1571 ! Case 1: zero context is picked first
1572 ! We read tsb pointers for the four zero context tsb config regs.
1573 ! If no entry was found, we invert the context in tag access reg
1574 ! Now we read the four non-zero context tsb config regs
1575 ! Case 2: non-zero context is picked first
1576 ! We invert the context in tag access reg
1577 ! Read tsb pointers for the four non-zero context tsb config regs
1578 ! If no entry was found, clear the context in tag access reg
1579 ! Read tsb pointers for the four zero context tsb config regs
1580 !
1581 setx tsb_addresses_zero, %g2, %l4
1582 or %g0, 0x30, %g5
1583 ldxa [%g5] 0x50, %l2 ! %l2 = tag access
1584 or %g0, 0x1fff, %g4
1585 sllx %g4, 13, %g4
1586 and %l2, %g4, %l2 ! %l2 = tag access with zero context
1587 ! We use bit VA[28] as random selection between zero and non-zero context
1588 srlx %l2, 28, %g4
1589 and %g4, 1, %g3
1590 brz,a %g3, trap_0x3e_zero_ctx
1591 nop
1592 add %l4, 72, %l4 ! %l4 = tsb_addresses_non_zero
1593 or %l2, 1, %l2 ! %l2 = tag access with non-zero context
1594 ! %g1 = masked tag
1595trap_0x3e_zero_ctx:
1596 stxa %l2, [%g5] 0x50 ! update tag access with proper context
1597 ldx [%l4], %g4 ! %g4 = va to tsb config reg
1598 or %g0, 0x50, %g2 ! %g2 = va to tsb pointer 0
1599trap_0x3e_next_tte:
1600 ! %g1=masked tag, %g2=va to tsb ptr, %g4=va to tsb config
1601 ldxa [%g2] 0x54, %g3 ! %g3 = dtsb pointer
1602 ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g6 ! %g6 = TTE_TAG, %g7 = TTE_DATA
1603 sethi 0x1fff, %g3
1604 sllx %g3, 38, %g3
1605 andn %g6, %g3, %g3 ! %g3 has the masked tag
1606 ! Need to mask out va[27:22] if page size is 5
1607 ldxa [%g4] 0x54, %g5 ! %g5 = TSB_CONFIG
1608 and %g5, 0x70, %g4 ! %g4 = PSIZE
1609 cmp %g4, 0x50
1610 be,a trap_0x3e_256m_page
1611 or %g0, 0x3f, %l1
1612 or %g0, 0, %l1
1613trap_0x3e_256m_page:
1614 ! %g1=tag target, %g2=va to tsb ptr, %g3=masked tte tag
1615 ! %g4=page size, %g5=tsb config reg
1616 andn %g1, %l1, %l1
1617 cmp %g3, %l1
1618 bne,a %xcc, trap_0x3e_next_tsb_ptr
1619 add %g2, 8, %g2
1620 srlx %g7, 63, %g3
1621 brz,a %g3, trap_0x3e_next_tsb_ptr
1622 add %g2, 8, %g2
1623
1624 ! check the ranotpa bit
1625 andcc %g5, 0x100, %g0
1626 be,a %xcc, trap_0x3e_skip_ra
1627 nop
1628
1629 ! look up realrange registers
1630 setx trap_ra_mask, %g3, %g6
1631 cmp %g4, 0x00
1632 be,a trap_0x3e_get_rr_limits
1633 add %g6, 48, %g6
1634 cmp %g4, 0x10
1635 be,a trap_0x3e_get_rr_limits
1636 add %g6, 32, %g6
1637 cmp %g4, 0x30
1638 be,a trap_0x3e_get_rr_limits
1639 add %g6, 16, %g6
1640trap_0x3e_get_rr_limits:
1641 ldda [%g6] 0x24, %g2 ! %g2 = RA_max mask, %g3 = RA_min mask
1642 sllx %g7, 24, %g5
1643 srlx %g5, 37, %g5
1644 sllx %g5, 13, %g5 ! %g5 = RA
1645 or %g5, %g2, %g2 ! %g2 = RA_max
1646 and %g5, %g3, %g3 ! %g3 = RA_min
1647
1648 or %g0, 0x108, %g1 ! %g1 points to REAL_RANGE_REG
1649trap_0x3e_next_rr:
1650 cmp %g1, 0x128
1651 bl,a %xcc, trap_0x3e_get_rr
1652 ldxa [%g1] 0x52, %g5 ! %g5 = REAL_RANGE
1653 done ! Error
1654trap_0x3e_get_rr:
1655 srlx %g5, 63, %g6 ! Check for the enable bit
1656 brz,a %g6, trap_0x3e_next_rr
1657 add %g1, 8, %g1
1658
1659 sllx %g5, 10, %g6 ! %g6 = RR left shift by 10
1660 srlx %g6, 37, %g6
1661 sllx %g6, 13, %g6 ! %g6 = RA_max
1662 cmp %g6, %g2
1663 bl,a %xcc, trap_0x3e_next_rr
1664 add %g1, 8, %g1
1665 sllx %g5, 37, %g6
1666 srlx %g6, 24, %g6 ! %g6 = RA_min
1667 cmp %g6, %g3
1668 bg,a %xcc, trap_0x3e_next_rr
1669 add %g1, 8, %g1
1670 add %g1, 0x100, %g1
1671 ldxa [%g1] 0x52, %g1 ! %g1 = physical offset
1672 add %g7, %g1, %g7
1673
1674trap_0x3e_skip_ra:
1675 or %g0, 0x30, %g4
1676 or %l2, 0x0ff, %l2
1677 stxa %l2, [%g4] 0x50 ! write non-zero context to tag access
1678 or %g0, 0x0400, %g5
1679 stxa %g7, [%g5] 0x54 ! write to data in
1680 ! Set im bit
1681 ldxa [%g0] 0x45, %g1
1682 or %g1, 4, %g1
1683 stxa %g1, [%g0] 0x45
1684 restore
1685 retry
1686
1687trap_0x3e_next_tsb_ptr:
1688 cmp %g2, 0x70
1689 bne,a %xcc, trap_0x3e_next_tsb_va
1690 nop
1691 or %g0, 0x50, %g2 ! Need to wrap it back to 0x50 (itsb ptr 0)
1692 xor %l2, 1, %l2
1693 or %g0, 0x30, %g5
1694 stxa %l2, [%g5] 0x50 ! write inverted context to tag access
1695trap_0x3e_next_tsb_va:
1696 add %l4, 8, %l4 ! go to next VA for tsb config reg
1697 ldx [%l4], %g4
1698 cmp %g4, 0x0ff ! we have exhausted all 8 regs if value is 0xff
1699 bne,a %xcc, trap_0x3e_next_tte
1700 nop
1701 restore
1702 ta HP_BAD_TRAP
1703
1704!****************************************************************************************
1705ext_trap_0x3f_begin:
1706 save ! Save %l2 and %l4 to be used in code below
1707
1708 ldxa [%g0] 0x58, %g1 ! %g1 = dmmu tag target
1709 ! Mask out context before comparing tags
1710 sethi 0x1fff, %g3
1711 sllx %g3, 38, %g3
1712 andn %g1, %g3, %g1 ! %g1 = masked tag target
1713 !
1714 ! Randomly pick zero or non-zero ctx to start with. We use context[0] as random seed
1715 ! context[0] = 0 ==> zero ctx is picked first
1716 ! context[0] = 1 ==> non-zero ctx is picked first
1717 !
1718 ! The other consideration is we need to write the correct context (zero or non-zero)
1719 ! to the tag access register in order to get the correct tsb pointer. For a real miss
1720 ! the context is zero in the tag access register.
1721 !
1722 ! Case 1: zero context is picked first
1723 ! We read tsb pointers for the four zero context tsb config regs.
1724 ! If no entry was found, we invert the context in tag access reg
1725 ! Now we read the four non-zero context tsb config regs
1726 ! Case 2: non-zero context is picked first
1727 ! We invert the context in tag access reg
1728 ! Read tsb pointers for the four non-zero context tsb config regs
1729 ! If no entry was found, clear the context in tag access reg
1730 ! Read tsb pointers for the four zero context tsb config regs
1731 !
1732 setx tsb_addresses_zero, %g2, %l4
1733 or %g0, 0x30, %g5
1734 ldxa [%g5] 0x58, %l2 ! %l2 = tag access
1735 or %g0, 0x1fff, %g4
1736 sllx %g4, 13, %g4
1737 and %l2, %g4, %l2 ! %l2 = tag access with zero context
1738 ! We use bit VA[28] as random selection between zero and non-zero context
1739 srlx %l2, 28, %g4
1740 and %g4, 1, %g3
1741 brz,a %g3, trap_0x3f_zero_ctx
1742 nop
1743 add %l4, 72, %l4 ! %l4 = tsb_addresses_non_zero
1744 or %l2, 1, %l2
1745 ! %g1 = masked tag
1746trap_0x3f_zero_ctx:
1747 stxa %l2, [%g5] 0x58 ! update tag access with proper context
1748 ldx [%l4], %g4 ! %g4 = va to tsb config reg
1749 or %g0, 0x70, %g2 ! %g2 = va to tsb pointer 0
1750trap_0x3f_next_tte:
1751 ! %g1=masked tag, %g2=va to tsb ptr, %g4=va to tsb config
1752 ldxa [%g2] 0x54, %g3 ! %g3 = dtsb pointer
1753 ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g6 ! %g6 = TTE_TAG, %g7 = TTE_DATA
1754 sethi 0x1fff, %g3
1755 sllx %g3, 38, %g3
1756 andn %g6, %g3, %g3 ! %g3 has the tte tag with zero context
1757 ! Need to mask out va[27:22] if page size is 5
1758 ldxa [%g4] 0x54, %g5 ! %g5 = TSB_CONFIG
1759 and %g5, 0x70, %g4 ! %g4 = PSIZE
1760 cmp %g4, 0x50
1761 be,a trap_0x3f_256m_page
1762 or %g0, 0x3f, %l1
1763 or %g0, 0, %l1
1764trap_0x3f_256m_page:
1765 ! %g1=tag target, %g2=va to tsb ptr, %g3=masked tte tag
1766 ! %g4=page size, %g5=tsb config reg
1767 andn %g1, %l1, %l1
1768 cmp %g3, %l1
1769 bne,a %xcc, trap_0x3f_next_tsb_ptr
1770 add %g2, 8, %g2
1771 srlx %g7, 63, %g3
1772 brz,a %g3, trap_0x3f_next_tsb_ptr
1773 add %g2, 8, %g2
1774
1775 ! check the ranotpa bit
1776 andcc %g5, 0x100, %g0
1777 be,a %xcc, trap_0x3f_skip_ra
1778 nop
1779
1780 ! look up realrange registers
1781 setx trap_ra_mask, %g3, %g6
1782 cmp %g4, 0x00
1783 be,a trap_0x3f_get_rr_limits
1784 add %g6, 48, %g6
1785 cmp %g4, 0x10
1786 be,a trap_0x3f_get_rr_limits
1787 add %g6, 32, %g6
1788 cmp %g4, 0x30
1789 be,a trap_0x3f_get_rr_limits
1790 add %g6, 16, %g6
1791trap_0x3f_get_rr_limits:
1792 ldda [%g6] 0x24, %g2 ! %g2 = RA_max mask, %g3 = RA_min mask
1793 sllx %g7, 24, %g5
1794 srlx %g5, 37, %g5
1795 sllx %g5, 13, %g5 ! %g5 = RA
1796 or %g5, %g2, %g2 ! %g2 = RA_max
1797 and %g5, %g3, %g3 ! %g3 = RA_min
1798
1799 or %g0, 0x108, %g1 ! %g1 points to REAL_RANGE_REG
1800trap_0x3f_next_rr:
1801 cmp %g1, 0x128
1802 bl,a %xcc, trap_0x3f_get_rr
1803 ldxa [%g1] 0x52, %g5 ! %g5 = REAL_RANGE
1804 done ! Error
1805trap_0x3f_get_rr:
1806 srlx %g5, 63, %g6 ! Check for the enable bit
1807 brz,a %g6, trap_0x3f_next_rr
1808 add %g1, 8, %g1
1809
1810 sllx %g5, 10, %g6 ! %g6 = RR left shift by 10
1811 srlx %g6, 37, %g6
1812 sllx %g6, 13, %g6 ! %g6 = RA_max
1813 cmp %g6, %g2
1814 bl,a %xcc, trap_0x3f_next_rr
1815 add %g1, 8, %g1
1816 sllx %g5, 37, %g6
1817 srlx %g6, 24, %g6 ! %g6 = RA_min
1818 cmp %g6, %g3
1819 bg,a %xcc, trap_0x3f_next_rr
1820 add %g1, 8, %g1
1821 add %g1, 0x100, %g1
1822 ldxa [%g1] 0x52, %g1 ! %g1 = physical offset
1823 add %g7, %g1, %g7
1824
1825trap_0x3f_skip_ra:
1826 or %g0, 0x30, %g4
1827 or %l2, 0x0ff, %l2
1828 stxa %l2, [%g4] 0x58 ! write non-zero context to tag access
1829 or %g0, 0x0400, %g5
1830 stxa %g7, [%g5] 0x5c ! write to data in
1831 ! Set dm bit
1832 ldxa [%g0] 0x45, %g1
1833 or %g1, 8, %g1
1834 stxa %g1, [%g0] 0x45
1835 restore
1836 retry
1837
1838trap_0x3f_next_tsb_ptr:
1839 cmp %g2, 0x90
1840 bne,a %xcc, trap_0x3f_next_tsb_va
1841 nop
1842 or %g0, 0x70, %g2 ! Need to wrap it back to 0x70 (dtsb ptr 0)
1843 xor %l2, 1, %l2
1844 or %g0, 0x30, %g5
1845 stxa %l2, [%g5] 0x58 ! write inverted context to tag access
1846trap_0x3f_next_tsb_va:
1847 add %l4, 8, %l4 ! go to next VA for tsb config reg
1848 ldx [%l4], %g4
1849 cmp %g4, 0x0ff ! we have exhausted all 8 regs if value is 0xff
1850 bne,a %xcc, trap_0x3f_next_tte
1851 nop
1852 restore
1853 ! Instead of going to bad trap, we just go ahead and skip this ld/st instruction
1854 !ta HP_BAD_TRAP
1855 done
1856
1857!****************************************************************************************
1858ext_trap_0x64_begin:
1859 save
1860 ldxa [%g0] MMU_ASI_ITSB_TAG_TARGET_REG, %g1 ! %g1 = tag target
1861 or %g0, MMU_ASI_ITSB_PTR_0_ADDR, %g2 ! %g2 = tsb ptr addr
1862 srlx %g1, 48, %g3 ! %g3 = req_ctx
1863 brz,a %g3, trap_0x64_load_tsb_config
1864 or %g0, MMU_ASI_Z_CTX_TSB_CONFIG_0_ADDR, %g3
1865 or %g0, MMU_ASI_NZ_CTX_TSB_CONFIG_0_ADDR, %g3
1866trap_0x64_load_tsb_config:
1867 ldxa [%g3] MMU_ASI_TSB_CONFIG_REG, %g4 ! %g4 = tsb config
1868 stxa %g4, [%g0] MMU_ASI_HYP_SCRATCHPAD_REG
1869 ldxa [%g2] MMU_ASI_TSB_PTR_REG, %g5 ! %g5 = tsb ptr
1870trap_0x64_load_tte:
1871 ldda [%g5] ASI_NUCLEUS_QUAD_LDD, %g6 ! %g6=TTE_TAG, %g7=TTE_DATA
1872 ! If page size is 256m, mask out va[27:22]
1873 ldxa [%g3] MMU_ASI_TSB_CONFIG_REG, %g4 ! %g4 = tsb config
1874 and %g4, 0x70, %g4
1875 cmp %g4, 0x50
1876 bne,a %xcc, trap_0x64_not_256m_page
1877 or %g0, %g1, %o1
1878 and %g1, 0x1fc0, %o1
1879 and %g6, 0x1fc0, %g6
1880trap_0x64_not_256m_page:
1881 cmp %g6, %o1 ! Compare TAG
1882 bne,a %xcc, trap_0x64_next_ptr
1883 add %g2, 8, %g2
1884 srlx %g7, 63, %g5 ! Check Valid bit
1885 brz,a %g5, trap_0x64_next_ptr
1886 add %g2, 8, %g2
1887 ! At this point, we have got the TTE to be loaded into the TLB.
1888 ! We just need to figure out what physical offset to use.
1889 ! Register %g4 and %g7 are restricted.
1890 setx trap_ra_mask, %g5, %g6
1891 ldxa [%g0] 0x4f, %g5 ! %g5 = TSB_CONFIG
1892 and %g5, 0x100, %g3 ! %g3 has the ranotpa bit
1893 brz,a %g3, trap_0x64_skip_ra
1894 nop
1895 and %g5, 0x70, %g3 ! %g3 = PSIZE
1896 cmp %g3, 0x00
1897 be,a trap_0x64_get_rr_limits
1898 add %g6, 48, %g6
1899 cmp %g3, 0x10
1900 be,a trap_0x64_get_rr_limits
1901 add %g6, 32, %g6
1902 cmp %g3, 0x30
1903 be,a trap_0x64_get_rr_limits
1904 add %g6, 16, %g6
1905trap_0x64_get_rr_limits:
1906 ldda [%g6] 0x24, %g2 ! %g2 = RA_max mask, %g3 = RA_min mask
1907 sllx %g7, 24, %g5
1908 srlx %g5, 37, %g5
1909 sllx %g5, 13, %g5 ! %g5 = RA
1910 or %g5, %g2, %g2 ! %g2 = RA_max
1911 and %g5, %g3, %g3 ! %g3 = RA_min
1912
1913 or %g0, 0x108, %g1 ! %g1 points to REAL_RANGE_REG
1914trap_0x64_next_rr:
1915 cmp %g1, 0x128
1916 bl,a %xcc, trap_0x64_get_rr
1917 ldxa [%g1] 0x52, %g5 ! %g5 = REAL_RANGE
1918 done ! Error
1919trap_0x64_get_rr:
1920 srlx %g5, 63, %g6 ! Check for the enable bit
1921 brz,a %g6, trap_0x64_next_rr
1922 add %g1, 8, %g1
1923
1924 sllx %g5, 10, %g6 ! %g6 = RR left shift by 10
1925 srlx %g6, 37, %g6
1926 sllx %g6, 13, %g6 ! %g6 = RA_max
1927 cmp %g6, %g2
1928 bl,a %xcc, trap_0x64_next_rr
1929 add %g1, 8, %g1
1930 sllx %g5, 37, %g6
1931 srlx %g6, 24, %g6 ! %g6 = RA_min
1932 cmp %g6, %g3
1933 bg,a %xcc, trap_0x64_next_rr
1934 add %g1, 8, %g1
1935 add %g1, 0x100, %g1
1936 ldxa [%g1] 0x52, %g1 ! %g1 = physical offset
1937 add %g7, %g1, %g7
1938trap_0x64_skip_ra:
1939 !
1940 ! To prevent multiple hits as a result of loading the itlb with entries with
1941 ! different contexts, we need to look at the use_context bits in the TSB config.
1942 ! The pseudo algorithm is
1943 !
1944 ! We are assuming the context in the tte is the primary context 0
1945 !
1946 ! if (not nucleus context) {
1947 ! if (use_ctx_1 == 1) {
1948 ! get pctx_1
1949 ! store pctx_1 in tag_access reg
1950 ! }
1951 ! }
1952 !
1953 ldxa [%g0] 0x50, %l1 ! %l1 = itlb tag target
1954 srlx %l1, 48, %l1 ! %l1 = req_ctx
1955 brz,a %l1, trap_0x64_not_ctx_1
1956 nop
1957 ldxa [%g0] 0x4f, %g5 ! %g5 = TSB_CONFIG
1958 srlx %g5, 61, %g5
1959 and %g5, 3, %g5
1960 cmp %g5, 1
1961 bne,a %xcc, trap_0x64_not_ctx_1
1962 nop
1963 or %g0, 0x30, %l1
1964 ldxa [%l1] 0x50, %l1 ! %l1 = itlb tag access
1965 sub %g0, 1, %l0
1966 srlx %l0, 51, %l0 ! %l0 = context mask
1967 andn %l1, %l0, %l1 ! %l1 = tag access with zero context
1968 or %g0, 0x108, %l2
1969 ldxa [%l2] 0x21, %l2 ! %l2 = pctx_1
1970 or %l1, %l2, %l1 ! %l1 = tag access with pctx_1
1971 or %g0, 0x30, %l3
1972 stxa %l1, [%l3] 0x50 ! update tag access with pctx_1
1973trap_0x64_not_ctx_1:
1974 stxa %g7, [%g0] MMU_ASI_I_DATA_IN_REG
1975 restore
1976 retry
1977
1978trap_0x64_next_ptr:
1979 cmp %g2, 0x70
1980 bl,a %xcc, trap_0x64_load_tsb_config
1981 add %g3, 8, %g3
1982#ifdef MMU247
1983 setx ext_trap_0x8_begin, %g2, %g1
1984 jmp %g1
1985 nop
1986#else
1987 ta HP_BAD_TRAP
1988#endif
1989
1990!****************************************************************************************
1991ext_trap_0x68_begin:
1992 save
1993 ldxa [%g0] MMU_ASI_DTSB_TAG_TARGET_REG, %g1 ! %g1 = dmmu_tag_target
1994 or %g0, MMU_ASI_DTSB_PTR_0_ADDR, %g2 ! %g2 points to dtsb_ptr_0
1995 srlx %g1, 48, %g3 ! %g3 = incoming ctx
1996 brz,a %g3, trap_0x68_load_tsb_config
1997 or %g0, MMU_ASI_Z_CTX_TSB_CONFIG_0_ADDR, %g3
1998 or %g0, MMU_ASI_NZ_CTX_TSB_CONFIG_0_ADDR, %g3
1999trap_0x68_load_tsb_config:
2000 ldxa [%g3] MMU_ASI_TSB_CONFIG_REG, %g4 ! %g4 = tsb_config
2001 stxa %g4, [%g0] MMU_ASI_HYP_SCRATCHPAD_REG ! save tsb_config in scratch pad
2002 ldxa [%g2] MMU_ASI_TSB_PTR_REG, %g5 ! %g5 = dtsb_ptr
2003trap_0x68_load_tte:
2004 ldda [%g5] ASI_NUCLEUS_QUAD_LDD, %g6 ! %g6=TTE_TAG, %g7=TTE_DATA
2005 srlx %g7, 63, %g5 ! Check Valid bit
2006 brz,a %g5, trap_0x68_next_ptr
2007 add %g2, 8, %g2
2008 !
2009 ! Need to check for context right here
2010 ! if (! nucleus) {
2011 ! case (req_ctx == pctx0 && use_ctx_0 == 1):
2012 ! update_tag_access_with_pctx0
2013 ! case (req_ctx == pctx0 && use_ctx_0 == 0 && use_ctx_1 == 1):
2014 ! update_tag_access_with_pctx1
2015 ! case (req_ctx == sctx0 && use_ctx_0 == 1):
2016 ! update_tag_access_with_sctx0
2017 ! case (req_ctx == sctx0 && use_ctx_0 == 0 && use_ctx_1 == 1):
2018 ! update_tag_access_with_sctx1
2019 ! }
2020 !
2021 ldxa [%g0] MMU_ASI_DTSB_TAG_TARGET_REG, %i0 ! %i0 = dtlb tag target
2022 srlx %i0, 48, %i1 ! %i1 = req_ctx
2023 brz,a %i1, trap_0x68_bypass_update_tag_access
2024 nop
2025 !
2026 ! the req_ctx is non-zero, we need to look at the use_context bits next
2027 !
2028 ldxa [%g0] MMU_ASI_HYP_SCRATCHPAD_REG, %i2 ! %i2 = tsb config
2029 srlx %i2, 61, %i2
2030 andcc %i2, 3, %i2
2031 be,a %xcc, trap_0x68_bypass_update_tag_access
2032 nop
2033 andcc %i2, 2, %g0
2034 be,a %xcc, trap_0x68_not_use_ctx_0
2035 nop
2036 !
2037 ! use_context_0 = 1
2038 !
2039 or %g0, MMU_ASI_PRIMARY_CONTEXT_0_ADDR, %i0
2040 ldxa [%i0] MMU_ASI_CONTEXT_REG, %i3
2041 cmp %i3, %i1
2042 be,a %xcc, trap_0x68_update_tag_access
2043 nop
2044 or %g0, MMU_ASI_SECONDARY_CONTEXT_0_ADDR, %i0
2045 ldxa [%i0] MMU_ASI_CONTEXT_REG, %i3
2046 ba trap_0x68_update_tag_access
2047 nop
2048trap_0x68_not_use_ctx_0:
2049 !
2050 ! use_context_0 = 0 && use_context_1 = 1
2051 !
2052 or %g0, MMU_ASI_PRIMARY_CONTEXT_0_ADDR, %i0
2053 ldxa [%i0] MMU_ASI_CONTEXT_REG, %i3
2054 cmp %i3, %i1
2055 bne,a %xcc, trap_0x68_secondary_ctx
2056 nop
2057 or %g0, MMU_ASI_PRIMARY_CONTEXT_1_ADDR, %i0
2058 ldxa [%i0] MMU_ASI_CONTEXT_REG, %i3
2059 ba trap_0x68_update_tag_access
2060 nop
2061trap_0x68_secondary_ctx:
2062 or %g0, MMU_ASI_SECONDARY_CONTEXT_1_ADDR, %i0
2063 ldxa [%i0] MMU_ASI_CONTEXT_REG, %i3
2064trap_0x68_update_tag_access:
2065 !
2066 ! %i3 has the new context
2067 ! we also need to mask out the context in the tte_tag (%g6)
2068 !
2069 sllx %g1, 16, %g1
2070 srlx %g1, 16, %g1 ! %g1 = expected tag target with masked context
2071 sllx %g6, 16, %g6
2072 srlx %g6, 16, %g6 ! %g6 = actual tag target with masked context
2073 or %g0, MMU_ASI_D_TAG_ACCESS_ADDR, %i0
2074 ldxa [%i0] MMU_ASI_D_TAG_ACCESS_REG, %i0
2075 srlx %i0, 13, %i0
2076 sllx %i0, 13, %i0
2077 or %i0, %i3, %i3 ! %i3 = tag access with updated context
2078 or %g0, MMU_ASI_D_TAG_ACCESS_ADDR, %i0
2079 stxa %i3, [%i0] MMU_ASI_D_TAG_ACCESS_REG
2080trap_0x68_bypass_update_tag_access:
2081 !
2082 ! If page size is 256m, mask out va[27:22]
2083 !
2084 ldxa [%g0] MMU_ASI_HYP_SCRATCHPAD_REG, %g4 ! %g4 = TSB_CONFIG
2085 and %g4, 0x70, %g4
2086 cmp %g4, 0x50
2087 bne,a %xcc, trap_0x68_not_256m_page
2088 or %g0, %g1, %o1
2089 and %g1, 0x1fc0, %o1
2090 and %g6, 0x1fc0, %g6
2091trap_0x68_not_256m_page:
2092 cmp %g6, %o1 ! Compare TAG
2093 bne,a %xcc, trap_0x68_next_ptr
2094 add %g2, 8, %g2
2095 !
2096 ! At this point, we have got the TTE to be loaded into the TLB.
2097 ! We just need to figure out what physical offset to use.
2098 ! Register %g4 and %g7 are restricted.
2099 !
2100 setx trap_ra_mask, %g5, %g6
2101 ldxa [%g0] MMU_ASI_HYP_SCRATCHPAD_REG, %g5 ! %g5 = TSB_CONFIG
2102 and %g5, 0x100, %g3 ! %g3 has the ranotpa bit
2103 brz,a %g3, trap_0x68_skip_ra
2104 nop
2105 and %g5, 0x70, %g3 ! %g3 = PSIZE
2106 cmp %g3, 0x00
2107 be,a trap_0x68_get_rr_limits
2108 add %g6, 48, %g6
2109 cmp %g3, 0x10
2110 be,a trap_0x68_get_rr_limits
2111 add %g6, 32, %g6
2112 cmp %g3, 0x30
2113 be,a trap_0x68_get_rr_limits
2114 add %g6, 16, %g6
2115trap_0x68_get_rr_limits:
2116 ldda [%g6] 0x24, %g2 ! %g2 = RA_max mask, %g3 = RA_min mask
2117 sllx %g7, 24, %g5
2118 srlx %g5, 37, %g5
2119 sllx %g5, 13, %g5 ! %g5 = RA
2120 or %g5, %g2, %g2 ! %g2 = RA_max
2121 and %g5, %g3, %g3 ! %g3 = RA_min
2122
2123 or %g0, MMU_ASI_REAL_RANGE_0_ADDR, %g1 ! %g1 points to REAL_RANGE_REG
2124trap_0x68_next_rr:
2125 cmp %g1, 0x128
2126 bl,a %xcc, trap_0x68_get_rr
2127 ldxa [%g1] MMU_ASI_REAL_RANGE_REG, %g5 ! %g5 = REAL_RANGE
2128 done
2129trap_0x68_get_rr:
2130 srlx %g5, 63, %g6
2131 brz,a %g6, trap_0x68_next_rr
2132 add %g1, 8, %g1
2133
2134 sllx %g5, 10, %g6 ! %g6 = RR left shift by 10
2135 srlx %g6, 37, %g6
2136 sllx %g6, 13, %g6 ! %g6 = RA_hi
2137 cmp %g6, %g2
2138 bl,a %xcc, trap_0x68_next_rr
2139 add %g1, 8, %g1
2140 sllx %g5, 37, %g6
2141 srlx %g6, 24, %g6 ! %g6 = RA_lo
2142 cmp %g6, %g3
2143 bg,a %xcc, trap_0x68_next_rr
2144 add %g1, 8, %g1
2145 add %g1, 0x100, %g1
2146 ldxa [%g1] MMU_ASI_PHY_OFFSET_REG, %g1 ! %g1 = physical offset
2147 add %g7, %g1, %g7
2148trap_0x68_skip_ra:
2149 stxa %g7, [%g0] MMU_ASI_D_DATA_IN_REG
2150 restore
2151 retry
2152
2153trap_0x68_next_ptr:
2154 cmp %g2, 0x90
2155 bl,a %xcc, trap_0x68_load_tsb_config
2156 add %g3, 8, %g3
2157#ifdef MMU247
2158 done
2159#else
2160 ta HP_BAD_TRAP
2161#endif
2162
2163#ifdef MMU247
2164/*************************************************************************/
2165ext_trap_load_idata_in:
2166 !
2167 ! %i1[43:40] = count, %i7[11:0] = random offset
2168 !
2169 setx hptrap_itte_end, %g1, %g2 ! %g2 = pointer to count
2170 ldx [%g2], %g3 ! %g3 = max count
2171 umul %g3, 16, %g1 ! %g1 = length
2172 sub %g2, %g1, %g1 ! %g1 = pointer to first entry
2173 srlx %i1, 40, %g3
2174 and %g3, 0xf, %g3 ! %g3 = count
2175 brz,a %g3, load_idata_set_count
2176 or %g0, 1, %g3
2177load_idata_set_count:
2178 and %i7, 0x0fff, %i7 ! %i7 = random offset
2179 umul %i7, 16, %i7
2180 add %g1, %i7, %i7 ! %i7 = pointer to random entry
2181 !
2182 ! %g1 = begin marker
2183 ! %g2 = end marker
2184 ! %g3 = number of entries to preload
2185 ! %i7 = pointer to random entry
2186 !
2187load_idata_in_next:
2188 ldda [%i7] ASI_NUCLEUS_QUAD_LDD, %g6 ! %g6 = tag access, %g7 = data
2189 or %g0, 0x30, %g4
2190 stxa %g6, [%g4] MMU_ASI_I_TAG_ACCESS_REG ! write to tag access
2191 stxa %g7, [%g0] MMU_ASI_I_DATA_IN_REG ! write to data in
2192 add %i7, 112, %i7 ! skip 7 entries
2193 cmp %i7, %g2
2194 bcs,a %xcc, load_idata_in_no_wrap
2195 nop
2196 sub %i7, %g2, %i7
2197 add %g1, %i7, %i7 ! wrap %i7
2198load_idata_in_no_wrap:
2199 sub %g3, 1, %g3
2200 brnz,a %g3, load_idata_in_next
2201 nop
2202 done
2203
2204/*************************************************************************/
2205ext_trap_load_ddata_in:
2206 !
2207 ! %i1[43:40] = count, %i7[11:0] = random offset
2208 !
2209 setx hptrap_dtte_end, %g1, %g2 ! %g2 = pointer to count
2210 ldx [%g2], %g3 ! %g3 = max count
2211 umul %g3, 16, %g1 ! %g1 = length
2212 sub %g2, %g1, %g1 ! %g1 = pointer to first entry
2213 srlx %i1, 40, %g3
2214 and %g3, 0xf, %g3 ! %g3 = count
2215 brz,a %g3, load_ddata_set_count
2216 or %g0, 1, %g3
2217load_ddata_set_count:
2218 and %i7, 0x0fff, %i7 ! %i7 = random offset
2219 umul %i7, 16, %i7
2220 add %g1, %i7, %i7 ! %i7 = pointer to random entry
2221 !
2222 ! %g1 = begin marker
2223 ! %g2 = end marker
2224 ! %g3 = number of entries to preload
2225 ! %i7 = pointer to random entry
2226 !
2227load_ddata_in_next:
2228 ldda [%i7] ASI_NUCLEUS_QUAD_LDD, %g6 ! %g6 = tag access, %g7 = data
2229 or %g0, 0x30, %g4
2230 stxa %g6, [%g4] MMU_ASI_D_TAG_ACCESS_REG ! write to tag access
2231 stxa %g7, [%g0] MMU_ASI_D_DATA_IN_REG ! write to data in
2232 add %i7, 112, %i7 ! skip 7 entries
2233 cmp %i7, %g2
2234 bcs,a %xcc, load_ddata_in_no_wrap
2235 nop
2236 sub %i7, %g2, %i7
2237 add %g1, %i7, %i7 ! wrap %i7
2238load_ddata_in_no_wrap:
2239 sub %g3, 1, %g3
2240 brnz,a %g3, load_ddata_in_next
2241 nop
2242 done
2243
2244/*************************************************************************/
2245ext_trap_load_idata_access:
2246 !
2247 ! %i7[9:3] = index , %i7[2:0] = count, %i7[11:0] = random offset
2248 !
2249 setx hptrap_itte_end, %g1, %g2 ! %g2 = pointer to count
2250 ldx [%g2], %g3 ! %g3 = max count
2251 umul %g3, 16, %g1 ! %g1 = length
2252 sub %g2, %g1, %g1 ! %g1 = pointer to first entry
2253 and %i7, 0x7, %g3 ! %g3 = count
2254 brz,a %g3, load_idata_access_set_count
2255 or %g0, 1, %g3
2256load_idata_access_set_count:
2257 and %i7, 0x05f8, %g5 ! %g5 = Real + index
2258 umul %i7, 16, %i7
2259 add %g1, %i7, %i7 ! %i7 = pointer to random entry
2260 !
2261 ! %g1 = begin marker
2262 ! %g2 = end marker
2263 ! %g3 = number of entries to preload
2264 ! %g5 = index
2265 ! %i7 = pointer to random entry
2266 !
2267load_idata_access_next:
2268 ldda [%i7] ASI_NUCLEUS_QUAD_LDD, %g6 ! %g6 = tag access, %g7 = data
2269 or %g0, 0x30, %g4
2270 stxa %g6, [%g4] MMU_ASI_I_TAG_ACCESS_REG ! write to tag access
2271 stxa %g7, [%g5] MMU_ASI_I_DATA_ACCESS_REG ! write to data access
2272 add %i7, 112, %i7 ! skip 7 entries
2273 cmp %i7, %g2
2274 bcs,a %xcc, load_idata_access_no_wrap
2275 nop
2276 sub %i7, %g2, %i7
2277 add %g1, %i7, %i7 ! wrap %i7
2278load_idata_access_no_wrap:
2279 add %g5, 0x18, %g5 ! increment index by 3
2280 and %g5, 0x5f8, %g5
2281 sub %g3, 1, %g3
2282 brnz,a %g3, load_idata_access_next
2283 nop
2284 done
2285
2286/*************************************************************************/
2287ext_trap_load_ddata_access:
2288 !
2289 ! %i7[9:3] = index , %i7[2:0] = count, %i7[11:0] = random offset
2290 !
2291 setx hptrap_itte_end, %g1, %g2 ! %g2 = pointer to count
2292 ldx [%g2], %g3 ! %g3 = max count
2293 umul %g3, 16, %g1 ! %g1 = length
2294 sub %g2, %g1, %g1 ! %g1 = pointer to first entry
2295 and %i7, 0x7, %g3 ! %g3 = count
2296 brz,a %g3, load_ddata_access_set_count
2297 or %g0, 1, %g3
2298load_ddata_access_set_count:
2299 and %i7, 0x07f8, %g5 ! %g5 = Real + index
2300 umul %i7, 16, %i7
2301 add %g1, %i7, %i7 ! %i7 = pointer to random entry
2302 !
2303 ! %g1 = begin marker
2304 ! %g2 = end marker
2305 ! %g3 = number of entries to preload
2306 ! %g5 = index
2307 ! %i7 = pointer to random entry
2308 !
2309load_ddata_access_next:
2310 ldda [%i7] ASI_NUCLEUS_QUAD_LDD, %g6 ! %g6 = tag access, %g7 = data
2311 or %g0, 0x30, %g4
2312 stxa %g6, [%g4] MMU_ASI_D_TAG_ACCESS_REG ! write to tag access
2313 stxa %g7, [%g5] MMU_ASI_D_DATA_ACCESS_REG ! write to data access
2314 add %i7, 112, %i7 ! skip 7 entries
2315 cmp %i7, %g2
2316 bcs,a %xcc, load_ddata_access_no_wrap
2317 nop
2318 sub %i7, %g2, %i7
2319 add %g1, %i7, %i7 ! wrap %i7
2320load_ddata_access_no_wrap:
2321 add %g5, 0x18, %g5 ! increment index by 3
2322 and %g5, 0x7f8, %g5
2323 sub %g3, 1, %g3
2324 brnz,a %g3, load_ddata_access_next
2325 nop
2326 done
2327
2328!****************************************************************************************
2329! This handler processes the exception based on tid. For each thread, a pointer to a new
2330! code page is used to provide the target of the return address from the done.
2331ext_trap_0x8_begin:
2332 wr %g0, ASI_CORE_ID, %asi
2333 ldxa [ASI_CORE_ID_VA] %asi, %g1
2334 and %g1, 7, %g1 ! %g1 = tid
2335 cmp %g1, 0
2336 bne,a %xcc, ext_trap_0x8_check_tid1
2337 cmp %g1, 1
2338 setx hptrap_user_code_ptrs_0_begin, %g3, %g2
2339 ba ext_trap_0x8_get_ucptr
2340 nop
2341ext_trap_0x8_check_tid1:
2342 bne,a %xcc, ext_trap_0x8_check_tid2
2343 cmp %g1, 2
2344 setx hptrap_user_code_ptrs_1_begin, %g3, %g2
2345 ba ext_trap_0x8_get_ucptr
2346 nop
2347ext_trap_0x8_check_tid2:
2348 bne,a %xcc, ext_trap_0x8_check_tid3
2349 cmp %g1, 3
2350 setx hptrap_user_code_ptrs_2_begin, %g3, %g2
2351 ba ext_trap_0x8_get_ucptr
2352 nop
2353ext_trap_0x8_check_tid3:
2354 bne,a %xcc, ext_trap_0x8_check_tid4
2355 cmp %g1, 4
2356 setx hptrap_user_code_ptrs_3_begin, %g3, %g2
2357 ba ext_trap_0x8_get_ucptr
2358 nop
2359ext_trap_0x8_check_tid4:
2360 bne,a %xcc, ext_trap_0x8_check_tid5
2361 cmp %g1, 5
2362 setx hptrap_user_code_ptrs_4_begin, %g3, %g2
2363 ba ext_trap_0x8_get_ucptr
2364 nop
2365ext_trap_0x8_check_tid5:
2366 bne,a %xcc, ext_trap_0x8_check_tid6
2367 cmp %g1, 6
2368 setx hptrap_user_code_ptrs_5_begin, %g3, %g2
2369 ba ext_trap_0x8_get_ucptr
2370 nop
2371ext_trap_0x8_check_tid6:
2372 bne,a %xcc, ext_trap_0x8_check_tid7
2373 nop
2374 setx hptrap_user_code_ptrs_6_begin, %g3, %g2
2375 ba ext_trap_0x8_get_ucptr
2376 nop
2377ext_trap_0x8_check_tid7:
2378 setx hptrap_user_code_ptrs_7_begin, %g3, %g2
2379ext_trap_0x8_get_ucptr:
2380 ldx [%g2], %g3 ! %g3 = offset to new pointer set
2381 add %g2, %g3, %g3 ! %g3 = pointer to next pointer set
2382 ldx [%g3], %g4 ! %g4 = pointer to new code
2383 cmp %g4, 8
2384 bne,a %xcc, ext_trap_0x8_no_wrap_around
2385 nop
2386 add %g2, 8, %g3
2387 ldx [%g3], %g4 ! %g4 = pointer to new code
2388ext_trap_0x8_no_wrap_around:
2389 ldx [%g3 + 8], %g5 ! %g5 = new offset
2390 stx %g5, [%g2] ! save next offset
2391 ! We are returning to the top of the page except for the first code section
2392 ! This prevents re-initializing loop counter
2393 !add %g4, 32, %g4
2394 wrpr %g4, %tnpc
2395 done
2396
2397/*************************************************************************/
2398.align 32
2399ext_trap_0x9_begin:
2400 setx ext_trap_0x9_cnt, %g1, %g2
2401 ldx [%g2], %g1
2402 addcc %g1, 1, %g1
2403 cmp %g1, MAX_TRAP_COUNT
2404 bl,a %xcc, ext_trap_0x9_continue
2405 stx %g1, [%g2]
2406 ta HP_BAD_TRAP
2407ext_trap_0x9_cnt:
2408 .xword 0
2409ext_trap_0x9_continue:
2410 setx ext_trap_0x8_begin, %g2, %g1
2411 jmp %g1
2412 nop
2413 ta HP_BAD_TRAP
2414
2415/*************************************************************************/
2416ext_trap_0x1b_begin:
2417 /* Get TID */
2418 wr %g0, ASI_CORE_ID, %asi
2419 ldxa [ASI_CORE_ID_VA] %asi, %l7
2420 set 0x7, %g1
2421 and %l7, %g1, %l7 ! %l7 has TID
2422 setx Thr0_trap_occurence_cnt_begin, %g2, %g1
2423 or %g0, NUM_IMPL_TRAPS, %g3
2424 umul %g3, 4, %g2
2425 umul %l7, %g2, %g2 ! %g2 points to thread offset
2426 add %g1, %g2, %g1 ! %g1 points to thread
2427 add %g1, TRAP_0x1B_OFFSET, %g1 ! %g1 points to trap 0x1b occurence count
2428 lduw [%g1], %g2
2429 add %g2, 1, %g2
2430 or %g0, MAX_OCCURENCE_CNT, %g4
2431 cmp %g2, %g4
2432 bge %xcc, clear_occurence_cnt
2433 nop
2434 stw %g2, [%g1]
2435 done
2436
2437/*************************************************************************/
2438.align 32
2439ext_trap_0x31_begin:
2440 setx ext_trap_0x31_cnt, %g1, %g2
2441 ldx [%g2], %g1
2442 addcc %g1, 1, %g1
2443 cmp %g1, MAX_TRAP_COUNT
2444 bl,a %xcc, ext_trap_0x31_continue
2445 stx %g1, [%g2]
2446 ta HP_BAD_TRAP
2447ext_trap_0x31_cnt:
2448 .xword 0
2449ext_trap_0x31_continue:
2450 done
2451
2452/*************************************************************************/
2453clear_occurence_cnt:
2454 stw %g0, [%g1]
2455 add %g1, 4, %g1
2456 sub %g3, 1, %g3
2457 brnz %g3, clear_occurence_cnt
2458 nop
2459 /* %l7 has TID */
2460 setx Thr0_register_initial_values, %i6, %i7
2461 umul %l7, 240, %i6
2462 add %i7, %i6, %i7 ! %i7 points to register values
2463restore_registers:
2464 wrpr 0, %g0, %gl
2465 ldx [%i7 + 0x10], %g2
2466 ldx [%i7 + 0x00], %g3
2467 ldx [%i7 + 0x08], %g4
2468 ldx [%i7 + 0x10], %g5
2469 ldx [%i7 + 0x18], %g6
2470 ldx [%i7 + 0x20], %g7
2471 ldx [%i7 + 0x28], %o0
2472 ldx [%i7 + 0x30], %o1
2473 ldx [%i7 + 0x38], %o2
2474 ldx [%i7 + 0x40], %o3
2475 ldx [%i7 + 0x48], %o4
2476 ldx [%i7 + 0x50], %o5
2477 ldx [%i7 + 0x58], %o6
2478 ldx [%i7 + 0x60], %o7
2479 ldx [%i7 + 0x68], %l0
2480 ldx [%i7 + 0x70], %l1
2481 ldx [%i7 + 0x78], %l2
2482 ldx [%i7 + 0x80], %l3
2483 ldx [%i7 + 0x88], %l4
2484 ldx [%i7 + 0x90], %l5
2485 ldx [%i7 + 0x98], %l6
2486 ldx [%i7 + 0xa0], %l7
2487 ldx [%i7 + 0xa8], %i0
2488 ldx [%i7 + 0xb0], %i1
2489 ldx [%i7 + 0xb8], %i2
2490 ldx [%i7 + 0xc0], %i3
2491 ldx [%i7 + 0xc8], %i4
2492 ldx [%i7 + 0xd0], %i5
2493 ldx [%i7 + 0xd8], %i6
2494 ldx [%i7 + 0xe0], %i7
2495 done
2496
2497#endif
2498
2499function_tsb_ptr_calc:
2500 ! %g1 = VA
2501 ! %g2 = TSB CONFIG REG
2502 ! %i6 + 8 = return address
2503 ! %i7 = TSB pointer
2504 and %g2, 0x0f, %g3 ! %g3 = TSB size
2505 umul %g3, 8, %g3
2506 setx tsb_base_mask, %g4, %g5
2507 ldx [%g5+%g3], %g4 ! %g4 = tsb mask
2508 and %g2, %g4, %i7 ! %i7 = TSB base
2509 and %g2, 0x70, %g4
2510 srlx %g4, 4, %g4 ! %g4 = page size
2511 setx tsb_va_8k_mask, %g5, %g6
2512 brnz,a %g4, test_page_1
2513 add %g6, 0x80, %g6
2514 ldx [%g6 + %g3], %g5 ! %g5 = VA mask
2515 and %g1, %g5, %g7
2516 srlx %g7, 9, %g7
2517 or %i7, %g7, %i7
2518 add %i6, 8, %i6
2519 jmp %i6
2520 nop
2521test_page_1:
2522 sub %g4, 1, %g7
2523 brnz,a %g7, test_page_3
2524 add %g6, 0x80, %g6
2525 ldx [%g6 + %g3], %g5 ! %g5 = VA mask
2526 and %g1, %g5, %g7
2527 srlx %g7, 12, %g7
2528 or %i7, %g7, %i7
2529 add %i6, 8, %i6
2530 jmp %i6
2531 nop
2532test_page_3:
2533 sub %g4, 3, %g7
2534 brnz,a %g7, test_page_5
2535 add %g6, 0x80, %g6
2536 ldx [%g6 + %g3], %g5 ! %g5 = VA mask
2537 and %g1, %g5, %g7
2538 srlx %g7, 18, %g7
2539 or %i7, %g7, %i7
2540 add %i6, 8, %i6
2541 jmp %i6
2542 nop
2543test_page_5:
2544 ldx [%g6 + %g3], %g5 ! %g5 = VA mask
2545 and %g1, %g5, %g7
2546 srlx %g7, 24, %g7
2547 or %i7, %g7, %i7
2548 add %i6, 8, %i6
2549 jmp %i6
2550 nop
2551
2552/*************************************************************************/
2553
2554attr_data {
2555 Name=.HPTRAPS_EXT_SECT,
2556 hypervisor
2557}
2558
2559.data
2560trap_ra_mask:
2561 .xword 0x00000fffe000
2562 .xword 0x000000000000
2563 .xword 0x0000003fe000
2564 .xword 0x000000000000
2565 .xword 0x00000000e000
2566 .xword 0x000000000000
2567 .xword 0x000000000000
2568 .xword 0x000000000000
2569
2570.global sem_data
2571sem_data:
2572 .xword 0x0fff
2573 .xword 0x0
2574
2575! TSB mask
2576.global tsb_base_mask
2577.global tsb_va_8k_mask
2578.global tsb_va_64k_mask
2579.global tsb_va_4m_mask
2580.global tsb_va_256m_mask
2581.global tsb_addresses_zero
2582.global tsb_addresses_non_zero
2583
2584tsb_base_mask:
2585.xword 0x000000ffffffe000
2586.xword 0x000000ffffffc000
2587.xword 0x000000ffffff8000
2588.xword 0x000000ffffff0000
2589.xword 0x000000fffffe0000
2590.xword 0x000000fffffc0000
2591.xword 0x000000fffff80000
2592.xword 0x000000fffff00000
2593.xword 0x000000ffffe00000
2594.xword 0x000000ffffc00000
2595.xword 0x000000ffff800000
2596.xword 0x000000ffff000000
2597.xword 0x000000fffe000000
2598.xword 0x000000fffc000000
2599.xword 0x000000fff8000000
2600.xword 0x000000fff0000000
2601tsb_va_8k_mask:
2602.xword 0x00000000003fe000
2603.xword 0x00000000007fe000
2604.xword 0x0000000000ffe000
2605.xword 0x0000000001ffe000
2606.xword 0x0000000003ffe000
2607.xword 0x0000000007ffe000
2608.xword 0x000000000fffe000
2609.xword 0x000000001fffe000
2610.xword 0x000000003fffe000
2611.xword 0x000000007fffe000
2612.xword 0x00000000ffffe000
2613.xword 0x00000001ffffe000
2614.xword 0x00000003ffffe000
2615.xword 0x00000007ffffe000
2616.xword 0x0000000fffffe000
2617.xword 0x0000001fffffe000
2618tsb_va_64k_mask:
2619.xword 0x0000000001ff0000
2620.xword 0x0000000003ff0000
2621.xword 0x0000000007ff0000
2622.xword 0x000000000fff0000
2623.xword 0x000000001fff0000
2624.xword 0x000000003fff0000
2625.xword 0x000000007fff0000
2626.xword 0x00000000ffff0000
2627.xword 0x00000001ffff0000
2628.xword 0x00000003ffff0000
2629.xword 0x00000007ffff0000
2630.xword 0x0000000fffff0000
2631.xword 0x0000001fffff0000
2632.xword 0x0000003fffff0000
2633.xword 0x0000007fffff0000
2634.xword 0x000000ffffff0000
2635tsb_va_4m_mask:
2636.xword 0x000000007fc00000
2637.xword 0x00000000ffc00000
2638.xword 0x00000001ffc00000
2639.xword 0x00000003ffc00000
2640.xword 0x00000007ffc00000
2641.xword 0x0000000fffc00000
2642.xword 0x0000001fffc00000
2643.xword 0x0000003fffc00000
2644.xword 0x0000007fffc00000
2645.xword 0x000000ffffc00000
2646.xword 0x000001ffffc00000
2647.xword 0x000003ffffc00000
2648.xword 0x000007ffffc00000
2649.xword 0x00000fffffc00000
2650.xword 0x00001fffffc00000
2651.xword 0x00003fffffc00000
2652tsb_va_256m_mask:
2653.xword 0x0000001fe0000000
2654.xword 0x0000003fe0000000
2655.xword 0x0000007fe0000000
2656.xword 0x000000ffe0000000
2657.xword 0x000001ffe0000000
2658.xword 0x000003ffe0000000
2659.xword 0x000007ffe0000000
2660.xword 0x00000fffe0000000
2661.xword 0x00001fffe0000000
2662.xword 0x00003fffe0000000
2663.xword 0x00007fffe0000000
2664.xword 0x0000ffffe0000000
2665.xword 0x0001ffffe0000000
2666.xword 0x0003ffffe0000000
2667.xword 0x0007ffffe0000000
2668.xword 0x000fffffe0000000
2669
2670tsb_addresses_zero:
2671.xword 0x10
2672.xword 0x18
2673.xword 0x20
2674.xword 0x28
2675.xword 0x30
2676.xword 0x38
2677.xword 0x40
2678.xword 0x48
2679.xword 0x0ff
2680
2681tsb_addresses_non_zero:
2682.xword 0x30
2683.xword 0x38
2684.xword 0x40
2685.xword 0x48
2686.xword 0x10
2687.xword 0x18
2688.xword 0x20
2689.xword 0x28
2690.xword 0x0ff
2691
Full OpenSPARC design & verification tarball including full HDL.