projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: mmu_hred.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define MAX_TRAP_COUNT 80 | |
| 39 | #define HV_RED_TEXT_PA 0x10000 | |
| 40 | #define HV_RED_DATA_PA 0x20000 | |
| 41 | #define HPTRAP_TEXT_PA 0x80000 | |
| 42 | #define HPTRAPS_EXT_TEXT_PA 0x90000 | |
| 43 | #define HPTRAPS_EXT_DATA_PA 0x98000 | |
| 44 | #define P_GOOD_TRAP 0x0 | |
| 45 | #define P_BAD_TRAP 0x1 | |
| 46 | #define HP_GOOD_TRAP 0xa0 | |
| 47 | #define HP_BAD_TRAP 0xa1 | |
| 48 | #define EXIT_GOOD ta P_GOOD_TRAP; nop | |
| 49 | #define EXIT_BAD ta P_BAD_TRAP; nop | |
| 50 | #define REALRANGE_LO_MASK 0x0000000007ffffff | |
| 51 | #define REALRANGE_HI_MASK 0x003ffffff8000000 | |
| 52 | #define RANOTPA_MASK 0x100 | |
| 53 | #define SUN4V_MASK 0x080 | |
| 54 | #define TTE_RA_MASK 0x000000ffffffe000 | |
| 55 | #define RETURN_FROM_SUPERVISOR0 rdpr %pstate, %i6 ; \ | |
| 56 | wrpr %g0, %gl ; \ | |
| 57 | jmp %i7 ; \ | |
| 58 | wrpr %i6, 4, %pstate ; | |
| 59 | #define RETURN_FROM_SUPERVISOR1 wrpr %i7, %tnpc ; \ | |
| 60 | done ; | |
| 61 | // Scratchpad Registers | |
| 62 | #define MMU_ASI_HYP_SCRATCHPAD_REG 0x4f | |
| 63 | ||
| 64 | // Real Range Registers | |
| 65 | #define MMU_ASI_REAL_RANGE_REG 0x52 | |
| 66 | #define MMU_ASI_REAL_RANGE_0_ADDR 0x108 | |
| 67 | #define MMU_ASI_REAL_RANGE_1_ADDR 0x110 | |
| 68 | #define MMU_ASI_REAL_RANGE_2_ADDR 0x118 | |
| 69 | #define MMU_ASI_REAL_RANGE_3_ADDR 0x120 | |
| 70 | ||
| 71 | // Physical Offset Registers | |
| 72 | #define MMU_ASI_PHY_OFFSET_REG 0x52 | |
| 73 | #define MMU_ASI_PHY_OFFSET_0_ADDR 0x208 | |
| 74 | #define MMU_ASI_PHY_OFFSET_1_ADDR 0x210 | |
| 75 | #define MMU_ASI_PHY_OFFSET_2_ADDR 0x218 | |
| 76 | #define MMU_ASI_PHY_OFFSET_3_ADDR 0x220 | |
| 77 | ||
| 78 | // ITLB Tag and Data Registers | |
| 79 | #define MMU_ASI_ITLB_PROBE_REG 0x53 | |
| 80 | #define MMU_ASI_ITSB_TAG_TARGET_REG 0x50 | |
| 81 | #define MMU_ASI_I_TAG_ACCESS_REG 0x50 | |
| 82 | #define MMU_ASI_I_TAG_ACCESS_ADDR 0x30 | |
| 83 | #define MMU_ASI_I_DATA_IN_REG 0x54 | |
| 84 | #define MMU_ASI_I_DATA_ACCESS_REG 0x55 | |
| 85 | #define MMU_ASI_I_TAG_READ_REG 0x56 | |
| 86 | ||
| 87 | // Demaps | |
| 88 | #define MMU_ASI_I_DEMAP 0x57 | |
| 89 | #define MMU_ASI_D_DEMAP 0x5f | |
| 90 | ||
| 91 | // DTLB Tag and Data Registers | |
| 92 | #define MMU_ASI_DTSB_TAG_TARGET_REG 0x58 | |
| 93 | #define MMU_ASI_D_TAG_ACCESS_REG 0x58 | |
| 94 | #define MMU_ASI_D_TAG_ACCESS_ADDR 0x30 | |
| 95 | #define MMU_ASI_D_DATA_IN_REG 0x5c | |
| 96 | #define MMU_ASI_D_DATA_ACCESS_REG 0x5d | |
| 97 | #define MMU_ASI_D_TAG_READ_REG 0x5e | |
| 98 | ||
| 99 | // TSB Configs | |
| 100 | #define MMU_ASI_TSB_CONFIG_REG 0x54 | |
| 101 | #define MMU_ASI_Z_CTX_TSB_CONFIG_0_ADDR 0x10 | |
| 102 | #define MMU_ASI_Z_CTX_TSB_CONFIG_1_ADDR 0x18 | |
| 103 | #define MMU_ASI_Z_CTX_TSB_CONFIG_2_ADDR 0x20 | |
| 104 | #define MMU_ASI_Z_CTX_TSB_CONFIG_3_ADDR 0x28 | |
| 105 | #define MMU_ASI_NZ_CTX_TSB_CONFIG_0_ADDR 0x30 | |
| 106 | #define MMU_ASI_NZ_CTX_TSB_CONFIG_1_ADDR 0x38 | |
| 107 | #define MMU_ASI_NZ_CTX_TSB_CONFIG_2_ADDR 0x40 | |
| 108 | #define MMU_ASI_NZ_CTX_TSB_CONFIG_3_ADDR 0x48 | |
| 109 | ||
| 110 | // TSB Pointers | |
| 111 | #define MMU_ASI_TSB_PTR_REG 0x54 | |
| 112 | #define MMU_ASI_ITSB_PTR_0_ADDR 0x50 | |
| 113 | #define MMU_ASI_ITSB_PTR_1_ADDR 0x58 | |
| 114 | #define MMU_ASI_ITSB_PTR_2_ADDR 0x60 | |
| 115 | #define MMU_ASI_ITSB_PTR_3_ADDR 0x68 | |
| 116 | #define MMU_ASI_DTSB_PTR_0_ADDR 0x70 | |
| 117 | #define MMU_ASI_DTSB_PTR_1_ADDR 0x78 | |
| 118 | #define MMU_ASI_DTSB_PTR_2_ADDR 0x80 | |
| 119 | #define MMU_ASI_DTSB_PTR_3_ADDR 0x88 | |
| 120 | ||
| 121 | // Contexts | |
| 122 | #define MMU_ASI_CONTEXT_REG 0x21 | |
| 123 | #define MMU_ASI_PRIMARY_CONTEXT_0_ADDR 0x8 | |
| 124 | #define MMU_ASI_PRIMARY_CONTEXT_1_ADDR 0x108 | |
| 125 | #define MMU_ASI_SECONDARY_CONTEXT_0_ADDR 0x10 | |
| 126 | #define MMU_ASI_SECONDARY_CONTEXT_1_ADDR 0x110 | |
| 127 | ||
| 128 | // ASI Load/Store | |
| 129 | #define MMU_ASI_AS_IF_USER_PRIMARY 0x10 | |
| 130 | #define MMU_ASI_AS_IF_USER_SECONDARY 0x11 | |
| 131 | #define MMU_ASI_REAL_MEM 0x14 | |
| 132 | #define MMU_ASI_REAL_IO 0x15 | |
| 133 | #define MMU_ASI_BLOCK_AS_IF_USER_PRIMARY 0x16 | |
| 134 | #define MMU_ASI_BLOCK_AS_IF_USER_SECONDARY 0x17 | |
| 135 | #define MMU_ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 | |
| 136 | #define MMU_ASI_AS_IF_USER_SECONDARY_LITTLE 0x19 | |
| 137 | #define MMU_ASI_REAL_MEM_LITTLE 0x1C | |
| 138 | #define MMU_ASI_REAL_IO_LITTLE 0x1D | |
| 139 | #define MMU_ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x1E | |
| 140 | #define MMU_ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F | |
| 141 | #define MMU_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_PRIMARY 0x22 | |
| 142 | #define MMU_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_SECONDARY 0x23 | |
| 143 | #define MMU_ASI_QUAD_LDD 0x24 | |
| 144 | #define MMU_ASI_QUAD_LDD_REAL 0x26 | |
| 145 | #define MMU_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD 0x27 | |
| 146 | #define MMU_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_PRIMARY_LITTLE 0x2A | |
| 147 | #define MMU_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_SECONDARY_LITTLE 0x2B | |
| 148 | #define MMU_ASI_QUAD_LDD_LITTLE 0x2C | |
| 149 | #define MMU_ASI_QUAD_LDD_REAL_LITTLE 0x2E | |
| 150 | #define MMU_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD_LITTLE 0x2F | |
| 151 | #define MMU_ASI_SECONDARY 0x81 | |
| 152 | #define MMU_ASI_PRIMARY_NO_FAULT 0x82 | |
| 153 | #define MMU_ASI_SECONDARY_NO_FAULT 0x83 | |
| 154 | #define MMU_ASI_PRIMARY_LITTLE 0x88 | |
| 155 | #define MMU_ASI_SECONDARY_LITTLE 0x89 | |
| 156 | #define MMU_ASI_PRIMARY_NO_FAULT_LITTLE 0x8A | |
| 157 | #define MMU_ASI_SECONDARY_NO_FAULT_LITTLE 0x8B | |
| 158 | #define MMU_ASI_BLK_COMMIT_P 0xE0 | |
| 159 | #define MMU_ASI_BLK_COMMIT_S 0xE1 | |
| 160 | #define MMU_ASI_BLK_INIT_ST_QUAD_LDD_PRIMARY 0xE2 | |
| 161 | #define MMU_ASI_BLK_INIT_ST_QUAD_LDD_SECONDARY 0xE3 | |
| 162 | #define MMU_ASI_BLK_INIT_ST_QUAD_LDD_PRIMARY_LITTLE 0xEA | |
| 163 | #define MMU_ASI_BLK_INIT_ST_QUAD_LDD_SECONDARY_LITTLE 0xEB | |
| 164 | #define MMU_ASI_BLK_P 0xF0 | |
| 165 | #define MMU_ASI_BLK_S 0xF1 | |
| 166 | #define MMU_ASI_BLK_PL 0xF8 | |
| 167 | #define MMU_ASI_BLK_SL 0xF9 | |
| 168 | ||
| 169 | // User level hooks | |
| 170 | #define IDEMAP_ALL ta PTRAP_I_DEMAP_ALL | |
| 171 | #define IDEMAP_PCTX ta PTRAP_I_DEMAP_PCTX | |
| 172 | #define IDEMAP_NCTX ta PTRAP_I_DEMAP_NCTX | |
| 173 | #define IDEMAP_PAGE ta PTRAP_I_DEMAP_PAGE | |
| 174 | #define IDEMAP_RPAGE ta PTRAP_I_DEMAP_RPAGE | |
| 175 | ||
| 176 | #define DDEMAP_ALL ta PTRAP_D_DEMAP_ALL | |
| 177 | #define DDEMAP_PCTX ta PTRAP_D_DEMAP_PCTX | |
| 178 | #define DDEMAP_SCTX ta PTRAP_D_DEMAP_SCTX | |
| 179 | #define DDEMAP_NCTX ta PTRAP_D_DEMAP_NCTX | |
| 180 | #define DDEMAP_PAGE ta PTRAP_D_DEMAP_PAGE | |
| 181 | #define DDEMAP_RPAGE ta PTRAP_D_DEMAP_RPAGE | |
| 182 | ||
| 183 | #define DO_BRANCH or %g1, %g0, %i7 ; ta PTRAP_REDIRECT | |
| 184 | #define CHANGE_PID ta PTRAP_CHANGE_PID | |
| 185 | #define INCR_TSB_SIZE ta PTRAP_INCR_TSB_SIZE | |
| 186 | #define REAL_MEM_LD ta PTRAP_REAL_MEM_LD | |
| 187 | #define REAL_MEM_LD_LITTLE ta PTRAP_REAL_MEM_LD_LITTLE | |
| 188 | #define REAL_MEM_QUAD_LD ta PTRAP_REAL_MEM_QUAD_LD | |
| 189 | #define REAL_MEM_QUAD_LD_LITTLE ta PTRAP_REAL_MEM_QUAD_LD_LITTLE | |
| 190 | #define CLEAR_LSU_IMMU ta PTRAP_CLEAR_LSU_IMMU | |
| 191 | #define CLEAR_LSU_DMMU ta PTRAP_CLEAR_LSU_DMMU | |
| 192 | #define DELAY_LOOP ta PTRAP_DELAY_LOOP | |
| 193 | #define SEM_LOCK ta PTRAP_SEM_LOCK | |
| 194 | #define SEM_RELEASE ta PTRAP_SEM_RELEASE | |
| 195 | #define SEM_GET ta PTRAP_SEM_GET | |
| 196 | #define SEM_SET ta PTRAP_SEM_SET | |
| 197 | #define GOTO_SUPERVISOR0 ta PTRAP_GOTO_SUPERVISOR0 | |
| 198 | #define GOTO_SUPERVISOR1 ta PTRAP_GOTO_SUPERVISOR1 | |
| 199 | #define IDEMAP_ALL_PAGES ta PTRAP_I_DEMAP_ALL_PAGES | |
| 200 | #define IDEMAP_ALL_RPAGES ta PTRAP_I_DEMAP_ALL_RPAGES | |
| 201 | #define DDEMAP_ALL_PAGES ta PTRAP_D_DEMAP_ALL_PAGES | |
| 202 | #define DDEMAP_ALL_RPAGES ta PTRAP_D_DEMAP_ALL_RPAGES | |
| 203 | #define ACCESS_ITSB_PTR ta PTRAP_ACCESS_ITSB_PTR | |
| 204 | #define ACCESS_DTSB_PTR ta PTRAP_ACCESS_DTSB_PTR | |
| 205 | #define TOGGLE_LSU_IM ta PTRAP_TOGGLE_LSU_IM | |
| 206 | #define TOGGLE_LSU_DM ta PTRAP_TOGGLE_LSU_DM | |
| 207 | #define LOAD_IDATA_IN ta PTRAP_LOAD_IDATA_IN | |
| 208 | #define LOAD_DDATA_IN ta PTRAP_LOAD_DDATA_IN | |
| 209 | #define READ_IDATA_ACCESS ta PTRAP_READ_IDATA_ACCESS | |
| 210 | #define READ_DDATA_ACCESS ta PTRAP_READ_DDATA_ACCESS | |
| 211 | #define USER_TRAP ta PTRAP_USER_TRAP | |
| 212 | #define LOAD_IDATA_ACCESS ta PTRAP_LOAD_IDATA_ACCESS | |
| 213 | #define LOAD_DDATA_ACCESS ta PTRAP_LOAD_DDATA_ACCESS | |
| 214 | #define ITLB_PROBE ta PTRAP_ITLB_PROBE | |
| 215 | #define TOGGLE_HWTW_DEMAP ta PTRAP_TOGGLE_HWTW_DEMAP | |
| 216 | #define ITLB_TAG_READ ta PTRAP_ITLB_TAG_READ | |
| 217 | #define DTLB_TAG_READ ta PTRAP_DTLB_TAG_READ | |
| 218 | ||
| 219 | #define PTRAP_I_DEMAP_ALL 0x10 | |
| 220 | #define PTRAP_I_DEMAP_PCTX 0x11 | |
| 221 | #define PTRAP_I_DEMAP_NCTX 0x13 | |
| 222 | #define PTRAP_I_DEMAP_PAGE 0x14 | |
| 223 | #define PTRAP_I_DEMAP_RPAGE 0x15 | |
| 224 | #define PTRAP_D_DEMAP_ALL 0x17 | |
| 225 | #define PTRAP_D_DEMAP_PCTX 0x18 | |
| 226 | #define PTRAP_D_DEMAP_SCTX 0x19 | |
| 227 | #define PTRAP_D_DEMAP_NCTX 0x1a | |
| 228 | #define PTRAP_D_DEMAP_PAGE 0x1b | |
| 229 | #define PTRAP_D_DEMAP_RPAGE 0x1c | |
| 230 | #define PTRAP_REDIRECT 0x20 | |
| 231 | #define PTRAP_CHANGE_PID 0x21 | |
| 232 | #define PTRAP_INCR_TSB_SIZE 0x22 | |
| 233 | #define PTRAP_REAL_MEM_LD 0x23 | |
| 234 | #define PTRAP_REAL_MEM_LD_LITTLE 0x24 | |
| 235 | #define PTRAP_REAL_MEM_QUAD_LD 0x25 | |
| 236 | #define PTRAP_REAL_MEM_QUAD_LD_LITTLE 0x26 | |
| 237 | #define PTRAP_CLEAR_LSU_IMMU 0x27 | |
| 238 | #define PTRAP_CLEAR_LSU_DMMU 0x28 | |
| 239 | #define PTRAP_DELAY_LOOP 0x29 | |
| 240 | #define PTRAP_SEM_LOCK 0x2a | |
| 241 | #define PTRAP_SEM_RELEASE 0x2b | |
| 242 | #define PTRAP_SEM_GET 0x2c | |
| 243 | #define PTRAP_SEM_SET 0x2d | |
| 244 | #define PTRAP_GOTO_SUPERVISOR0 0x2e | |
| 245 | #define PTRAP_GOTO_SUPERVISOR1 0x2f | |
| 246 | #define PTRAP_I_DEMAP_ALL_PAGES 0x30 | |
| 247 | #define PTRAP_I_DEMAP_ALL_RPAGES 0x31 | |
| 248 | #define PTRAP_D_DEMAP_ALL_PAGES 0x32 | |
| 249 | #define PTRAP_D_DEMAP_ALL_RPAGES 0x33 | |
| 250 | #define PTRAP_ACCESS_ITSB_PTR 0x34 | |
| 251 | #define PTRAP_ACCESS_DTSB_PTR 0x35 | |
| 252 | #define PTRAP_TOGGLE_LSU_IM 0x36 | |
| 253 | #define PTRAP_TOGGLE_LSU_DM 0x37 | |
| 254 | #define PTRAP_LOAD_IDATA_IN 0x38 | |
| 255 | #define PTRAP_LOAD_DDATA_IN 0x39 | |
| 256 | #define PTRAP_READ_IDATA_ACCESS 0x3a | |
| 257 | #define PTRAP_READ_DDATA_ACCESS 0x3b | |
| 258 | #define PTRAP_USER_TRAP 0x3c | |
| 259 | #define PTRAP_LOAD_IDATA_ACCESS 0x3d | |
| 260 | #define PTRAP_LOAD_DDATA_ACCESS 0x3e | |
| 261 | #define PTRAP_ITLB_PROBE 0x3f | |
| 262 | #define PTRAP_TOGGLE_HWTW_DEMAP 0x40 | |
| 263 | #define PTRAP_ITLB_TAG_READ 0x41 | |
| 264 | #define PTRAP_DTLB_TAG_READ 0x42 | |
| 265 | ||
| 266 | // Supervisor level hooks | |
| 267 | #define P_IDEMAP_ALL ta HPTRAP_I_DEMAP_ALL | |
| 268 | #define P_IDEMAP_PCTX ta HPTRAP_I_DEMAP_PCTX | |
| 269 | #define P_IDEMAP_NCTX ta HPTRAP_I_DEMAP_NCTX | |
| 270 | #define P_IDEMAP_PAGE ta HPTRAP_I_DEMAP_PAGE | |
| 271 | #define P_IDEMAP_RPAGE ta HPTRAP_I_DEMAP_RPAGE | |
| 272 | ||
| 273 | #define P_DDEMAP_ALL ta HPTRAP_D_DEMAP_ALL | |
| 274 | #define P_DDEMAP_PCTX ta HPTRAP_D_DEMAP_PCTX | |
| 275 | #define P_DDEMAP_SCTX ta HPTRAP_D_DEMAP_SCTX | |
| 276 | #define P_DDEMAP_NCTX ta HPTRAP_D_DEMAP_NCTX | |
| 277 | #define P_DDEMAP_PAGE ta HPTRAP_D_DEMAP_PAGE | |
| 278 | #define P_DDEMAP_RPAGE ta HPTRAP_D_DEMAP_RPAGE | |
| 279 | ||
| 280 | #define P_IDEMAP_ALL_PAGES ta HPTRAP_I_DEMAP_ALL_PAGES | |
| 281 | #define P_IDEMAP_ALL_RPAGES ta HPTRAP_I_DEMAP_ALL_RPAGES | |
| 282 | #define P_DDEMAP_ALL_PAGES ta HPTRAP_D_DEMAP_ALL_PAGES | |
| 283 | #define P_DDEMAP_ALL_RPAGES ta HPTRAP_D_DEMAP_ALL_RPAGES | |
| 284 | #define P_ACCESS_ITSB_PTR ta HPTRAP_ACCESS_ITSB_PTR | |
| 285 | #define P_ACCESS_DTSB_PTR ta HPTRAP_ACCESS_DTSB_PTR | |
| 286 | #define P_TOGGLE_LSU_IM ta HPTRAP_TOGGLE_LSU_IM | |
| 287 | #define P_TOGGLE_LSU_DM ta HPTRAP_TOGGLE_LSU_DM | |
| 288 | #define P_LOAD_IDATA_IN ta HPTRAP_LOAD_IDATA_IN | |
| 289 | #define P_LOAD_DDATA_IN ta HPTRAP_LOAD_DDATA_IN | |
| 290 | #define P_READ_IDATA_ACCESS ta HPTRAP_READ_IDATA_ACCESS | |
| 291 | #define P_READ_DDATA_ACCESS ta HPTRAP_READ_DDATA_ACCESS | |
| 292 | #define P_LOAD_IDATA_ACCESS ta HPTRAP_LOAD_IDATA_ACCESS | |
| 293 | #define P_LOAD_DDATA_ACCESS ta HPTRAP_LOAD_DDATA_ACCESS | |
| 294 | #define P_ITLB_PROBE ta HPTRAP_ITLB_PROBE | |
| 295 | #define P_TOGGLE_HWTW_DEMAP ta HPTRAP_TOGGLE_HWTW_DEMAP | |
| 296 | #define P_ITLB_TAG_READ ta HPTRAP_ITLB_TAG_READ | |
| 297 | #define P_DTLB_TAG_READ ta HPTRAP_DTLB_TAG_READ | |
| 298 | ||
| 299 | // Hypervisor trap types | |
| 300 | #define HPTRAP_I_DEMAP_ALL 0x80 | |
| 301 | #define HPTRAP_I_DEMAP_PCTX 0x81 | |
| 302 | #define HPTRAP_I_DEMAP_NCTX 0x83 | |
| 303 | #define HPTRAP_I_DEMAP_PAGE 0x84 | |
| 304 | #define HPTRAP_I_DEMAP_RPAGE 0x85 | |
| 305 | #define HPTRAP_D_DEMAP_ALL 0x87 | |
| 306 | #define HPTRAP_D_DEMAP_PCTX 0x88 | |
| 307 | #define HPTRAP_D_DEMAP_SCTX 0x89 | |
| 308 | #define HPTRAP_D_DEMAP_NCTX 0x8a | |
| 309 | #define HPTRAP_D_DEMAP_PAGE 0x8b | |
| 310 | #define HPTRAP_D_DEMAP_RPAGE 0x8c | |
| 311 | #define HPTRAP_CHANGE_PID 0x91 | |
| 312 | #define HPTRAP_INCR_TSB_SIZE 0x92 | |
| 313 | #define HPTRAP_CLEAR_LSU_IMMU 0x93 | |
| 314 | #define HPTRAP_CLEAR_LSU_DMMU 0x94 | |
| 315 | #define HPTRAP_DELAY_LOOP 0x95 | |
| 316 | #define HPTRAP_SEM_LOCK 0x96 | |
| 317 | #define HPTRAP_SEM_RELEASE 0x97 | |
| 318 | #define HPTRAP_SEM_GET 0x98 | |
| 319 | #define HPTRAP_SEM_SET 0x99 | |
| 320 | #define HPTRAP_GOTO_SUPERVISOR0 0x9a | |
| 321 | #define HPTRAP_GOTO_SUPERVISOR1 0x9b | |
| 322 | #define HPTRAP_I_DEMAP_ALL_PAGES 0x9c | |
| 323 | #define HPTRAP_I_DEMAP_ALL_RPAGES 0x9d | |
| 324 | #define HPTRAP_D_DEMAP_ALL_PAGES 0x9e | |
| 325 | #define HPTRAP_D_DEMAP_ALL_RPAGES 0x9f | |
| 326 | #define HPTRAP_ACCESS_ITSB_PTR 0xa2 /* a0=good_trap, a1=bad_trap */ | |
| 327 | #define HPTRAP_ACCESS_DTSB_PTR 0xa3 | |
| 328 | #define HPTRAP_TOGGLE_LSU_IM 0xa4 | |
| 329 | #define HPTRAP_TOGGLE_LSU_DM 0xa5 | |
| 330 | #define HPTRAP_LOAD_IDATA_IN 0xa6 | |
| 331 | #define HPTRAP_LOAD_DDATA_IN 0xa7 | |
| 332 | #define HPTRAP_READ_IDATA_ACCESS 0xa8 | |
| 333 | #define HPTRAP_READ_DDATA_ACCESS 0xa9 | |
| 334 | #define HPTRAP_USER_TRAP 0xaa | |
| 335 | #define HPTRAP_LOAD_IDATA_ACCESS 0xab | |
| 336 | #define HPTRAP_LOAD_DDATA_ACCESS 0xac | |
| 337 | #define HPTRAP_ITLB_PROBE 0xad | |
| 338 | #define HPTRAP_TOGGLE_HWTW_DEMAP 0xae | |
| 339 | #define HPTRAP_ITLB_TAG_READ 0xaf | |
| 340 | #define HPTRAP_DTLB_TAG_READ 0xb0 | |
| 341 | #define HPTRAP_PRIV_OPCODE 0xb1 | |
| 342 | ||
| 343 | #define MAX_OCCURENCE_CNT 10 | |
| 344 | #define NUM_IMPL_TRAPS 6 /* number of implemented traps */ | |
| 345 | #define TRAP_0x9_OFFSET 0 | |
| 346 | #define TRAP_0xB_OFFSET 4 | |
| 347 | #define TRAP_0x1B_OFFSET 8 | |
| 348 | #define TRAP_0x2E_OFFSET 0xc | |
| 349 | #define TRAP_0x31_OFFSET 0x10 | |
| 350 | #define TRAP_0x6C_OFFSET 0x14 | |
| 351 | ||
| 352 | MIDAS_TSB thr0_z_ctx_tsb_0 THR0_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 353 | MIDAS_TSB thr0_z_ctx_tsb_1 THR0_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 354 | MIDAS_TSB thr0_z_ctx_tsb_2 THR0_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 355 | MIDAS_TSB thr0_z_ctx_tsb_3 THR0_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 356 | MIDAS_TSB thr0_nz_ctx_tsb_0 THR0_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 357 | MIDAS_TSB thr0_nz_ctx_tsb_1 THR0_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 358 | MIDAS_TSB thr0_nz_ctx_tsb_2 THR0_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 359 | MIDAS_TSB thr0_nz_ctx_tsb_3 THR0_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 360 | ||
| 361 | MIDAS_TSB thr1_z_ctx_tsb_0 THR1_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 362 | MIDAS_TSB thr1_z_ctx_tsb_1 THR1_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 363 | MIDAS_TSB thr1_z_ctx_tsb_2 THR1_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 364 | MIDAS_TSB thr1_z_ctx_tsb_3 THR1_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 365 | MIDAS_TSB thr1_nz_ctx_tsb_0 THR1_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 366 | MIDAS_TSB thr1_nz_ctx_tsb_1 THR1_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 367 | MIDAS_TSB thr1_nz_ctx_tsb_2 THR1_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 368 | MIDAS_TSB thr1_nz_ctx_tsb_3 THR1_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 369 | ||
| 370 | MIDAS_TSB thr2_z_ctx_tsb_0 THR2_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 371 | MIDAS_TSB thr2_z_ctx_tsb_1 THR2_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 372 | MIDAS_TSB thr2_z_ctx_tsb_2 THR2_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 373 | MIDAS_TSB thr2_z_ctx_tsb_3 THR2_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 374 | MIDAS_TSB thr2_nz_ctx_tsb_0 THR2_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 375 | MIDAS_TSB thr2_nz_ctx_tsb_1 THR2_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 376 | MIDAS_TSB thr2_nz_ctx_tsb_2 THR2_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 377 | MIDAS_TSB thr2_nz_ctx_tsb_3 THR2_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 378 | ||
| 379 | MIDAS_TSB thr3_z_ctx_tsb_0 THR3_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 380 | MIDAS_TSB thr3_z_ctx_tsb_1 THR3_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 381 | MIDAS_TSB thr3_z_ctx_tsb_2 THR3_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 382 | MIDAS_TSB thr3_z_ctx_tsb_3 THR3_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 383 | MIDAS_TSB thr3_nz_ctx_tsb_0 THR3_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 384 | MIDAS_TSB thr3_nz_ctx_tsb_1 THR3_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 385 | MIDAS_TSB thr3_nz_ctx_tsb_2 THR3_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 386 | MIDAS_TSB thr3_nz_ctx_tsb_3 THR3_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 387 | ||
| 388 | MIDAS_TSB thr4_z_ctx_tsb_0 THR4_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 389 | MIDAS_TSB thr4_z_ctx_tsb_1 THR4_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 390 | MIDAS_TSB thr4_z_ctx_tsb_2 THR4_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 391 | MIDAS_TSB thr4_z_ctx_tsb_3 THR4_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 392 | MIDAS_TSB thr4_nz_ctx_tsb_0 THR4_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 393 | MIDAS_TSB thr4_nz_ctx_tsb_1 THR4_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 394 | MIDAS_TSB thr4_nz_ctx_tsb_2 THR4_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 395 | MIDAS_TSB thr4_nz_ctx_tsb_3 THR4_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 396 | ||
| 397 | MIDAS_TSB thr5_z_ctx_tsb_0 THR5_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 398 | MIDAS_TSB thr5_z_ctx_tsb_1 THR5_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 399 | MIDAS_TSB thr5_z_ctx_tsb_2 THR5_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 400 | MIDAS_TSB thr5_z_ctx_tsb_3 THR5_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 401 | MIDAS_TSB thr5_nz_ctx_tsb_0 THR5_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 402 | MIDAS_TSB thr5_nz_ctx_tsb_1 THR5_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 403 | MIDAS_TSB thr5_nz_ctx_tsb_2 THR5_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 404 | MIDAS_TSB thr5_nz_ctx_tsb_3 THR5_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 405 | ||
| 406 | MIDAS_TSB thr6_z_ctx_tsb_0 THR6_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 407 | MIDAS_TSB thr6_z_ctx_tsb_1 THR6_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 408 | MIDAS_TSB thr6_z_ctx_tsb_2 THR6_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 409 | MIDAS_TSB thr6_z_ctx_tsb_3 THR6_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 410 | MIDAS_TSB thr6_nz_ctx_tsb_0 THR6_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 411 | MIDAS_TSB thr6_nz_ctx_tsb_1 THR6_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 412 | MIDAS_TSB thr6_nz_ctx_tsb_2 THR6_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 413 | MIDAS_TSB thr6_nz_ctx_tsb_3 THR6_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 414 | ||
| 415 | MIDAS_TSB thr7_z_ctx_tsb_0 THR7_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 416 | MIDAS_TSB thr7_z_ctx_tsb_1 THR7_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 417 | MIDAS_TSB thr7_z_ctx_tsb_2 THR7_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 418 | MIDAS_TSB thr7_z_ctx_tsb_3 THR7_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 419 | MIDAS_TSB thr7_nz_ctx_tsb_0 THR7_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v | |
| 420 | MIDAS_TSB thr7_nz_ctx_tsb_1 THR7_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v | |
| 421 | MIDAS_TSB thr7_nz_ctx_tsb_2 THR7_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v | |
| 422 | MIDAS_TSB thr7_nz_ctx_tsb_3 THR7_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v | |
| 423 | ||
| 424 | /*****************************************************************************************/ | |
| 425 | SECTION .RED_SEC TEXT_VA = 0xfffffffff0000000 | |
| 426 | ||
| 427 | attr_text { | |
| 428 | Name=.RED_SEC, | |
| 429 | hypervisor | |
| 430 | } | |
| 431 | ||
| 432 | .text | |
| 433 | nop | |
| 434 | nop | |
| 435 | nop | |
| 436 | nop | |
| 437 | nop | |
| 438 | nop | |
| 439 | nop | |
| 440 | nop | |
| 441 | ||
| 442 | rdhpr %hpstate, %l1 | |
| 443 | wrhpr %l1, 0x820, %hpstate | |
| 444 | ||
| 445 | wrpr 0, %tl | |
| 446 | wrpr 0, %g0, %gl | |
| 447 | ||
| 448 | #ifdef ENABLE_ITTM_DTTM | |
| 449 | thr0_enable_ittm_dttm: | |
| 450 | or %g0, 0x10, %g2 | |
| 451 | ldxa [%g2] 0x4c, %g5 | |
| 452 | or %g0, 1, %g4 | |
| 453 | sllx %g4, 61, %g3 | |
| 454 | or %g5, %g3, %g5 ! enable ITTM | |
| 455 | sllx %g4, 47, %g3 | |
| 456 | or %g5, %g3, %g5 ! enable DTTM | |
| 457 | stxa %g5, [%g2] 0x4c | |
| 458 | #endif | |
| 459 | ||
| 460 | ! load partition id to %l7 | |
| 461 | wr %g0, ASI_CORE_ID, %asi | |
| 462 | ldxa [ASI_CORE_ID_VA] %asi, %l7 | |
| 463 | set 0x7, %g1 | |
| 464 | and %l7, %g1, %l7 ! %l7 has TID | |
| 465 | xor %l0, %l0, %l0 | |
| 466 | sub %l7, %l0, %l1 | |
| 467 | brnz %l1, test_thr1 | |
| 468 | nop | |
| 469 | setx thr0_red_handler, %l0, %l2 | |
| 470 | jmp %l2 | |
| 471 | nop | |
| 472 | test_thr1: | |
| 473 | add %l0, 1, %l0 | |
| 474 | sub %l7, %l0, %l1 | |
| 475 | brnz %l1, test_thr2 | |
| 476 | nop | |
| 477 | setx thr1_red_handler, %l0, %l2 | |
| 478 | jmp %l2 | |
| 479 | nop | |
| 480 | test_thr2: | |
| 481 | add %l0, 1, %l0 | |
| 482 | sub %l7, %l0, %l1 | |
| 483 | brnz %l1, test_thr3 | |
| 484 | nop | |
| 485 | setx thr2_red_handler, %l0, %l2 | |
| 486 | jmp %l2 | |
| 487 | nop | |
| 488 | test_thr3: | |
| 489 | add %l0, 1, %l0 | |
| 490 | sub %l7, %l0, %l1 | |
| 491 | brnz %l1, test_thr4 | |
| 492 | nop | |
| 493 | setx thr3_red_handler, %l0, %l2 | |
| 494 | jmp %l2 | |
| 495 | nop | |
| 496 | test_thr4: | |
| 497 | add %l0, 1, %l0 | |
| 498 | sub %l7, %l0, %l1 | |
| 499 | brnz %l1, test_thr5 | |
| 500 | nop | |
| 501 | setx thr4_red_handler, %l0, %l2 | |
| 502 | jmp %l2 | |
| 503 | nop | |
| 504 | test_thr5: | |
| 505 | add %l0, 1, %l0 | |
| 506 | sub %l7, %l0, %l1 | |
| 507 | brnz %l1, test_thr6 | |
| 508 | nop | |
| 509 | setx thr5_red_handler, %l0, %l2 | |
| 510 | jmp %l2 | |
| 511 | nop | |
| 512 | test_thr6: | |
| 513 | add %l0, 1, %l0 | |
| 514 | sub %l7, %l0, %l1 | |
| 515 | brnz %l1, test_thr7 | |
| 516 | nop | |
| 517 | setx thr6_red_handler, %l0, %l2 | |
| 518 | jmp %l2 | |
| 519 | nop | |
| 520 | test_thr7: | |
| 521 | setx thr7_red_handler, %l0, %l2 | |
| 522 | jmp %l2 | |
| 523 | nop | |
| 524 | ||
| 525 | EXIT_BAD | |
| 526 | ||
| 527 | /*****************************************************************************************/ | |
| 528 | SECTION .RED_EXT_SEC TEXT_VA = HV_RED_TEXT_PA, DATA_VA = HV_RED_DATA_PA | |
| 529 | ||
| 530 | attr_text { | |
| 531 | Name=.RED_EXT_SEC, | |
| 532 | hypervisor | |
| 533 | } | |
| 534 | ||
| 535 | .text | |
| 536 | .global thr0_red_handler | |
| 537 | thr0_red_handler: | |
| 538 | ! set partition id | |
| 539 | set THR_0_PARTID, %g2 | |
| 540 | mov ASI_PARTITION_ID_VAL, %g1 | |
| 541 | stxa %g2, [%g1] ASI_PARTITION_ID | |
| 542 | ||
| 543 | ! set hyper trap base addr | |
| 544 | setx HPTRAP_TEXT_PA, %l0, %l7 | |
| 545 | wrhpr %l7, %g0, %htba | |
| 546 | ||
| 547 | thr0_hred_context_config: | |
| 548 | setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1 | |
| 549 | wr %g1, 0x0, %asi | |
| 550 | setx THR0_PCONTEXT_0, %l0, %g1 | |
| 551 | stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi | |
| 552 | setx THR0_PCONTEXT_1, %l0, %g1 | |
| 553 | stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi | |
| 554 | setx THR0_SCONTEXT_0, %l0, %g1 | |
| 555 | stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi | |
| 556 | setx THR0_SCONTEXT_1, %l0, %g1 | |
| 557 | stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi | |
| 558 | ||
| 559 | #ifdef TSB_SEARCH_BURST | |
| 560 | thr0_tsb_burst_mode: | |
| 561 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 562 | or TSB_SEARCH_BURST, %g0, %g2 | |
| 563 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 564 | #endif | |
| 565 | #ifdef TSB_SEARCH_PREDICTION | |
| 566 | thr0_tsb_prediction_mode: | |
| 567 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 568 | or TSB_SEARCH_PREDICTION, %g0, %g2 | |
| 569 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 570 | #endif | |
| 571 | ||
| 572 | thr0_hred_physical_offset: | |
| 573 | setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1 | |
| 574 | wr %g1, 0x0, %asi | |
| 575 | ||
| 576 | setx THR0_PHY_OFF_0, %l0, %l1 | |
| 577 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi | |
| 578 | setx THR0_PHY_OFF_1, %l0, %l1 | |
| 579 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi | |
| 580 | setx THR0_PHY_OFF_2, %l0, %l1 | |
| 581 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi | |
| 582 | setx THR0_PHY_OFF_3, %l0, %l1 | |
| 583 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi | |
| 584 | ||
| 585 | thr0_hred_real_range: | |
| 586 | setx ASI_MMU_REAL_RANGE, %l1, %g1 | |
| 587 | wr %g1, 0x0, %asi | |
| 588 | ||
| 589 | setx THR0_REAL_RANGE_0, %l0, %l1 | |
| 590 | stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi | |
| 591 | setx THR0_REAL_RANGE_1, %l0, %l1 | |
| 592 | stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi | |
| 593 | setx THR0_REAL_RANGE_2, %l0, %l1 | |
| 594 | stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi | |
| 595 | setx THR0_REAL_RANGE_3, %l0, %l1 | |
| 596 | stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi | |
| 597 | ||
| 598 | thr0_hred_tsb_config: | |
| 599 | mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 | |
| 600 | wr %g3, 0x0, %asi | |
| 601 | ||
| 602 | thr0_hred_tsb_z_config_0: | |
| 603 | setx THR0_Z_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 604 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 605 | setx THR0_Z_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 606 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 607 | setx THR0_Z_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 608 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 609 | setx THR0_Z_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 610 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 611 | setx THR0_NZ_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 612 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 613 | setx THR0_NZ_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 614 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 615 | setx THR0_NZ_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 616 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 617 | setx THR0_NZ_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 618 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 619 | ||
| 620 | thr0_lsu_ctl_reg: | |
| 621 | setx 0x1f, %l0, %l7 | |
| 622 | stxa %l7, [%g0] ASI_LSU_CONTROL | |
| 623 | ||
| 624 | thr0_transfer_to_priv_code: | |
| 625 | setx Thr0_Priv_Sect_text_begin, %g1, %g2 | |
| 626 | jmp %g2 | |
| 627 | wrhpr %g0, 0x000, %hpstate | |
| 628 | nop | |
| 629 | ||
| 630 | EXIT_BAD | |
| 631 | ||
| 632 | .global thr1_red_handler | |
| 633 | thr1_red_handler: | |
| 634 | ! set partition id | |
| 635 | set THR_1_PARTID, %g2 | |
| 636 | mov ASI_PARTITION_ID_VAL, %g1 | |
| 637 | stxa %g2, [%g1] ASI_PARTITION_ID | |
| 638 | ||
| 639 | ! set hyper trap base addr | |
| 640 | setx HPTRAP_TEXT_PA, %l0, %l7 | |
| 641 | wrhpr %l7, %g0, %htba | |
| 642 | ||
| 643 | thr1_hred_context_config: | |
| 644 | setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1 | |
| 645 | wr %g1, 0x0, %asi | |
| 646 | setx THR1_PCONTEXT_0, %l0, %g1 | |
| 647 | stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi | |
| 648 | setx THR1_PCONTEXT_1, %l0, %g1 | |
| 649 | stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi | |
| 650 | setx THR1_SCONTEXT_0, %l0, %g1 | |
| 651 | stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi | |
| 652 | setx THR1_SCONTEXT_1, %l0, %g1 | |
| 653 | stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi | |
| 654 | ||
| 655 | #ifdef TSB_SEARCH_BURST | |
| 656 | thr1_tsb_burst_mode: | |
| 657 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 658 | or TSB_SEARCH_BURST, %g0, %g2 | |
| 659 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 660 | #endif | |
| 661 | #ifdef TSB_SEARCH_PREDICTION | |
| 662 | thr1_tsb_prediction_mode: | |
| 663 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 664 | or TSB_SEARCH_PREDICTION, %g0, %g2 | |
| 665 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 666 | #endif | |
| 667 | ||
| 668 | thr1_hred_physical_offset: | |
| 669 | setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1 | |
| 670 | wr %g1, 0x0, %asi | |
| 671 | ||
| 672 | setx THR1_PHY_OFF_0, %l0, %l1 | |
| 673 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi | |
| 674 | setx THR1_PHY_OFF_1, %l0, %l1 | |
| 675 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi | |
| 676 | setx THR1_PHY_OFF_2, %l0, %l1 | |
| 677 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi | |
| 678 | setx THR1_PHY_OFF_3, %l0, %l1 | |
| 679 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi | |
| 680 | ||
| 681 | thr1_hred_real_range: | |
| 682 | setx ASI_MMU_REAL_RANGE, %l1, %g1 | |
| 683 | wr %g1, 0x0, %asi | |
| 684 | ||
| 685 | setx THR1_REAL_RANGE_0, %l0, %l1 | |
| 686 | stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi | |
| 687 | setx THR1_REAL_RANGE_1, %l0, %l1 | |
| 688 | stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi | |
| 689 | setx THR1_REAL_RANGE_2, %l0, %l1 | |
| 690 | stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi | |
| 691 | setx THR1_REAL_RANGE_3, %l0, %l1 | |
| 692 | stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi | |
| 693 | ||
| 694 | thr1_hred_tsb_config: | |
| 695 | mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 | |
| 696 | wr %g3, 0x0, %asi | |
| 697 | ||
| 698 | thr1_hred_tsb_z_config_0: | |
| 699 | setx THR1_Z_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 700 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 701 | setx THR1_Z_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 702 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 703 | setx THR1_Z_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 704 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 705 | setx THR1_Z_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 706 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 707 | setx THR1_NZ_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 708 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 709 | setx THR1_NZ_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 710 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 711 | setx THR1_NZ_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 712 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 713 | setx THR1_NZ_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 714 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 715 | ||
| 716 | thr1_lsu_ctl_reg: | |
| 717 | setx 0x1f, %l0, %l7 | |
| 718 | stxa %l7, [%g0] ASI_LSU_CONTROL | |
| 719 | ||
| 720 | thr1_transfer_to_priv_code: | |
| 721 | setx Thr1_Priv_Sect_text_begin, %g1, %g2 | |
| 722 | jmp %g2 | |
| 723 | wrhpr %g0, 0x000, %hpstate | |
| 724 | nop | |
| 725 | ||
| 726 | EXIT_BAD | |
| 727 | ||
| 728 | .global thr2_red_handler | |
| 729 | thr2_red_handler: | |
| 730 | ! set partition id | |
| 731 | set THR_2_PARTID, %g2 | |
| 732 | mov ASI_PARTITION_ID_VAL, %g1 | |
| 733 | stxa %g2, [%g1] ASI_PARTITION_ID | |
| 734 | ||
| 735 | ! set hyper trap base addr | |
| 736 | setx HPTRAP_TEXT_PA, %l0, %l7 | |
| 737 | wrhpr %l7, %g0, %htba | |
| 738 | ||
| 739 | thr2_hred_context_config: | |
| 740 | setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1 | |
| 741 | wr %g1, 0x0, %asi | |
| 742 | setx THR2_PCONTEXT_0, %l0, %g1 | |
| 743 | stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi | |
| 744 | setx THR2_PCONTEXT_1, %l0, %g1 | |
| 745 | stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi | |
| 746 | setx THR2_SCONTEXT_0, %l0, %g1 | |
| 747 | stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi | |
| 748 | setx THR2_SCONTEXT_1, %l0, %g1 | |
| 749 | stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi | |
| 750 | ||
| 751 | #ifdef TSB_SEARCH_BURST | |
| 752 | thr2_tsb_burst_mode: | |
| 753 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 754 | or TSB_SEARCH_BURST, %g0, %g2 | |
| 755 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 756 | #endif | |
| 757 | #ifdef TSB_SEARCH_PREDICTION | |
| 758 | thr2_tsb_prediction_mode: | |
| 759 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 760 | or TSB_SEARCH_PREDICTION, %g0, %g2 | |
| 761 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 762 | #endif | |
| 763 | ||
| 764 | thr2_hred_physical_offset: | |
| 765 | setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1 | |
| 766 | wr %g1, 0x0, %asi | |
| 767 | ||
| 768 | setx THR2_PHY_OFF_0, %l0, %l1 | |
| 769 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi | |
| 770 | setx THR2_PHY_OFF_1, %l0, %l1 | |
| 771 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi | |
| 772 | setx THR2_PHY_OFF_2, %l0, %l1 | |
| 773 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi | |
| 774 | setx THR2_PHY_OFF_3, %l0, %l1 | |
| 775 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi | |
| 776 | ||
| 777 | thr2_hred_real_range: | |
| 778 | setx ASI_MMU_REAL_RANGE, %l1, %g1 | |
| 779 | wr %g1, 0x0, %asi | |
| 780 | ||
| 781 | setx THR2_REAL_RANGE_0, %l0, %l1 | |
| 782 | stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi | |
| 783 | setx THR2_REAL_RANGE_1, %l0, %l1 | |
| 784 | stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi | |
| 785 | setx THR2_REAL_RANGE_2, %l0, %l1 | |
| 786 | stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi | |
| 787 | setx THR2_REAL_RANGE_3, %l0, %l1 | |
| 788 | stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi | |
| 789 | ||
| 790 | thr2_hred_tsb_config: | |
| 791 | mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 | |
| 792 | wr %g3, 0x0, %asi | |
| 793 | ||
| 794 | thr2_hred_tsb_z_config_0: | |
| 795 | setx THR2_Z_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 796 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 797 | setx THR2_Z_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 798 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 799 | setx THR2_Z_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 800 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 801 | setx THR2_Z_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 802 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 803 | setx THR2_NZ_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 804 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 805 | setx THR2_NZ_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 806 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 807 | setx THR2_NZ_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 808 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 809 | setx THR2_NZ_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 810 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 811 | ||
| 812 | thr2_lsu_ctl_reg: | |
| 813 | setx 0x1f, %l0, %l7 | |
| 814 | stxa %l7, [%g0] ASI_LSU_CONTROL | |
| 815 | ||
| 816 | thr2_transfer_to_priv_code: | |
| 817 | setx Thr2_Priv_Sect_text_begin, %g1, %g2 | |
| 818 | jmp %g2 | |
| 819 | wrhpr %g0, 0x000, %hpstate | |
| 820 | nop | |
| 821 | ||
| 822 | EXIT_BAD | |
| 823 | ||
| 824 | .global thr3_red_handler | |
| 825 | thr3_red_handler: | |
| 826 | ! set partition id | |
| 827 | set THR_3_PARTID, %g2 | |
| 828 | mov ASI_PARTITION_ID_VAL, %g1 | |
| 829 | stxa %g2, [%g1] ASI_PARTITION_ID | |
| 830 | ||
| 831 | ! set hyper trap base addr | |
| 832 | setx HPTRAP_TEXT_PA, %l0, %l7 | |
| 833 | wrhpr %l7, %g0, %htba | |
| 834 | ||
| 835 | thr3_hred_context_config: | |
| 836 | setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1 | |
| 837 | wr %g1, 0x0, %asi | |
| 838 | setx THR3_PCONTEXT_0, %l0, %g1 | |
| 839 | stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi | |
| 840 | setx THR3_PCONTEXT_1, %l0, %g1 | |
| 841 | stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi | |
| 842 | setx THR3_SCONTEXT_0, %l0, %g1 | |
| 843 | stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi | |
| 844 | setx THR3_SCONTEXT_1, %l0, %g1 | |
| 845 | stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi | |
| 846 | ||
| 847 | #ifdef TSB_SEARCH_BURST | |
| 848 | thr3_tsb_burst_mode: | |
| 849 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 850 | or TSB_SEARCH_BURST, %g0, %g2 | |
| 851 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 852 | #endif | |
| 853 | #ifdef TSB_SEARCH_PREDICTION | |
| 854 | thr3_tsb_prediction_mode: | |
| 855 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 856 | or TSB_SEARCH_PREDICTION, %g0, %g2 | |
| 857 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 858 | #endif | |
| 859 | ||
| 860 | thr3_hred_physical_offset: | |
| 861 | setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1 | |
| 862 | wr %g1, 0x0, %asi | |
| 863 | ||
| 864 | setx THR3_PHY_OFF_0, %l0, %l1 | |
| 865 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi | |
| 866 | setx THR3_PHY_OFF_1, %l0, %l1 | |
| 867 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi | |
| 868 | setx THR3_PHY_OFF_2, %l0, %l1 | |
| 869 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi | |
| 870 | setx THR3_PHY_OFF_3, %l0, %l1 | |
| 871 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi | |
| 872 | ||
| 873 | thr3_hred_real_range: | |
| 874 | setx ASI_MMU_REAL_RANGE, %l1, %g1 | |
| 875 | wr %g1, 0x0, %asi | |
| 876 | ||
| 877 | setx THR3_REAL_RANGE_0, %l0, %l1 | |
| 878 | stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi | |
| 879 | setx THR3_REAL_RANGE_1, %l0, %l1 | |
| 880 | stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi | |
| 881 | setx THR3_REAL_RANGE_2, %l0, %l1 | |
| 882 | stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi | |
| 883 | setx THR3_REAL_RANGE_3, %l0, %l1 | |
| 884 | stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi | |
| 885 | ||
| 886 | thr3_hred_tsb_config: | |
| 887 | mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 | |
| 888 | wr %g3, 0x0, %asi | |
| 889 | ||
| 890 | thr3_hred_tsb_z_config_0: | |
| 891 | setx THR3_Z_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 892 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 893 | setx THR3_Z_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 894 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 895 | setx THR3_Z_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 896 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 897 | setx THR3_Z_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 898 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 899 | setx THR3_NZ_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 900 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 901 | setx THR3_NZ_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 902 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 903 | setx THR3_NZ_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 904 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 905 | setx THR3_NZ_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 906 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 907 | ||
| 908 | thr3_lsu_ctl_reg: | |
| 909 | setx 0x1f, %l0, %l7 | |
| 910 | stxa %l7, [%g0] ASI_LSU_CONTROL | |
| 911 | ||
| 912 | thr3_transfer_to_priv_code: | |
| 913 | setx Thr3_Priv_Sect_text_begin, %g1, %g2 | |
| 914 | jmp %g2 | |
| 915 | wrhpr %g0, 0x000, %hpstate | |
| 916 | nop | |
| 917 | ||
| 918 | EXIT_BAD | |
| 919 | ||
| 920 | .global thr4_red_handler | |
| 921 | thr4_red_handler: | |
| 922 | ! set partition id | |
| 923 | set THR_4_PARTID, %g2 | |
| 924 | mov ASI_PARTITION_ID_VAL, %g1 | |
| 925 | stxa %g2, [%g1] ASI_PARTITION_ID | |
| 926 | ||
| 927 | ! set hyper trap base addr | |
| 928 | setx HPTRAP_TEXT_PA, %l0, %l7 | |
| 929 | wrhpr %l7, %g0, %htba | |
| 930 | ||
| 931 | thr4_hred_context_config: | |
| 932 | setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1 | |
| 933 | wr %g1, 0x0, %asi | |
| 934 | setx THR4_PCONTEXT_0, %l0, %g1 | |
| 935 | stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi | |
| 936 | setx THR4_PCONTEXT_1, %l0, %g1 | |
| 937 | stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi | |
| 938 | setx THR4_SCONTEXT_0, %l0, %g1 | |
| 939 | stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi | |
| 940 | setx THR4_SCONTEXT_1, %l0, %g1 | |
| 941 | stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi | |
| 942 | ||
| 943 | #ifdef TSB_SEARCH_BURST | |
| 944 | thr4_tsb_burst_mode: | |
| 945 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 946 | or TSB_SEARCH_BURST, %g0, %g2 | |
| 947 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 948 | #endif | |
| 949 | #ifdef TSB_SEARCH_PREDICTION | |
| 950 | thr4_tsb_prediction_mode: | |
| 951 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 952 | or TSB_SEARCH_PREDICTION, %g0, %g2 | |
| 953 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 954 | #endif | |
| 955 | ||
| 956 | thr4_hred_physical_offset: | |
| 957 | setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1 | |
| 958 | wr %g1, 0x0, %asi | |
| 959 | ||
| 960 | setx THR4_PHY_OFF_0, %l0, %l1 | |
| 961 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi | |
| 962 | setx THR4_PHY_OFF_1, %l0, %l1 | |
| 963 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi | |
| 964 | setx THR4_PHY_OFF_2, %l0, %l1 | |
| 965 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi | |
| 966 | setx THR4_PHY_OFF_3, %l0, %l1 | |
| 967 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi | |
| 968 | ||
| 969 | thr4_hred_real_range: | |
| 970 | setx ASI_MMU_REAL_RANGE, %l1, %g1 | |
| 971 | wr %g1, 0x0, %asi | |
| 972 | ||
| 973 | setx THR4_REAL_RANGE_0, %l0, %l1 | |
| 974 | stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi | |
| 975 | setx THR4_REAL_RANGE_1, %l0, %l1 | |
| 976 | stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi | |
| 977 | setx THR4_REAL_RANGE_2, %l0, %l1 | |
| 978 | stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi | |
| 979 | setx THR4_REAL_RANGE_3, %l0, %l1 | |
| 980 | stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi | |
| 981 | ||
| 982 | thr4_hred_tsb_config: | |
| 983 | mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 | |
| 984 | wr %g3, 0x0, %asi | |
| 985 | ||
| 986 | thr4_hred_tsb_z_config_0: | |
| 987 | setx THR4_Z_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 988 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 989 | setx THR4_Z_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 990 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 991 | setx THR4_Z_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 992 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 993 | setx THR4_Z_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 994 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 995 | setx THR4_NZ_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 996 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 997 | setx THR4_NZ_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 998 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 999 | setx THR4_NZ_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 1000 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 1001 | setx THR4_NZ_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 1002 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 1003 | ||
| 1004 | thr4_lsu_ctl_reg: | |
| 1005 | setx 0x1f, %l0, %l7 | |
| 1006 | stxa %l7, [%g0] ASI_LSU_CONTROL | |
| 1007 | ||
| 1008 | thr4_transfer_to_priv_code: | |
| 1009 | setx Thr4_Priv_Sect_text_begin, %g1, %g2 | |
| 1010 | jmp %g2 | |
| 1011 | wrhpr %g0, 0x000, %hpstate | |
| 1012 | nop | |
| 1013 | ||
| 1014 | EXIT_BAD | |
| 1015 | ||
| 1016 | .global thr5_red_handler | |
| 1017 | thr5_red_handler: | |
| 1018 | ! set partition id | |
| 1019 | set THR_5_PARTID, %g2 | |
| 1020 | mov ASI_PARTITION_ID_VAL, %g1 | |
| 1021 | stxa %g2, [%g1] ASI_PARTITION_ID | |
| 1022 | ||
| 1023 | ! set hyper trap base addr | |
| 1024 | setx HPTRAP_TEXT_PA, %l0, %l7 | |
| 1025 | wrhpr %l7, %g0, %htba | |
| 1026 | ||
| 1027 | thr5_hred_context_config: | |
| 1028 | setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1 | |
| 1029 | wr %g1, 0x0, %asi | |
| 1030 | setx THR5_PCONTEXT_0, %l0, %g1 | |
| 1031 | stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi | |
| 1032 | setx THR5_PCONTEXT_1, %l0, %g1 | |
| 1033 | stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi | |
| 1034 | setx THR5_SCONTEXT_0, %l0, %g1 | |
| 1035 | stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi | |
| 1036 | setx THR5_SCONTEXT_1, %l0, %g1 | |
| 1037 | stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi | |
| 1038 | ||
| 1039 | #ifdef TSB_SEARCH_BURST | |
| 1040 | thr5_tsb_burst_mode: | |
| 1041 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 1042 | or TSB_SEARCH_BURST, %g0, %g2 | |
| 1043 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 1044 | #endif | |
| 1045 | #ifdef TSB_SEARCH_PREDICTION | |
| 1046 | thr5_tsb_prediction_mode: | |
| 1047 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 1048 | or TSB_SEARCH_PREDICTION, %g0, %g2 | |
| 1049 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 1050 | #endif | |
| 1051 | ||
| 1052 | thr5_hred_physical_offset: | |
| 1053 | setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1 | |
| 1054 | wr %g1, 0x0, %asi | |
| 1055 | ||
| 1056 | setx THR5_PHY_OFF_0, %l0, %l1 | |
| 1057 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi | |
| 1058 | setx THR5_PHY_OFF_1, %l0, %l1 | |
| 1059 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi | |
| 1060 | setx THR5_PHY_OFF_2, %l0, %l1 | |
| 1061 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi | |
| 1062 | setx THR5_PHY_OFF_3, %l0, %l1 | |
| 1063 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi | |
| 1064 | ||
| 1065 | thr5_hred_real_range: | |
| 1066 | setx ASI_MMU_REAL_RANGE, %l1, %g1 | |
| 1067 | wr %g1, 0x0, %asi | |
| 1068 | ||
| 1069 | setx THR5_REAL_RANGE_0, %l0, %l1 | |
| 1070 | stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi | |
| 1071 | setx THR5_REAL_RANGE_1, %l0, %l1 | |
| 1072 | stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi | |
| 1073 | setx THR5_REAL_RANGE_2, %l0, %l1 | |
| 1074 | stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi | |
| 1075 | setx THR5_REAL_RANGE_3, %l0, %l1 | |
| 1076 | stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi | |
| 1077 | ||
| 1078 | thr5_hred_tsb_config: | |
| 1079 | mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 | |
| 1080 | wr %g3, 0x0, %asi | |
| 1081 | ||
| 1082 | thr5_hred_tsb_z_config_0: | |
| 1083 | setx THR5_Z_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 1084 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 1085 | setx THR5_Z_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 1086 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 1087 | setx THR5_Z_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 1088 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 1089 | setx THR5_Z_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 1090 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 1091 | setx THR5_NZ_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 1092 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 1093 | setx THR5_NZ_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 1094 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 1095 | setx THR5_NZ_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 1096 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 1097 | setx THR5_NZ_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 1098 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 1099 | ||
| 1100 | thr5_lsu_ctl_reg: | |
| 1101 | setx 0x1f, %l0, %l7 | |
| 1102 | stxa %l7, [%g0] ASI_LSU_CONTROL | |
| 1103 | ||
| 1104 | thr5_transfer_to_priv_code: | |
| 1105 | setx Thr5_Priv_Sect_text_begin, %g1, %g2 | |
| 1106 | jmp %g2 | |
| 1107 | wrhpr %g0, 0x000, %hpstate | |
| 1108 | nop | |
| 1109 | ||
| 1110 | EXIT_BAD | |
| 1111 | ||
| 1112 | .global thr6_red_handler | |
| 1113 | thr6_red_handler: | |
| 1114 | ! set partition id | |
| 1115 | set THR_6_PARTID, %g2 | |
| 1116 | mov ASI_PARTITION_ID_VAL, %g1 | |
| 1117 | stxa %g2, [%g1] ASI_PARTITION_ID | |
| 1118 | ||
| 1119 | ! set hyper trap base addr | |
| 1120 | setx HPTRAP_TEXT_PA, %l0, %l7 | |
| 1121 | wrhpr %l7, %g0, %htba | |
| 1122 | ||
| 1123 | thr6_hred_context_config: | |
| 1124 | setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1 | |
| 1125 | wr %g1, 0x0, %asi | |
| 1126 | setx THR6_PCONTEXT_0, %l0, %g1 | |
| 1127 | stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi | |
| 1128 | setx THR6_PCONTEXT_1, %l0, %g1 | |
| 1129 | stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi | |
| 1130 | setx THR6_SCONTEXT_0, %l0, %g1 | |
| 1131 | stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi | |
| 1132 | setx THR6_SCONTEXT_1, %l0, %g1 | |
| 1133 | stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi | |
| 1134 | ||
| 1135 | #ifdef TSB_SEARCH_BURST | |
| 1136 | thr6_tsb_burst_mode: | |
| 1137 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 1138 | or TSB_SEARCH_BURST, %g0, %g2 | |
| 1139 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 1140 | #endif | |
| 1141 | #ifdef TSB_SEARCH_PREDICTION | |
| 1142 | thr6_tsb_prediction_mode: | |
| 1143 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 1144 | or TSB_SEARCH_PREDICTION, %g0, %g2 | |
| 1145 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 1146 | #endif | |
| 1147 | ||
| 1148 | thr6_hred_physical_offset: | |
| 1149 | setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1 | |
| 1150 | wr %g1, 0x0, %asi | |
| 1151 | ||
| 1152 | setx THR6_PHY_OFF_0, %l0, %l1 | |
| 1153 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi | |
| 1154 | setx THR6_PHY_OFF_1, %l0, %l1 | |
| 1155 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi | |
| 1156 | setx THR6_PHY_OFF_2, %l0, %l1 | |
| 1157 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi | |
| 1158 | setx THR6_PHY_OFF_3, %l0, %l1 | |
| 1159 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi | |
| 1160 | ||
| 1161 | thr6_hred_real_range: | |
| 1162 | setx ASI_MMU_REAL_RANGE, %l1, %g1 | |
| 1163 | wr %g1, 0x0, %asi | |
| 1164 | ||
| 1165 | setx THR6_REAL_RANGE_0, %l0, %l1 | |
| 1166 | stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi | |
| 1167 | setx THR6_REAL_RANGE_1, %l0, %l1 | |
| 1168 | stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi | |
| 1169 | setx THR6_REAL_RANGE_2, %l0, %l1 | |
| 1170 | stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi | |
| 1171 | setx THR6_REAL_RANGE_3, %l0, %l1 | |
| 1172 | stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi | |
| 1173 | ||
| 1174 | thr6_hred_tsb_config: | |
| 1175 | mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 | |
| 1176 | wr %g3, 0x0, %asi | |
| 1177 | ||
| 1178 | thr6_hred_tsb_z_config_0: | |
| 1179 | setx THR6_Z_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 1180 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 1181 | setx THR6_Z_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 1182 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 1183 | setx THR6_Z_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 1184 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 1185 | setx THR6_Z_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 1186 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 1187 | setx THR6_NZ_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 1188 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 1189 | setx THR6_NZ_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 1190 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 1191 | setx THR6_NZ_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 1192 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 1193 | setx THR6_NZ_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 1194 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 1195 | ||
| 1196 | thr6_lsu_ctl_reg: | |
| 1197 | setx 0x1f, %l0, %l7 | |
| 1198 | stxa %l7, [%g0] ASI_LSU_CONTROL | |
| 1199 | ||
| 1200 | thr6_transfer_to_priv_code: | |
| 1201 | setx Thr6_Priv_Sect_text_begin, %g1, %g2 | |
| 1202 | jmp %g2 | |
| 1203 | wrhpr %g0, 0x000, %hpstate | |
| 1204 | nop | |
| 1205 | ||
| 1206 | EXIT_BAD | |
| 1207 | ||
| 1208 | .global thr7_red_handler | |
| 1209 | thr7_red_handler: | |
| 1210 | ! set partition id | |
| 1211 | set THR_7_PARTID, %g2 | |
| 1212 | mov ASI_PARTITION_ID_VAL, %g1 | |
| 1213 | stxa %g2, [%g1] ASI_PARTITION_ID | |
| 1214 | ||
| 1215 | ! set hyper trap base addr | |
| 1216 | setx HPTRAP_TEXT_PA, %l0, %l7 | |
| 1217 | wrhpr %l7, %g0, %htba | |
| 1218 | ||
| 1219 | thr7_hred_context_config: | |
| 1220 | setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1 | |
| 1221 | wr %g1, 0x0, %asi | |
| 1222 | setx THR7_PCONTEXT_0, %l0, %g1 | |
| 1223 | stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi | |
| 1224 | setx THR7_PCONTEXT_1, %l0, %g1 | |
| 1225 | stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi | |
| 1226 | setx THR7_SCONTEXT_0, %l0, %g1 | |
| 1227 | stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi | |
| 1228 | setx THR7_SCONTEXT_1, %l0, %g1 | |
| 1229 | stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi | |
| 1230 | ||
| 1231 | #ifdef TSB_SEARCH_BURST | |
| 1232 | thr7_tsb_burst_mode: | |
| 1233 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 1234 | or TSB_SEARCH_BURST, %g0, %g2 | |
| 1235 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 1236 | #endif | |
| 1237 | #ifdef TSB_SEARCH_PREDICTION | |
| 1238 | thr7_tsb_prediction_mode: | |
| 1239 | setx ASI_TSB_SEARCH_MODE_ADDR, %l1, %g1 | |
| 1240 | or TSB_SEARCH_PREDICTION, %g0, %g2 | |
| 1241 | stxa %g2, [%g1] ASI_TSB_SEARCH_MODE_REG | |
| 1242 | #endif | |
| 1243 | ||
| 1244 | thr7_hred_physical_offset: | |
| 1245 | setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1 | |
| 1246 | wr %g1, 0x0, %asi | |
| 1247 | ||
| 1248 | setx THR7_PHY_OFF_0, %l0, %l1 | |
| 1249 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi | |
| 1250 | setx THR7_PHY_OFF_1, %l0, %l1 | |
| 1251 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi | |
| 1252 | setx THR7_PHY_OFF_2, %l0, %l1 | |
| 1253 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi | |
| 1254 | setx THR7_PHY_OFF_3, %l0, %l1 | |
| 1255 | stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi | |
| 1256 | ||
| 1257 | thr7_hred_real_range: | |
| 1258 | setx ASI_MMU_REAL_RANGE, %l1, %g1 | |
| 1259 | wr %g1, 0x0, %asi | |
| 1260 | ||
| 1261 | setx THR7_REAL_RANGE_0, %l0, %l1 | |
| 1262 | stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi | |
| 1263 | setx THR7_REAL_RANGE_1, %l0, %l1 | |
| 1264 | stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi | |
| 1265 | setx THR7_REAL_RANGE_2, %l0, %l1 | |
| 1266 | stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi | |
| 1267 | setx THR7_REAL_RANGE_3, %l0, %l1 | |
| 1268 | stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi | |
| 1269 | ||
| 1270 | thr7_hred_tsb_config: | |
| 1271 | mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 | |
| 1272 | wr %g3, 0x0, %asi | |
| 1273 | ||
| 1274 | thr7_hred_tsb_z_config_0: | |
| 1275 | setx THR7_Z_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 1276 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 1277 | setx THR7_Z_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 1278 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 1279 | setx THR7_Z_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 1280 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 1281 | setx THR7_Z_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 1282 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 1283 | setx THR7_NZ_CTX_TSB_CONFIG_0, %g1, %g4 | |
| 1284 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi | |
| 1285 | setx THR7_NZ_CTX_TSB_CONFIG_1, %g1, %g4 | |
| 1286 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi | |
| 1287 | setx THR7_NZ_CTX_TSB_CONFIG_2, %g1, %g4 | |
| 1288 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi | |
| 1289 | setx THR7_NZ_CTX_TSB_CONFIG_3, %g1, %g4 | |
| 1290 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi | |
| 1291 | ||
| 1292 | thr7_lsu_ctl_reg: | |
| 1293 | setx 0x1f, %l0, %l7 | |
| 1294 | stxa %l7, [%g0] ASI_LSU_CONTROL | |
| 1295 | ||
| 1296 | thr7_transfer_to_priv_code: | |
| 1297 | setx Thr7_Priv_Sect_text_begin, %g1, %g2 | |
| 1298 | jmp %g2 | |
| 1299 | wrhpr %g0, 0x000, %hpstate | |
| 1300 | nop | |
| 1301 | ||
| 1302 | EXIT_BAD | |
| 1303 | ||
| 1304 | attr_data { | |
| 1305 | Name=.RED_EXT_SEC, | |
| 1306 | hypervisor | |
| 1307 | } | |
| 1308 | ||
| 1309 | .data | |
| 1310 | part_id_list: | |
| 1311 | .xword THR_0_PARTID, THR_1_PARTID, THR_2_PARTID, THR_3_PARTID | |
| 1312 | .xword THR_4_PARTID, THR_5_PARTID, THR_6_PARTID, THR_7_PARTID | |
| 1313 |