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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / tlu_custom_intr_handlers.s
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tlu_custom_intr_handlers.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#ifndef INT_HANDLER_RAND4_1
39#define INT_HANDLER_RAND4_1 retry; nop; nop; nop
40#endif
41#ifndef INT_HANDLER_RAND7_1
42#define INT_HANDLER_RAND7_1 retry; nop; nop; nop ; nop; nop; nop
43#endif
44#ifndef INT_HANDLER_RAND4_2
45#define INT_HANDLER_RAND4_2 retry; nop; nop; nop
46#endif
47#ifndef INT_HANDLER_RAND7_2
48#define INT_HANDLER_RAND7_2 retry; nop; nop; nop ; nop; nop; nop
49#endif
50#ifndef INT_HANDLER_RAND4_3
51#define INT_HANDLER_RAND4_3 retry; nop; nop; nop
52#endif
53#ifndef INT_HANDLER_RAND7_3
54#define INT_HANDLER_RAND7_3 retry; nop; nop; nop ; nop; nop; nop
55#endif
56#define H_HT0_Externally_Initiated_Reset_0x03
57#define SUN_H_HT0_Externally_Initiated_Reset_0x03 \
58 ldxa [%g0] ASI_LSU_CTL_REG, %g1; \
59 set cregs_lsu_ctl_reg_r64, %g1; \
60 stxa %g1, [%g0] ASI_LSU_CTL_REG; \
61 retry;nop
62
63#define My_External_Reset \
64 ldxa [%g0] ASI_LSU_CTL_REG, %l5; \
65 set cregs_lsu_ctl_reg_r64, %l5; \
66 stxa %l5, [%g0] ASI_LSU_CTL_REG; \
67 retry;nop
68
69!!!!! SPU Interrupt Handlers
70
71#define H_HT0_Control_Word_Queue_Interrupt_0x3c
72#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
73 INT_HANDLER_RAND7_1 ;\
74 retry ;
75
76#define H_HT0_Modular_Arithmetic_Interrupt_0x3d
77#define My_H_HT0_Modular_Arithmetic_Interrupt_0x3d \
78 INT_HANDLER_RAND7_2 ;\
79 retry ;
80
81
82!!!!! HW interrupt handlers
83
84#define H_HT0_Interrupt_0x60
85#define My_HT0_Interrupt_0x60 \
86 ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g5 ;\
87 ldxa [%g0] ASI_SWVR_INTR_R, %g4 ;\
88 ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g3 ;\
89 INT_HANDLER_RAND4_1 ;\
90 retry;
91
92!!!!! Queue interrupt handler
93
94
95#define H_T0_Cpu_Mondo_Trap_0x7c
96#define My_T0_Cpu_Mondo_Trap_0x7c \
97 mov 0x3c8, %g3; \
98 ldxa [%g3] 0x25, %g5; \
99 mov 0x3c0, %g3; \
100 stxa %g5, [%g3] 0x25; \
101 retry; \
102 nop; \
103 nop; \
104 nop
105
106#define H_T0_Dev_Mondo_Trap_0x7d
107#define My_T0_Dev_Mondo_Trap_0x7d \
108 mov 0x3d8, %g3; \
109 ldxa [%g3] 0x25, %g5; \
110 mov 0x3d0, %g3; \
111 stxa %g5, [%g3] 0x25; \
112 retry; \
113 nop; \
114 nop; \
115 nop
116
117#define H_T0_Resumable_Error_0x7e
118#define My_T0_Resumable_Error_0x7e \
119 mov 0x3e8, %g3; \
120 ldxa [%g3] 0x25, %g5; \
121 mov 0x3e0, %g3; \
122 stxa %g5, [%g3] 0x25; \
123 retry; \
124 nop; \
125 nop; \
126 nop
127
128#define H_T1_Cpu_Mondo_Trap_0x7c
129#define My_T1_Cpu_Mondo_Trap_0x7c \
130 mov 0x3c8, %g3; \
131 ldxa [%g3] 0x25, %g5; \
132 mov 0x3c0, %g3; \
133 stxa %g5, [%g3] 0x25; \
134 retry; \
135 nop; \
136 nop; \
137 nop
138
139#define H_T1_Dev_Mondo_Trap_0x7d
140#define My_T1_Dev_Mondo_Trap_0x7d \
141 mov 0x3d8, %g3; \
142 ldxa [%g3] 0x25, %g5; \
143 mov 0x3d0, %g3; \
144 stxa %g5, [%g3] 0x25; \
145 retry; \
146 nop; \
147 nop; \
148 nop
149
150#define H_T1_Resumable_Error_0x7e
151#define My_T1_Resumable_Error_0x7e \
152 mov 0x3e8, %g3; \
153 ldxa [%g3] 0x25, %g5; \
154 mov 0x3e0, %g3; \
155 stxa %g5, [%g3] 0x25; \
156 retry; \
157 nop; \
158 nop; \
159 nop
160
161#define H_HT0_Reserved_0x7c
162#define SUN_H_HT0_Reserved_0x7c \
163 mov 0x3c8, %g3; \
164 ldxa [%g3] 0x25, %g5; \
165 mov 0x3c0, %g3; \
166 stxa %g5, [%g3] 0x25; \
167 retry; \
168 nop; \
169 nop; \
170 nop
171
172#define H_HT0_Reserved_0x7d
173#define SUN_H_HT0_Reserved_0x7d \
174 mov 0x3d8, %g3; \
175 ldxa [%g3] 0x25, %g5; \
176 mov 0x3d0, %g3; \
177 stxa %g5, [%g3] 0x25; \
178 retry; \
179 nop; \
180 nop; \
181 nop
182
183#define H_HT0_Reserved_0x7e
184#define SUN_H_HT0_Reserved_0x7e \
185 mov 0x3e8, %g3; \
186 ldxa [%g3] 0x25, %g5; \
187 mov 0x3e0, %g3; \
188 stxa %g5, [%g3] 0x25; \
189 retry; \
190 nop; \
191 nop; \
192 nop
193
194
195!!!!! Hstick-match trap handler
196
197
198#define H_T0_Reserved_0x5e
199#define My_T0_Reserved_0x5e \
200 rdhpr %hintp, %g3; \
201 wrhpr %g3, %g3, %hintp; \
202 retry; \
203 nop; \
204 nop; \
205 nop; \
206 nop; \
207 nop
208
209#define H_HT0_Hstick_Match_0x5e
210#define My_HT0_Hstick_Match_0x5e \
211 rdhpr %hintp, %g3; \
212 wrhpr %g3, %g3, %hintp; \
213 retry; \
214 nop; \
215 nop; \
216 nop; \
217 nop; \
218 nop
219
220#define H_T0_Reserved_0x5e
221#define My_T0_Reserved_0x5e \
222 rdhpr %hintp, %g3; \
223 wrhpr %g3, %g3, %hintp; \
224 retry; \
225 nop; \
226 nop; \
227 nop; \
228 nop; \
229 nop
230
231#define H_T1_Reserved_0x5e
232#define My_T1_Reserved_0x5e \
233 rdhpr %hintp, %g3; \
234 wrhpr %g3, %g3, %hintp; \
235 retry; \
236 nop; \
237 nop; \
238 nop; \
239 nop; \
240 nop
241
242
243!!!!! SW interuupt handlers
244
245
246#define H_T0_Interrupt_Level_14_0x4e
247#define My_T0_Interrupt_Level_14_0x4e \
248 rd %softint, %g3; \
249 sethi %hi(0x14000), %g3; \
250 or %g3, 0x1, %g3; \
251 wr %g3, %g0, %clear_softint; \
252 rd %tick, %g3 ;\
253 retry; \
254
255#define H_T0_Interrupt_Level_1_0x41
256#define My_T0_Interrupt_Level_1_0x41 \
257 rd %softint, %g3; \
258 or %g0, 0x2, %g3; \
259 wr %g3, %g0, %clear_softint; \
260 retry; \
261 nop; \
262 nop; \
263 nop; \
264 nop
265
266#define H_T0_Interrupt_Level_2_0x42
267#define My_T0_Interrupt_Level_2_0x42 \
268 rd %softint, %g3; \
269 or %g0, 0x4, %g3; \
270 wr %g3, %g0, %clear_softint; \
271 retry; \
272 nop; \
273 nop; \
274 nop; \
275 nop
276
277#define H_T0_Interrupt_Level_3_0x43
278#define My_T0_Interrupt_Level_3_0x43 \
279 rd %softint, %g3; \
280 or %g0, 0x8, %g3; \
281 wr %g3, %g0, %clear_softint; \
282 retry; \
283 nop; \
284 nop; \
285 nop; \
286 nop
287
288#define H_T0_Interrupt_Level_4_0x44
289#define My_T0_Interrupt_Level_4_0x44 \
290 rd %softint, %g3; \
291 or %g0, 0x10, %g3; \
292 wr %g3, %g0, %clear_softint; \
293 retry; \
294 nop; \
295 nop; \
296 nop; \
297 nop
298
299#define H_T0_Interrupt_Level_5_0x45
300#define My_T0_Interrupt_Level_5_0x45 \
301 rd %softint, %g3; \
302 or %g0, 0x20, %g3; \
303 wr %g3, %g0, %clear_softint; \
304 retry; \
305 nop; \
306 nop; \
307 nop; \
308 nop
309
310#define H_T0_Interrupt_Level_6_0x46
311#define My_T0_Interrupt_Level_6_0x46 \
312 rd %softint, %g3; \
313 or %g0, 0x40, %g3; \
314 wr %g3, %g0, %clear_softint; \
315 retry; \
316 nop; \
317 nop; \
318 nop; \
319 nop
320
321#define H_T0_Interrupt_Level_7_0x47
322#define My_T0_Interrupt_Level_7_0x47 \
323 rd %softint, %g3; \
324 or %g0, 0x80, %g3; \
325 wr %g3, %g0, %clear_softint; \
326 retry; \
327 nop; \
328 nop; \
329 nop; \
330 nop
331
332#define H_T0_Interrupt_Level_8_0x48
333#define My_T0_Interrupt_Level_8_0x48 \
334 rd %softint, %g3; \
335 or %g0, 0x100, %g3; \
336 wr %g3, %g0, %clear_softint; \
337 retry; \
338 nop; \
339 nop; \
340 nop; \
341 nop
342
343#define H_T0_Interrupt_Level_9_0x49
344#define My_T0_Interrupt_Level_9_0x49 \
345 rd %softint, %g3; \
346 or %g0, 0x200, %g3; \
347 wr %g3, %g0, %clear_softint; \
348 retry; \
349 nop; \
350 nop; \
351 nop; \
352 nop
353
354#define H_T0_Interrupt_Level_10_0x4a
355#define My_T0_Interrupt_Level_10_0x4a \
356 rd %softint, %g3; \
357 or %g0, 0x400, %g3; \
358 wr %g3, %g0, %clear_softint; \
359 retry; \
360 nop; \
361 nop; \
362 nop; \
363 nop
364
365#define H_T0_Interrupt_Level_11_0x4b
366#define My_T0_Interrupt_Level_11_0x4b \
367 rd %softint, %g3; \
368 or %g0, 0x800, %g3; \
369 wr %g3, %g0, %clear_softint; \
370 retry; \
371 nop; \
372 nop; \
373 nop; \
374 nop
375
376#define H_T0_Interrupt_Level_12_0x4c
377#define My_T0_Interrupt_Level_12_0x4c \
378 rd %softint, %g3; \
379 sethi %hi(0x1000), %g3; \
380 wr %g3, %g0, %clear_softint; \
381 retry; \
382 nop; \
383 nop; \
384 nop; \
385 nop
386
387#define H_T0_Interrupt_Level_13_0x4d
388#define My_T0_Interrupt_Level_13_0x4d \
389 rd %softint, %g3; \
390 sethi %hi(0x2000), %g3; \
391 wr %g3, %g0, %clear_softint; \
392 retry; \
393 nop; \
394 nop; \
395 nop; \
396 nop
397
398#define H_T0_Interrupt_Level_15_0x4f
399#define My_T0_Interrupt_Level_15_0x4f \
400 sethi %hi(0x8000), %g3; \
401 wr %g3, %g0, %clear_softint; \
402 wr %g0, %g0, %pic;\
403 sethi %hi(0x80040000), %g2;\
404 rd %pcr, %g3;\
405 andn %g3, %g2, %g3;\
406 wr %g3, %g0, %pcr;\
407 retry;
408
409#define H_T1_Interrupt_Level_14_0x4e
410#define My_T1_Interrupt_Level_14_0x4e \
411 rd %softint, %g3; \
412 sethi %hi(0x14000), %g3; \
413 or %g3, 0x1, %g3; \
414 wr %g3, %g0, %clear_softint; \
415 rd %tick, %g3 ;\
416 retry; \
417
418#define H_T1_Interrupt_Level_1_0x41
419#define My_T1_Interrupt_Level_1_0x41 \
420 rd %softint, %g3; \
421 or %g0, 0x2, %g3; \
422 wr %g3, %g0, %clear_softint; \
423 retry; \
424 nop; \
425 nop; \
426 nop; \
427 nop
428
429#define H_T1_Interrupt_Level_2_0x42
430#define My_T1_Interrupt_Level_2_0x42 \
431 rd %softint, %g3; \
432 or %g0, 0x4, %g3; \
433 wr %g3, %g0, %clear_softint; \
434 retry; \
435 nop; \
436 nop; \
437 nop; \
438 nop
439
440#define H_T1_Interrupt_Level_3_0x43
441#define My_T1_Interrupt_Level_3_0x43 \
442 rd %softint, %g3; \
443 or %g0, 0x8, %g3; \
444 wr %g3, %g0, %clear_softint; \
445 retry; \
446 nop; \
447 nop; \
448 nop; \
449 nop
450
451#define H_T1_Interrupt_Level_4_0x44
452#define My_T1_Interrupt_Level_4_0x44 \
453 rd %softint, %g3; \
454 or %g0, 0x10, %g3; \
455 wr %g3, %g0, %clear_softint; \
456 retry; \
457 nop; \
458 nop; \
459 nop; \
460 nop
461
462#define H_T1_Interrupt_Level_5_0x45
463#define My_T1_Interrupt_Level_5_0x45 \
464 rd %softint, %g3; \
465 or %g0, 0x20, %g3; \
466 wr %g3, %g0, %clear_softint; \
467 retry; \
468 nop; \
469 nop; \
470 nop; \
471 nop
472
473#define H_T1_Interrupt_Level_6_0x46
474#define My_T1_Interrupt_Level_6_0x46 \
475 rd %softint, %g3; \
476 or %g0, 0x40, %g3; \
477 wr %g3, %g0, %clear_softint; \
478 retry; \
479 nop; \
480 nop; \
481 nop; \
482 nop
483
484#define H_T1_Interrupt_Level_7_0x47
485#define My_T1_Interrupt_Level_7_0x47 \
486 rd %softint, %g3; \
487 or %g0, 0x80, %g3; \
488 wr %g3, %g0, %clear_softint; \
489 retry; \
490 nop; \
491 nop; \
492 nop; \
493 nop
494
495#define H_T1_Interrupt_Level_8_0x48
496#define My_T1_Interrupt_Level_8_0x48 \
497 rd %softint, %g3; \
498 or %g0, 0x100, %g3; \
499 wr %g3, %g0, %clear_softint; \
500 retry; \
501 nop; \
502 nop; \
503 nop; \
504 nop
505
506#define H_T1_Interrupt_Level_9_0x49
507#define My_T1_Interrupt_Level_9_0x49 \
508 rd %softint, %g3; \
509 or %g0, 0x200, %g3; \
510 wr %g3, %g0, %clear_softint; \
511 retry; \
512 nop; \
513 nop; \
514 nop; \
515 nop
516
517#define H_T1_Interrupt_Level_10_0x4a
518#define My_T1_Interrupt_Level_10_0x4a \
519 rd %softint, %g3; \
520 or %g0, 0x400, %g3; \
521 wr %g3, %g0, %clear_softint; \
522 retry; \
523 nop; \
524 nop; \
525 nop; \
526 nop
527
528#define H_T1_Interrupt_Level_11_0x4b
529#define My_T1_Interrupt_Level_11_0x4b \
530 rd %softint, %g3; \
531 or %g0, 0x800, %g3; \
532 wr %g3, %g0, %clear_softint; \
533 retry; \
534 nop; \
535 nop; \
536 nop; \
537 nop
538
539#define H_T1_Interrupt_Level_12_0x4c
540#define My_T1_Interrupt_Level_12_0x4c \
541 rd %softint, %g3; \
542 sethi %hi(0x1000), %g3; \
543 wr %g3, %g0, %clear_softint; \
544 retry; \
545 nop; \
546 nop; \
547 nop; \
548 nop
549
550#define H_T1_Interrupt_Level_13_0x4d
551#define My_T1_Interrupt_Level_13_0x4d \
552 rd %softint, %g3; \
553 sethi %hi(0x2000), %g3; \
554 wr %g3, %g0, %clear_softint; \
555 retry; \
556 nop; \
557 nop; \
558 nop; \
559 nop
560
561#define H_T1_Interrupt_Level_15_0x4f
562#define My_T1_Interrupt_Level_15_0x4f \
563 sethi %hi(0x8000), %g3; \
564 wr %g3, %g0, %clear_softint; \
565 wr %g0, %g0, %pic;\
566 sethi %hi(0x80040000), %g2;\
567 rd %pcr, %g3;\
568 andn %g3, %g2, %g3;\
569 wr %g3, %g0, %pcr;\
570 retry;
571
572#define H_HT0_Interrupt_Level_14_0x4e
573#define My_HT0_Interrupt_Level_14_0x4e \
574 rd %softint, %g3; \
575 sethi %hi(0x14000), %g3; \
576 or %g3, 0x1, %g3; \
577 wr %g3, %g0, %clear_softint; \
578 rd %tick, %g3 ;\
579 sub %g3, 0x80, %g3;\
580 wrpr %g3, %g0, %tick;\
581 retry; \
582
583#define H_HT0_Interrupt_Level_1_0x41
584#define My_HT0_Interrupt_Level_1_0x41 \
585 rd %softint, %g3; \
586 or %g0, 0x2, %g3; \
587 wr %g3, %g0, %clear_softint; \
588 retry; \
589 nop; \
590 nop; \
591 nop; \
592 nop
593
594#define H_HT0_Interrupt_Level_2_0x42
595#define My_HT0_Interrupt_Level_2_0x42 \
596 rd %softint, %g3; \
597 or %g0, 0x4, %g3; \
598 wr %g3, %g0, %clear_softint; \
599 retry; \
600 nop; \
601 nop; \
602 nop; \
603 nop
604
605#define H_HT0_Interrupt_Level_3_0x43
606#define My_HT0_Interrupt_Level_3_0x43 \
607 rd %softint, %g3; \
608 or %g0, 0x8, %g3; \
609 wr %g3, %g0, %clear_softint; \
610 retry; \
611 nop; \
612 nop; \
613 nop; \
614 nop
615
616#define H_HT0_Interrupt_Level_4_0x44
617#define My_HT0_Interrupt_Level_4_0x44 \
618 rd %softint, %g3; \
619 or %g0, 0x10, %g3; \
620 wr %g3, %g0, %clear_softint; \
621 retry; \
622 nop; \
623 nop; \
624 nop; \
625 nop
626
627#define H_HT0_Interrupt_Level_5_0x45
628#define My_HT0_Interrupt_Level_5_0x45 \
629 rd %softint, %g3; \
630 or %g0, 0x20, %g3; \
631 wr %g3, %g0, %clear_softint; \
632 retry; \
633 nop; \
634 nop; \
635 nop; \
636 nop
637
638#define H_HT0_Interrupt_Level_6_0x46
639#define My_HT0_Interrupt_Level_6_0x46 \
640 rd %softint, %g3; \
641 or %g0, 0x40, %g3; \
642 wr %g3, %g0, %clear_softint; \
643 retry; \
644 nop; \
645 nop; \
646 nop; \
647 nop
648
649#define H_HT0_Interrupt_Level_7_0x47
650#define My_HT0_Interrupt_Level_7_0x47 \
651 rd %softint, %g3; \
652 or %g0, 0x80, %g3; \
653 wr %g3, %g0, %clear_softint; \
654 retry; \
655 nop; \
656 nop; \
657 nop; \
658 nop
659
660#define H_HT0_Interrupt_Level_8_0x48
661#define My_HT0_Interrupt_Level_8_0x48 \
662 rd %softint, %g3; \
663 or %g0, 0x100, %g3; \
664 wr %g3, %g0, %clear_softint; \
665 retry; \
666 nop; \
667 nop; \
668 nop; \
669 nop
670
671#define H_HT0_Interrupt_Level_9_0x49
672#define My_HT0_Interrupt_Level_9_0x49 \
673 rd %softint, %g3; \
674 or %g0, 0x200, %g3; \
675 wr %g3, %g0, %clear_softint; \
676 retry; \
677 nop; \
678 nop; \
679 nop; \
680 nop
681
682#define H_HT0_Interrupt_Level_10_0x4a
683#define My_HT0_Interrupt_Level_10_0x4a \
684 rd %softint, %g3; \
685 or %g0, 0x400, %g3; \
686 wr %g3, %g0, %clear_softint; \
687 retry; \
688 nop; \
689 nop; \
690 nop; \
691 nop
692
693#define H_HT0_Interrupt_Level_11_0x4b
694#define My_HT0_Interrupt_Level_11_0x4b \
695 rd %softint, %g3; \
696 or %g0, 0x800, %g3; \
697 wr %g3, %g0, %clear_softint; \
698 retry; \
699 nop; \
700 nop; \
701 nop; \
702 nop
703
704#define H_HT0_Interrupt_Level_12_0x4c
705#define My_HT0_Interrupt_Level_12_0x4c \
706 rd %softint, %g3; \
707 sethi %hi(0x1000), %g3; \
708 wr %g3, %g0, %clear_softint; \
709 retry; \
710 nop; \
711 nop; \
712 nop; \
713 nop
714
715#define H_HT0_Interrupt_Level_13_0x4d
716#define My_HT0_Interrupt_Level_13_0x4d \
717 rd %softint, %g3; \
718 sethi %hi(0x2000), %g3; \
719 wr %g3, %g0, %clear_softint; \
720 retry; \
721 nop; \
722 nop; \
723 nop; \
724 nop
725
726#define H_HT0_Interrupt_Level_15_0x4f
727#define My_HT0_Interrupt_Level_15_0x4f \
728 sethi %hi(0x8000), %g3; \
729 wr %g3, %g0, %clear_softint; \
730 wr %g0, %g0, %pic;\
731 sethi %hi(0x80040000), %g2;\
732 rd %pcr, %g3;\
733 andn %g3, %g2, %g3;\
734 wr %g3, %g0, %pcr;\
735 retry;
736
737
738!!!!!!!!!!!!!!!!!!!!!! END of all handlers !!!!!!!!!!!!!!!!!!!
739
Full OpenSPARC design & verification tarball including full HDL.