[OpenSPARC-T2-DV] / verif / diag / assembly / niu / niu_pio_regs1.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: niu_pio_regs1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
!#include "asi_s.h"


#define FZC_PIO_BASE_ADDRESS   0x080000
#define NIU_BASE_ADDRESS       0x8100000000
#define PIO_ADDRESS_RANGE      mpeval(NIU_BASE_ADDRESS + FZC_PIO_BASE_ADDRESS)

#define PIO_DMA_BIND		0x10000
#define PIO_LDG_NUM 		0x20000
#define PIO_LDGITMRES 		0x00008
#define PIO_SID 		0x10200
#define PIO_SMX_CFIG_DAT 	0x00040
#define PIO_SMX_CTL      	0x00050
#define PIO_SMX_DBG_VEC      	0x00058
#define PIO_DBG_SEL      	0x00060
#define PIO_TRAIN_VEC      	0x00068
#define PIO_ARB_CTL      	0x00070
#define PIO_ARB_DBG_VEC      	0x00078

#define DMA_BIND           	mpeval(PIO_ADDRESS_RANGE + PIO_DMA_BIND)
#define LDG_NUM           	mpeval(PIO_ADDRESS_RANGE + PIO_LDG_NUM)
#define LDGITMRES            	mpeval(PIO_ADDRESS_RANGE + PIO_LDGITMRES)
#define SID                  	mpeval(PIO_ADDRESS_RANGE + PIO_SID)
#define ARB_CTL         	mpeval(PIO_ADDRESS_RANGE + PIO_ARB_CTL)
#define ARB_DBG_VEC         	mpeval(PIO_ADDRESS_RANGE + PIO_ARB_DBG_VEC)
#define SMX_CTL         	mpeval(PIO_ADDRESS_RANGE + PIO_SMX_CTL)
#define SMX_DBG_VEC         	mpeval(PIO_ADDRESS_RANGE + PIO_SMX_DBG_VEC)
#define DBG_SEL         	mpeval(PIO_ADDRESS_RANGE + PIO_DBG_SEL)
#define TRAIN_VEC         	mpeval(PIO_ADDRESS_RANGE + PIO_TRAIN_VEC)
#define SMX_CFIG_DAT         	mpeval(PIO_ADDRESS_RANGE + PIO_SMX_CFIG_DAT)

#define DMA_BIND_DATA_MASK   	0x0000000000003f3f
#define DATA_EN_32BITS    	0x00000000ffffffff
#define DATA_EN_20BITS    	0x00000000000fffff
#define DATA_EN_6BITS    	0x000000000000003f
#define DATA_EN_7BITS    	0x000000000000007f
#define SMX_CFIG_DAT_DATA_MASK 	0x00000000cfffffff

.text
.global	 main


main:
    ta   T_CHANGE_HPRIV

get_th_id:
    ta   T_RD_THID

//    cmp  %o1,0x0
//    bne  test_pass
    nop

!Write then read data of  PIO_ARB_DBG_VEC  
 setx ARB_DBG_VEC,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop1:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_32BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop1
    nop


!Write then read data of  PIO_ARB_CTL  
 setx ARB_CTL,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop2:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_32BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop2
    nop


!Write then read data of  PIO_TRAIN_VEC  
 setx TRAIN_VEC,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop3:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_32BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop3
    nop


!Write then read data of  PIO_SMX_DBG_VEC  
 setx SMX_DBG_VEC,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop4:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_32BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop4
    nop


!Write then read data of  PIO_DBG_SEL  
 setx DBG_SEL,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop5:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_6BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop5
    nop


!Write then read data of  PIO_SMX_DBG_VEC  
 setx SMX_DBG_VEC,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop6:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_32BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop6
    nop


!Write then read data of  PIO_SMX_CTL  count 64 step 8 
 setx SMX_CTL,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop7:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_32BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop7
    nop


!Write then read data of  PIO_SMX_CFIG_DAT  count 64 step 8 
 setx SMX_CFIG_DAT,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop8:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx SMX_CFIG_DAT_DATA_MASK, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop8
    nop


!Write then read data of  PIO_LDGITMRES  count 64 step 8 
 setx LDGITMRES,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop9:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_20BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop9
    nop


!Write then read data of  PIO_DMA_BIND  count 64 step 8 
 setx DMA_BIND,%g7,%g1
    setx wdata,%g7,%g2
    set  64,%g8

loop10:
    set  0x05,%g3
loop11:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DMA_BIND_DATA_MASK, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop11
    nop
    add  %g1,8,%g1
    sub  %g8,1,%g8
    cmp  %g8,%g0
    bne  loop10	 
    nop


/******************************************************
 * Exit code
 *******************************************************/

test_pass:
EXIT_GOOD

test_fail:
EXIT_BAD


.data
.align 0x100
wdata:
    .xword 0xffffffffffffffff
    .xword 0xaaaaaaaaaaaaaaaa
    .xword 0x0000000000000000
    .xword 0x5555555555555555
    .xword 0x0123456789abcdef

.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: niu_pio_regs1.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#include "hboot.s"
	42	!#include "asi_s.h"
	43
	44
	45
	46
	47	#define FZC_PIO_BASE_ADDRESS 0x080000
	48	#define NIU_BASE_ADDRESS 0x8100000000
	49	#define PIO_ADDRESS_RANGE mpeval(NIU_BASE_ADDRESS + FZC_PIO_BASE_ADDRESS)
	50
	51	#define PIO_DMA_BIND 0x10000
	52	#define PIO_LDG_NUM 0x20000
	53	#define PIO_LDGITMRES 0x00008
	54	#define PIO_SID 0x10200
	55	#define PIO_SMX_CFIG_DAT 0x00040
	56	#define PIO_SMX_CTL 0x00050
	57	#define PIO_SMX_DBG_VEC 0x00058
	58	#define PIO_DBG_SEL 0x00060
	59	#define PIO_TRAIN_VEC 0x00068
	60	#define PIO_ARB_CTL 0x00070
	61	#define PIO_ARB_DBG_VEC 0x00078
	62
	63	#define DMA_BIND mpeval(PIO_ADDRESS_RANGE + PIO_DMA_BIND)
	64	#define LDG_NUM mpeval(PIO_ADDRESS_RANGE + PIO_LDG_NUM)
65	#define LDGITMRES mpeval(PIO_ADDRESS_RANGE + PIO_LDGITMRES)
66	#define SID mpeval(PIO_ADDRESS_RANGE + PIO_SID)
67	#define ARB_CTL mpeval(PIO_ADDRESS_RANGE + PIO_ARB_CTL)
68	#define ARB_DBG_VEC mpeval(PIO_ADDRESS_RANGE + PIO_ARB_DBG_VEC)
69	#define SMX_CTL mpeval(PIO_ADDRESS_RANGE + PIO_SMX_CTL)
70	#define SMX_DBG_VEC mpeval(PIO_ADDRESS_RANGE + PIO_SMX_DBG_VEC)
71	#define DBG_SEL mpeval(PIO_ADDRESS_RANGE + PIO_DBG_SEL)
72	#define TRAIN_VEC mpeval(PIO_ADDRESS_RANGE + PIO_TRAIN_VEC)
73	#define SMX_CFIG_DAT mpeval(PIO_ADDRESS_RANGE + PIO_SMX_CFIG_DAT)
74
75	#define DMA_BIND_DATA_MASK 0x0000000000003f3f
76	#define DATA_EN_32BITS 0x00000000ffffffff
77	#define DATA_EN_20BITS 0x00000000000fffff
78	#define DATA_EN_6BITS 0x000000000000003f
79	#define DATA_EN_7BITS 0x000000000000007f
80	#define SMX_CFIG_DAT_DATA_MASK 0x00000000cfffffff
81
82	.text
83	.global main
84
85
86	main:
87	ta T_CHANGE_HPRIV
88
89	get_th_id:
90	ta T_RD_THID
91
92	// cmp %o1,0x0
93	// bne test_pass
94	nop
95
96	!Write then read data of PIO_ARB_DBG_VEC
97	setx ARB_DBG_VEC,%g7,%g1
98	setx wdata,%g7,%g2
99
100	set 0x05,%g3
101	loop1:
102	ldx [%g2],%g4
103	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
104
105	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
106	setx DATA_EN_32BITS, %g7, %g6
107	and %g4, %g6, %g4
108
109	cmp %g4, %g5
110
111	bne %xcc, test_fail
112
113
114	add %g2,8,%g2
115	sub %g3,1,%g3
116	cmp %g3,%g0
117	bne loop1
118	nop
119
120
121
122	!Write then read data of PIO_ARB_CTL
123	setx ARB_CTL,%g7,%g1
124	setx wdata,%g7,%g2
125
126	set 0x05,%g3
127	loop2:
128	ldx [%g2],%g4
129	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
130
131	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
132	setx DATA_EN_32BITS, %g7, %g6
133	and %g4, %g6, %g4
134
135	cmp %g4, %g5
136
137	bne %xcc, test_fail
138
139
140	add %g2,8,%g2
141	sub %g3,1,%g3
142	cmp %g3,%g0
143	bne loop2
144	nop
145
146
147	!Write then read data of PIO_TRAIN_VEC
148	setx TRAIN_VEC,%g7,%g1
149	setx wdata,%g7,%g2
150
151	set 0x05,%g3
152	loop3:
153	ldx [%g2],%g4
154	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
155
156	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
157	setx DATA_EN_32BITS, %g7, %g6
158	and %g4, %g6, %g4
159
160	cmp %g4, %g5
161
162	bne %xcc, test_fail
163
164
165	add %g2,8,%g2
166	sub %g3,1,%g3
167	cmp %g3,%g0
168	bne loop3
169	nop
170
171
172
173	!Write then read data of PIO_SMX_DBG_VEC
174	setx SMX_DBG_VEC,%g7,%g1
175	setx wdata,%g7,%g2
176
177	set 0x05,%g3
178	loop4:
179	ldx [%g2],%g4
180	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
181
182	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
183	setx DATA_EN_32BITS, %g7, %g6
184	and %g4, %g6, %g4
185
186	cmp %g4, %g5
187
188	bne %xcc, test_fail
189
190
191	add %g2,8,%g2
192	sub %g3,1,%g3
193	cmp %g3,%g0
194	bne loop4
195	nop
196
197
198
199
200	!Write then read data of PIO_DBG_SEL
201	setx DBG_SEL,%g7,%g1
202	setx wdata,%g7,%g2
203
204	set 0x05,%g3
205	loop5:
206	ldx [%g2],%g4
207	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
208
209	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
210	setx DATA_EN_6BITS, %g7, %g6
211	and %g4, %g6, %g4
212
213	cmp %g4, %g5
214
215	bne %xcc, test_fail
216
217
218	add %g2,8,%g2
219	sub %g3,1,%g3
220	cmp %g3,%g0
221	bne loop5
222	nop
223
224
225	!Write then read data of PIO_SMX_DBG_VEC
226	setx SMX_DBG_VEC,%g7,%g1
227	setx wdata,%g7,%g2
228
229	set 0x05,%g3
230	loop6:
231	ldx [%g2],%g4
232	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
233
234	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
235	setx DATA_EN_32BITS, %g7, %g6
236	and %g4, %g6, %g4
237
238	cmp %g4, %g5
239
240	bne %xcc, test_fail
241
242
243	add %g2,8,%g2
244	sub %g3,1,%g3
245	cmp %g3,%g0
246	bne loop6
247	nop
248
249
250
251	!Write then read data of PIO_SMX_CTL count 64 step 8
252	setx SMX_CTL,%g7,%g1
253	setx wdata,%g7,%g2
254
255	set 0x05,%g3
256	loop7:
257	ldx [%g2],%g4
258	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
259
260	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
261	setx DATA_EN_32BITS, %g7, %g6
262	and %g4, %g6, %g4
263
264	cmp %g4, %g5
265
266	bne %xcc, test_fail
267
268
269	add %g2,8,%g2
270	sub %g3,1,%g3
271	cmp %g3,%g0
272	bne loop7
273	nop
274
275
276
277
278	!Write then read data of PIO_SMX_CFIG_DAT count 64 step 8
279	setx SMX_CFIG_DAT,%g7,%g1
280	setx wdata,%g7,%g2
281
282	set 0x05,%g3
283	loop8:
284	ldx [%g2],%g4
285	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
286
287	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
288	setx SMX_CFIG_DAT_DATA_MASK, %g7, %g6
289	and %g4, %g6, %g4
290
291	cmp %g4, %g5
292
293	bne %xcc, test_fail
294
295
296	add %g2,8,%g2
297	sub %g3,1,%g3
298	cmp %g3,%g0
299	bne loop8
300	nop
301
302
303	!Write then read data of PIO_LDGITMRES count 64 step 8
304	setx LDGITMRES,%g7,%g1
305	setx wdata,%g7,%g2
306
307	set 0x05,%g3
308	loop9:
309	ldx [%g2],%g4
310	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
311
312	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
313	setx DATA_EN_20BITS, %g7, %g6
314	and %g4, %g6, %g4
315
316	cmp %g4, %g5
317
318	bne %xcc, test_fail
319
320
321	add %g2,8,%g2
322	sub %g3,1,%g3
323	cmp %g3,%g0
324	bne loop9
325	nop
326
327
328	!Write then read data of PIO_DMA_BIND count 64 step 8
329	setx DMA_BIND,%g7,%g1
330	setx wdata,%g7,%g2
331	set 64,%g8
332
333	loop10:
334	set 0x05,%g3
335	loop11:
336	ldx [%g2],%g4
337	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
338
339	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
340	setx DMA_BIND_DATA_MASK, %g7, %g6
341	and %g4, %g6, %g4
342
343	cmp %g4, %g5
344
345	bne %xcc, test_fail
346
347
348	add %g2,8,%g2
349	sub %g3,1,%g3
350	cmp %g3,%g0
351	bne loop11
352	nop
353	add %g1,8,%g1
354	sub %g8,1,%g8
355	cmp %g8,%g0
356	bne loop10
357	nop
358
359
360
361
362
363
364
365	/******************************************************
366	* Exit code
367	*******************************************************/
368
369	test_pass:
370	EXIT_GOOD
371
372	test_fail:
373	EXIT_BAD
374
375
376	.data
377	.align 0x100
378	wdata:
379	.xword 0xffffffffffffffff
380	.xword 0xaaaaaaaaaaaaaaaa
381	.xword 0x0000000000000000
382	.xword 0x5555555555555555
383	.xword 0x0123456789abcdef
384
385	.end