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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / niu / niu_zcp_regs1.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: niu_zcp_regs1.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41#include "hboot.s"
42!#include "asi_s.h"
43
44
45
46
47#define FZC_ZCP_BASE_ADDRESS 0x580000
48#define NIU_BASE_ADDRESS 0x8100000000
49#define ZCP_ADDRESS_RANGE mpeval(NIU_BASE_ADDRESS + FZC_ZCP_BASE_ADDRESS)
50
51#define ZCP_RDC_TBL 0x10000
52#define RDC_TBL mpeval(ZCP_ADDRESS_RANGE + ZCP_RDC_TBL)
53
54#define ZCP_CFIG 0x00000
55#define CFIG mpeval(ZCP_ADDRESS_RANGE + ZCP_CFIG)
56
57#define ZCP_INT_STAT_TEST 0x00108
58#define INT_STAT_TEST mpeval(ZCP_ADDRESS_RANGE + ZCP_INT_STAT_TEST)
59
60#define ZCP_INT_MASK 0x00010
61#define INT_MASK mpeval(ZCP_ADDRESS_RANGE + ZCP_INT_MASK)
62
63#define ZCP_BAM4BUF 0x00018
64#define ZCP_BAM8BUF 0x00020
65#define ZCP_BAM16BUF 0x00028
66#define ZCP_BAM32BUF 0x00030
67#define BAM4BUF mpeval(ZCP_ADDRESS_RANGE + ZCP_BAM4BUF)
68
69
70#define ZCP_DST4BUF 0x00038
71#define ZCP_DST8BUF 0x00040
72#define ZCP_DST16BUF 0x00048
73#define ZCP_DST32BUF 0x00050
74#define DST4BUF mpeval(ZCP_ADDRESS_RANGE + ZCP_DST4BUF)
75
76#define ZCP_RAM_DATA0 0x00058
77#define ZCP_RAM_DATA1 0x00060
78#define ZCP_RAM_DATA2 0x00068
79#define ZCP_RAM_DATA3 0x00070
80#define ZCP_RAM_DATA4 0x00078
81#define RAM_DATA0 mpeval(ZCP_ADDRESS_RANGE + ZCP_RAM_DATA0)
82
83#define ZCP_RAM_BE0 0x00080
84#define RAM_BE0 mpeval(ZCP_ADDRESS_RANGE + ZCP_RAM_BE0)
85
86#define ZCP_RAM_ACC 0x00088
87#define RAM_ACC mpeval(ZCP_ADDRESS_RANGE + ZCP_RAM_ACC)
88
89#define ZCP_BIT_DATA 0x00090
90#define BIT_DATA mpeval(ZCP_ADDRESS_RANGE + ZCP_BIT_DATA)
91
92#define ZCP_RESET_CFIFO 0x00098
93#define RESET_CFIFO mpeval(ZCP_ADDRESS_RANGE + ZCP_RESET_CFIFO)
94
95#define ZCP_TRAINING_VECTOR 0x000c0
96#define TRAINING_VECTOR mpeval(ZCP_ADDRESS_RANGE + ZCP_TRAINING_VECTOR)
97
98/*
99#define ZCP_CFIFO_ECC_PORT2 0x000b0
100#define CFIFO_ECC_PORT2 mpeval(ZCP_ADDRESS_RANGE + ZCP_CFIFO_ECC_PORT2)
101*/
102
103#define DATA_EN_32BITS 0x00000000ffffffff
104#define DATA_EN_31BITS 0x000000007fffffff
105#define DATA_EN_25BITS 0x0000000001ffffff
106#define DATA_EN_20BITS 0x00000000000fffff
107#define DATA_EN_17BITS 0x000000000001ffff
108#define DATA_EN_16BITS 0x000000000000ffff
109#define DATA_EN_14BITS 0x0000000000003fff
110#define DATA_EN_10BITS 0x00000000000003ff
111#define DATA_EN_8BITS 0x00000000000000ff
112#define DATA_EN_7BITS 0x000000000000007f
113#define DATA_EN_6BITS 0x000000000000003f
114#define DATA_EN_4BITS 0x000000000000000f
115
116#define INT_STAT_TEST_DATA_MASK 0x000000000000dfff
117
118.text
119.global main
120
121
122main:
123 ta T_CHANGE_HPRIV
124
125get_th_id:
126 ta T_RD_THID
127
128 cmp %o1,0x0
129 bne test_pass
130 nop
131
132
133!Write then read data of ZCP_CFIG
134 setx CFIG,%g7,%g1
135 setx wdata,%g7,%g2
136
137 set 0x05,%g3
138loop1:
139 ldx [%g2],%g4
140 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
141
142 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
143 setx DATA_EN_25BITS, %g7, %g6
144 and %g4, %g6, %g4
145
146 cmp %g4, %g5
147
148 bne %xcc, test_fail
149
150
151 add %g2,8,%g2
152 sub %g3,1,%g3
153 cmp %g3,%g0
154 bne loop1
155 nop
156
157
158
159!Write then read data of ZCP_INT_STAT_TEST
160 setx INT_STAT_TEST,%g7,%g1
161 setx wdata,%g7,%g2
162
163 set 0x05,%g3
164loop2:
165 ldx [%g2],%g4
166 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
167
168 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
169 setx INT_STAT_TEST_DATA_MASK, %g7, %g6
170 and %g4, %g6, %g4
171
172 cmp %g4, %g5
173
174 bne %xcc, test_fail
175
176
177 add %g2,8,%g2
178 sub %g3,1,%g3
179 cmp %g3,%g0
180 bne loop2
181 nop
182
183
184
185!Write then read data of ZCP_INT_MASK
186 setx INT_MASK,%g7,%g1
187 setx wdata,%g7,%g2
188
189 set 0x05,%g3
190loop3:
191 ldx [%g2],%g4
192 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
193
194 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
195 setx DATA_EN_16BITS, %g7, %g6
196 and %g4, %g6, %g4
197
198 cmp %g4, %g5
199
200 bne %xcc, test_fail
201
202
203 add %g2,8,%g2
204 sub %g3,1,%g3
205 cmp %g3,%g0
206 bne loop3
207 nop
208
209!Write then read data of ZCP_RAM_BE0
210 setx RAM_BE0,%g7,%g1
211 setx wdata,%g7,%g2
212
213 set 0x05,%g3
214loop4:
215 ldx [%g2],%g4
216 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
217
218 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
219 setx DATA_EN_17BITS, %g7, %g6
220 and %g4, %g6, %g4
221
222 cmp %g4, %g5
223
224 bne %xcc, test_fail
225
226
227 add %g2,8,%g2
228 sub %g3,1,%g3
229 cmp %g3,%g0
230 bne loop4
231 nop
232
233
234
235!Write then read data of ZCP_RAM_ACC
236 setx RAM_ACC,%g7,%g1
237 setx wdata,%g7,%g2
238
239 set 0x05,%g3
240loop5:
241 ldx [%g2],%g4
242 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
243
244 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
245 setx DATA_EN_31BITS, %g7, %g6
246 and %g4, %g6, %g4
247
248 cmp %g4, %g5
249
250 bne %xcc, test_fail
251
252
253 add %g2,8,%g2
254 sub %g3,1,%g3
255 cmp %g3,%g0
256 bne loop5
257 nop
258
259
260!Write then read data of ZCP_BIT_DATA
261 setx BIT_DATA,%g7,%g1
262 setx wdata,%g7,%g2
263
264 set 0x05,%g3
265loop6:
266 ldx [%g2],%g4
267 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
268
269 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
270 setx DATA_EN_17BITS, %g7, %g6
271 and %g4, %g6, %g4
272
273 cmp %g4, %g5
274
275 bne %xcc, test_fail
276
277
278 add %g2,8,%g2
279 sub %g3,1,%g3
280 cmp %g3,%g0
281 bne loop6
282 nop
283
284
285
286!Write then read data of ZCP_RESET_CFIFO
287 setx RESET_CFIFO,%g7,%g1
288 setx wdata,%g7,%g2
289
290 set 0x05,%g3
291loop7:
292 ldx [%g2],%g4
293 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
294
295 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
296 setx DATA_EN_4BITS, %g7, %g6
297 and %g4, %g6, %g4
298
299 cmp %g4, %g5
300
301 bne %xcc, test_fail
302
303
304 add %g2,8,%g2
305 sub %g3,1,%g3
306 cmp %g3,%g0
307 bne loop7
308 nop
309
310
311
312!Write then read data of ZCP_TRAINING_VECTOR
313 setx TRAINING_VECTOR,%g7,%g1
314 setx wdata,%g7,%g2
315
316 set 0x05,%g3
317loop8:
318 ldx [%g2],%g4
319 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
320
321 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
322 setx DATA_EN_32BITS, %g7, %g6
323 and %g4, %g6, %g4
324
325 cmp %g4, %g5
326
327 bne %xcc, test_fail
328
329
330 add %g2,8,%g2
331 sub %g3,1,%g3
332 cmp %g3,%g0
333 bne loop8
334 nop
335
336!Write then read data of ZCP_BAM4BUF, BAM8BUF,BAM16BUF,BAM32BUF
337 setx BAM4BUF,%g7,%g1
338 setx wdata,%g7,%g2
339 set 4,%g8
340
341loop10:
342 set 0x05,%g3
343loop11:
344 ldx [%g2],%g4
345 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
346
347 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
348 setx DATA_EN_32BITS, %g7, %g6
349 and %g4, %g6, %g4
350
351 cmp %g4, %g5
352
353 bne %xcc, test_fail
354
355
356 add %g2,8,%g2
357 sub %g3,1,%g3
358 cmp %g3,%g0
359 bne loop11
360 nop
361 add %g1,8,%g1
362 sub %g8,1,%g8
363 cmp %g8,%g0
364 bne loop10
365 nop
366
367
368!Write then read data of ZCP_DST4BUF, DST8BUF,DST16BUF,DST32BUF
369 setx DST4BUF,%g7,%g1
370 setx wdata,%g7,%g2
371 set 4,%g8
372
373loop12:
374 set 0x05,%g3
375loop13:
376 ldx [%g2],%g4
377 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
378
379 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
380 setx DATA_EN_10BITS, %g7, %g6
381 and %g4, %g6, %g4
382
383 cmp %g4, %g5
384
385 bne %xcc, test_fail
386
387
388 add %g2,8,%g2
389 sub %g3,1,%g3
390 cmp %g3,%g0
391 bne loop13
392 nop
393 add %g1,8,%g1
394 sub %g8,1,%g8
395 cmp %g8,%g0
396 bne loop12
397 nop
398
399
400!Write then read data of ZCP_RAM_DATA0~ZCP_RAM_DATA4
401 setx RAM_DATA0,%g7,%g1
402 setx wdata,%g7,%g2
403 set 5,%g8
404
405loop14:
406 set 0x05,%g3
407loop15:
408 ldx [%g2],%g4
409 stxa %g4,[%g1]ASI_PRIMARY_LITTLE
410
411 ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
412 setx DATA_EN_32BITS, %g7, %g6
413 and %g4, %g6, %g4
414
415 cmp %g4, %g5
416
417 bne %xcc, test_fail
418
419
420 add %g2,8,%g2
421 sub %g3,1,%g3
422 cmp %g3,%g0
423 bne loop15
424 nop
425 add %g1,8,%g1
426 sub %g8,1,%g8
427 cmp %g8,%g0
428 bne loop14
429 nop
430
431
432
433
434
435/******************************************************
436 * Exit code
437 *******************************************************/
438
439test_pass:
440EXIT_GOOD
441
442test_fail:
443EXIT_BAD
444
445
446.data
447.align 0x100
448wdata:
449 .xword 0xffffffffffffffff
450 .xword 0xaaaaaaaaaaaaaaaa
451 .xword 0x0000000000000000
452 .xword 0x5555555555555555
453 .xword 0x0123456789abcdef
454
455.end
Full OpenSPARC design & verification tarball including full HDL.