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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: PCIeDMARw.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define ENABLE_PCIE_LINK_TRAINING | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #include "hboot.s" | |
42 | #include "peu_defines.h" | |
43 | ||
44 | #define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA) | |
45 | ||
46 | #define DMA_DATA_ADDR 0x0000000123456000 | |
47 | #define DMA_DATA_BYP_SADDR 0xfffc000123456000 | |
48 | #define DMA_DATA_BYP_EADDR 0xfffc000123456800 | |
49 | ||
50 | #define DMA_DATA_BYP_ADDR1 0xfffc000123457000 | |
51 | #define DMA_DATA_BYP_ADDR2 0xfffc000123457100 | |
52 | #define DMA_DATA_BYP_ADDR3 0xfffc000123457200 | |
53 | #define DMA_DATA_BYP_ADDR4 0xfffc000123457300 | |
54 | #define DMA_DATA_BYP_ADDR5 0xfffc000123457400 | |
55 | #define DMA_DATA_BYP_ADDR6 0xfffc000123457500 | |
56 | #define DMA_DATA_BYP_ADDR7 0xfffc000123457600 | |
57 | #define DMA_DATA_BYP_ADDR8 0xfffc000123457700 | |
58 | #define DMA_DATA_BYP_ADDR9 0xfffc000123457800 | |
59 | ||
60 | /************************************************************************ | |
61 | Test case code start | |
62 | ************************************************************************/ | |
63 | .text | |
64 | .global main | |
65 | ||
66 | main: | |
67 | ta T_CHANGE_HPRIV | |
68 | nop | |
69 | ||
70 | ! see if this user event works in a loop (multi-shot) | |
71 | ||
72 | mov 0x02, %g4 | |
73 | UsrEvnt1: | |
74 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt1)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_EADDR, "64'h40", 1, *, * ) | |
75 | UsrEvnt2: | |
76 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR2, "64'h40", 1 ) | |
77 | nop | |
78 | nop | |
79 | dec %g4 | |
80 | brnz %g4, UsrEvnt1 | |
81 | nop | |
82 | nop | |
83 | ||
84 | UsrEvnt3: !! this DMA Read will have 2 completions, since it is longer than 128 bytes (default MPS) | |
85 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt3)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_EADDR, "64'h100", 1, *, * ) | |
86 | ||
87 | UsrEvnt4: | |
88 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt4)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR3, "64'h80", 1 ) | |
89 | ||
90 | UsrEvnt5: | |
91 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt5)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR4, "64'h20", 1 ) | |
92 | ||
93 | UsrEvnt6: | |
94 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt6)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR4, DMA_DATA_BYP_ADDR5, "64'h10", 1 ) | |
95 | ||
96 | UsrEvnt7: | |
97 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt7)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR5, DMA_DATA_BYP_ADDR6, "64'h8", 1 ) | |
98 | ||
99 | UsrEvnt8: | |
100 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt8)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR6, DMA_DATA_BYP_ADDR7, "64'h4", 1 ) | |
101 | ||
102 | UsrEvnt9: | |
103 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt9)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR7, DMA_DATA_BYP_ADDR8, "64'h2", 1 ) | |
104 | ||
105 | UsrEvnt10: | |
106 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt10)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR9, "64'h1", 1 ) | |
107 | ||
108 | UsrEvnt11: | |
109 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt11)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR9, "64'h0", 1 ) | |
110 | ||
111 | UsrEvnt12: | |
112 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt12)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR9, DMA_DATA_BYP_ADDR9, "64'h0", 1 ) | |
113 | ||
114 | ! select a MEM32 address in PCI address range and transmit the command to NCU | |
115 | ||
116 | setx MEM32_RD_ADDR, %g1, %g2 | |
117 | ||
118 | stx %g1, [%g2] ! MEM32 PIO Write | |
119 | stx %g2, [%g2+8] ! MEM32 PIO Write | |
120 | stx %g3, [%g2+16] ! MEM32 PIO Write | |
121 | ||
122 | ldx [%g2], %l0 ! MEM32 PIO READ | |
123 | ldx [%g2+8], %l1 ! MEM32 PIO READ | |
124 | ldx [%g2+16], %l2 ! MEM32 PIO READ | |
125 | ||
126 | ||
127 | test_passed: | |
128 | EXIT_GOOD | |
129 | ||
130 | ||
131 | test_failed: | |
132 | EXIT_BAD | |
133 | ||
134 | ||
135 | ||
136 | /************************************************************************ | |
137 | Test case data start | |
138 | ************************************************************************/ | |
139 | ||
140 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
141 | attr_data { | |
142 | Name = .DATA, | |
143 | hypervisor, | |
144 | compressimage | |
145 | } | |
146 | .data | |
147 | init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004) | |
148 | /************************************************************************/ |