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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeLinkDisable.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: PCIeLinkDisable.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39#define MAIN_PAGE_HV_ALSO
40#define RESET_STAT_CHECK
41#define RESET_CHECK_REG
42
43#include "hboot.s"
44#include "peu_defines.h"
45#include "dmu_peu_regs.h"
46#include "rst_defines.h"
47
48#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) | IO_ACCESS_PA)
49
50#define DMA_DATA_ADDR 0x0000000123457000
51#define DMA_DATA_BYP_ADDR1 0xfffc000123457000
52#define DMA_DATA_BYP_ADDR2 0xfffc000123457100
53#define DMA_DATA_BYP_ADDR3 0xfffc000123457200
54#define DMA_DATA_BYP_ADDR4 0xfffc000123457300
55
56/*
57Test case code start
58*/
59.text
60.global main
61
62main:
63 ta T_CHANGE_HPRIV
64 nop
65
66/************************************************************
67 Check if this is the first time thru here
68 ************************************************************/
69 setx test_entered, %g1, %g2
70 ldx [%g2], %g3
71 brnz %g3, After_Warm_Reset
72 nop
73
74! First time thru, Store a non-zero value there
75 dec %g3
76 stx %g3, [%g2]
77
78/************************************************************
79 Link Disable
80 ************************************************************/
81Set_Detect_Quiet:
82 ! set bit to remain in Detect.Quiet state
83 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
84 ldx [%g3], %g4
85 mov 0x100, %g5
86 orcc %g5, %g4, %g5 ! OR in bit 8 == 1
87 stx %g5, [%g3]
88 ldx [%g3], %g4
89
90Set_Link_Disable:
91 ! set the Disable bit
92 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_ADDR, %g1, %g3
93 mov 0x010, %g5
94 stx %g5, [%g3]
95 ldx [%g3], %g4
96
97 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3 ! 0x680000
98 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g4 ! 0x681018
99 mov 25, %l1 ! loop timeout count
100 setx 0x0000020000000200, %g1, %g5 ! mask for Link Down Primary & Secondary events
101
102! Wait for Link Down primary or secondary event before doing a Warm Reset
103Wait4LinkDown:
104 ldx [%g3 + 8], %l3 ! read the PEU Status Reg
105 ldx [%g4], %l4 ! read the PEU Other Event Status Clear Reg
106 andcc %l4, %g5, %l5
107 bne %xcc, do_WARM_RESET
108 nop
109 dec %l1
110 brnz %l1, Wait4LinkDown
111 nop
112 b test_failed
113 nop
114
115/************************************************************
116 Now do WARM RESET
117 ************************************************************/
118do_WARM_RESET:
119 stx %l4, [%g4] ! clear the PEU Other Event Status Clear Reg
120
121#ifdef PCIE_USE_SSYS_RESET
122 setx RST_SSYS_RESET, %g1, %g5 ! subsystem reset reg
123 mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data
124 stx %g7, [%g5] ! Subsystem Reset
125
126 mov 255, %l0 ! loop timeout count
127
128Wait4SsysReset:
129 ldx [%g5], %l7 ! check if reset bit has cleared
130 brz %l7, redo_link_training
131 nop
132 dec %l0
133 brnz %l0, Wait4SsysReset
134 nop
135 ba test_failed ! Subsystem reset should have completed
136 nop
137/************************************************************
138 Now redo link training...
139 ************************************************************/
140redo_link_training:
141 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g2, %g3
142 ldx [%g3], %g4
143 mov 0x0010, %g5 ! FAST LINK MODE, for simulation.
144 or %g4, %g5, %g5
145 stx %g5, [%g3]
146
147 ! clear bit 8, to not remain in Detect.Quiet state
148 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
149 mov 0x001, %l4
150 stx %l4, [%g3]
151
152 ! enable bypass in IOMMU
153 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
154 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
155 stx %g3, [%g2]
156
157! wait for the "Link Up" status bit to get set in the PEU
158! (this code copied from peu_init.h)
159
160 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
161 ldx [%g3], %l4
162 stx %l4, [%g3] ! clear any status bits that are set
163 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
164 mov 255, %l0
165 mov FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1
166
167LinkTrainingLoop2:
168 ldx [%g3], %l4 ! bit 8 is Link Up primary event
169 ldx [%g4], %l5 ! bits 48:44 are the LTSSM state
170 andcc %l1, %l4, %l4
171 bne After_Warm_Reset
172 nop
173
174 dec %l0
175 brnz %l0, LinkTrainingLoop2
176 nop
177 b test_failed
178 nop
179
180#else
181 setx RST_RESET_GEN, %g1, %g5 ! warm reset reg
182 mov RST_RESET_GEN__WMR_GEN, %g7 ! warm reset reg data
183 mov 25, %l0 ! loop timeout count
184
185 stx %g7, [%g5] ! Warm Reset
186 ldx [%g5], %g7
187
188Wait4WarmReset:
189 dec %l0
190 brnz %l0, Wait4WarmReset
191 nop
192 ba test_failed ! Warm reset didn't happen
193 nop
194#endif
195
196/************************************************************
197 Do a couple of PIOs and DMAs to verify that its working fine.
198 ************************************************************/
199After_Warm_Reset:
200nop ! $EV trig_pc_d(1, @VA(.MAIN.After_Warm_Reset)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR2, "64'h40", 1 )
201
202After_Warm_Reset2:
203nop ! $EV trig_pc_d(1, @VA(.MAIN.After_Warm_Reset2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR4, "64'h40", 1 )
204
205 ! Do PIOs to IO address space
206 ! load byte - all byte offsets within an octlet
207 setx IO_RD_ADDR, %g1, %g2
208 ldub [%g2 + 1*8 + 0], %l0
209 ldub [%g2 + 2*8 + 1], %l1
210 ldub [%g2 + 3*8 + 2], %l2
211 ldub [%g2 + 4*8 + 3], %l3
212 ldub [%g2 + 5*8 + 4], %l4
213 ldub [%g2 + 6*8 + 5], %l5
214 ldub [%g2 + 7*8 + 6], %l6
215 ldub [%g2 + 8*8 + 7], %l7
216
217
218test_passed:
219 EXIT_GOOD
220
221test_failed:
222 EXIT_BAD
223
224/************************************************************************
225 Test case data start
226************************************************************************/
227 .align 64
228test_entered:
229 .xword 0
230
231
232SECTION .PIODATA DATA_VA=IO_RD_ADDR
233attr_data {
234 Name = .PIODATA,
235 hypervisor,
236 compressimage
237}
238
239.data
240 .xword 0xdeadbeefdeadbeef
241
242 .xword 0x1101010101010101
243 .xword 0x0122010101010101
244 .xword 0x0101330101010101
245 .xword 0x0101014401010101
246 .xword 0x0101010155010101
247 .xword 0x0101010101660101
248 .xword 0x0101010101017701
249 .xword 0x0101010101010188
250
251 .xword 0x1122010101010101
252 .xword 0x0101334401010101
253 .xword 0x0101010155660101
254 .xword 0x0101010101017788
255
256 .xword 0x1122334401010101
257 .xword 0x0101010155667788
258
259 .xword 0xdeadbeefdeadbeef
260
261/************************************************************************/
262
263SECTION .DMADATA DATA_VA=DMA_DATA_ADDR
264attr_data {
265 Name = .DMADATA,
266 hypervisor,
267 compressimage
268}
269
270.data
271 init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004)
Full OpenSPARC design & verification tarball including full HDL.