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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / RegWrWrmrst.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: RegWrWrmrst.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39#define RESET_STAT_CHECK
40#define RESET_CHECK_REG
41
42#include "hboot.s"
43#include "peu_defines.h"
44#include "dmu_peu_regs.h"
45#include "rst_defines.h"
46
47/*
48Test case code start
49*/
50.text
51.global main
52
53main:
54 ta T_CHANGE_HPRIV
55 nop
56
57/************************************************************
58 Check if this is the first time thru here
59 ************************************************************/
60 setx test_entered, %g1, %g2
61 ldx [%g2], %g3
62 brnz %g3, After_Warm_Reset
63 nop
64
65! First time thru, Store a non-zero value there
66 dec %g3
67 stx %g3, [%g2]
68
69/************************************************************
70 Read each register information entry (addr, value), write
71 the reg, read back what got written and save it.
72 ************************************************************/
73write_por_regs:
74 setx RegisterData, %g1, %g2
75
76write_por_reg_loop:
77 ldx [%g2 + 0], %g3
78 ldx [%g2 + 8], %g4
79 brz %g3, do_WARM_RESET
80 nop
81 stx %g4, [%g3]
82 ldx [%g3], %g5
83 stx %g5, [%g2 + 24]
84 add %g2, 0x20, %g2
85 b write_por_reg_loop
86 nop
87
88/************************************************************
89 Now do a WARM RESET.
90 ************************************************************/
91do_WARM_RESET:
92#ifdef PCIE_USE_SSYS_RESET
93 setx RST_SSYS_RESET, %g1, %g5 ! subsystem reset reg
94 mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data
95 stx %g7, [%g5] ! Subsystem Reset
96
97 mov 255, %l0 ! loop timeout count
98
99Wait4SsysReset:
100 ldx [%g5], %l7 ! should clear when Subsystem Reset is done
101 brz %l7, After_Warm_Reset
102 nop
103 dec %l0
104 brnz %l0, Wait4SsysReset
105 nop
106 ba test_failed ! Subsystem reset should have completed
107 nop
108#else
109 setx RST_RESET_GEN, %g1, %g5 ! warm reset reg
110 mov RST_RESET_GEN__WMR_GEN, %g7 ! warm reset reg data
111 mov 25, %l0 ! loop timeout count
112
113 stx %g7, [%g5] ! Warm Reset
114 ldx [%g5], %g7
115
116Wait4WarmReset:
117 dec %l0
118 brnz %l0, Wait4WarmReset
119 nop
120 b test_failed
121 nop
122#endif
123
124/************************************************************
125 Read all the registers written above to verify that the values
126 written were retained.
127 I have to SAVE the value I read out above and do a comparison
128 here, otherwise the follow-me register stuff makes Riesling
129 think that whatever gets read back is always correct.
130 ************************************************************/
131After_Warm_Reset:
132 setx RegisterData, %g1, %g2
133
134read_por_reg_loop:
135 ldx [%g2 + 0], %g3
136 ldx [%g2 + 24], %g4
137 brz %g3, test_passed
138 nop
139
140 ldx [%g3], %g5 ! read por reg
141 xor %g4, %g5, %g6 ! compare to pre-reset value
142 brnz %g6, test_failed ! if different, fail
143 nop
144
145 add %g2, 0x20, %g2
146 b read_por_reg_loop
147 nop
148
149
150
151test_passed:
152 EXIT_GOOD
153
154test_failed:
155 EXIT_BAD
156
157 .align 64
158test_entered:
159 .xword 0 ! pass 1 / pass 2 indicator
160
161/********************************************************************
162 Register Data
163 1. Register address
164 2. Value to write
165 3. Mask for value read back
166 4. Value read back before Warm Reset
167 ********************************************************************/
168 .align 64
169RegisterData:
170 .xword FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR
171 .xword 0xffffffffffffffff
172 .xword 0xffffffffffffffff
173 .xword 0
174
175 .xword FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR
176 .xword 0xffffffffffffffff
177 .xword 0xffffffffffffffff
178 .xword 0
179
180 .xword FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR
181 .xword 0xffffffffffffffff
182 .xword 0xffffffffffffffff
183 .xword 0
184
185 .xword FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_ADDR
186 .xword 0xffffffffffffffff
187 .xword 0xffffffffffffffff
188 .xword 0
189
190 .xword FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_ADDR
191 .xword 0xffffffffffffffff
192 .xword 0xffffffffffffffff
193 .xword 0
194
195 .xword FIRE_DLC_MMU_CSR_A_LOG_ADDR
196 .xword ~FIRE_DLC_MMU_CSR_A_LOG_POR_VALUE
197 .xword 0xffffffffffffffff
198 .xword 0
199
200 .xword FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_ADDR
201 .xword 0xffffffffffffffff
202 .xword 0xffffffffffffffff
203 .xword 0
204
205 .xword FIRE_DLC_MMU_CSR_A_FLTA_ADDR
206 .xword 0xffffffffffffffff
207 .xword 0xffffffffffffffff
208 .xword 0
209
210 .xword FIRE_DLC_MMU_CSR_A_FLTS_ADDR
211 .xword 0xffffffffffffffff
212 .xword 0xffffffffffffffff
213 .xword 0
214
215 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x00)
216 .xword 0xffffffffffffffff
217 .xword 0xffffffffffffffff
218 .xword 0
219
220 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x08)
221 .xword 0xffffffffffffffff
222 .xword 0xffffffffffffffff
223 .xword 0
224
225 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x10)
226 .xword 0xffffffffffffffff
227 .xword 0xffffffffffffffff
228 .xword 0
229
230 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x18)
231 .xword 0xffffffffffffffff
232 .xword 0xffffffffffffffff
233 .xword 0
234
235 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x20)
236 .xword 0xffffffffffffffff
237 .xword 0xffffffffffffffff
238 .xword 0
239
240 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x28)
241 .xword 0xffffffffffffffff
242 .xword 0xffffffffffffffff
243 .xword 0
244
245 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x30)
246 .xword 0xffffffffffffffff
247 .xword 0xffffffffffffffff
248 .xword 0
249
250 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x38)
251 .xword 0xffffffffffffffff
252 .xword 0xffffffffffffffff
253 .xword 0
254
255 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x40)
256 .xword 0xffffffffffffffff
257 .xword 0xffffffffffffffff
258 .xword 0
259
260 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x48)
261 .xword 0xffffffffffffffff
262 .xword 0xffffffffffffffff
263 .xword 0
264
265 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x50)
266 .xword 0xffffffffffffffff
267 .xword 0xffffffffffffffff
268 .xword 0
269
270 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x58)
271 .xword 0xffffffffffffffff
272 .xword 0xffffffffffffffff
273 .xword 0
274
275 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x60)
276 .xword 0xffffffffffffffff
277 .xword 0xffffffffffffffff
278 .xword 0
279
280 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x68)
281 .xword 0xffffffffffffffff
282 .xword 0xffffffffffffffff
283 .xword 0
284
285 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x70)
286 .xword 0xffffffffffffffff
287 .xword 0xffffffffffffffff
288 .xword 0
289
290 .xword mpeval(FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR + 0x78)
291 .xword 0xffffffffffffffff
292 .xword 0xffffffffffffffff
293 .xword 0
294
295
296 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x00)
297 .xword 0xffffffffffffffff
298 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
299 .xword 0
300
301 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x08)
302 .xword 0xffffffffffffffff
303 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
304 .xword 0
305
306 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x10)
307 .xword 0xffffffffffffffff
308 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
309 .xword 0
310
311 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x18)
312 .xword 0xffffffffffffffff
313 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
314 .xword 0
315
316 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x20)
317 .xword 0xffffffffffffffff
318 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
319 .xword 0
320
321 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x28)
322 .xword 0xffffffffffffffff
323 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
324 .xword 0
325
326 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x30)
327 .xword 0xffffffffffffffff
328 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
329 .xword 0
330
331 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x38)
332 .xword 0xffffffffffffffff
333 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
334 .xword 0
335
336 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x40)
337 .xword 0xffffffffffffffff
338 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
339 .xword 0
340
341 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x48)
342 .xword 0xffffffffffffffff
343 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
344 .xword 0
345
346 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x50)
347 .xword 0xffffffffffffffff
348 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
349 .xword 0
350
351 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x58)
352 .xword 0xffffffffffffffff
353 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
354 .xword 0
355
356 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x60)
357 .xword 0xffffffffffffffff
358 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
359 .xword 0
360
361 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x68)
362 .xword 0xffffffffffffffff
363 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
364 .xword 0
365
366 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x70)
367 .xword 0xffffffffffffffff
368 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
369 .xword 0
370
371 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x78)
372 .xword 0xffffffffffffffff
373 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
374 .xword 0
375
376 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x80)
377 .xword 0xffffffffffffffff
378 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
379 .xword 0
380
381 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x88)
382 .xword 0xffffffffffffffff
383 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
384 .xword 0
385
386 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x90)
387 .xword 0xffffffffffffffff
388 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
389 .xword 0
390
391 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0x98)
392 .xword 0xffffffffffffffff
393 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
394 .xword 0
395
396 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xa0)
397 .xword 0xffffffffffffffff
398 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
399 .xword 0
400
401 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xa8)
402 .xword 0xffffffffffffffff
403 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
404 .xword 0
405
406 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xb0)
407 .xword 0xffffffffffffffff
408 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
409 .xword 0
410
411 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xb8)
412 .xword 0xffffffffffffffff
413 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
414 .xword 0
415
416 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xc0)
417 .xword 0xffffffffffffffff
418 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
419 .xword 0
420
421 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xc8)
422 .xword 0xffffffffffffffff
423 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
424 .xword 0
425
426 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xd0)
427 .xword 0xffffffffffffffff
428 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
429 .xword 0
430
431 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xd8)
432 .xword 0xffffffffffffffff
433 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
434 .xword 0
435
436 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xe0)
437 .xword 0xffffffffffffffff
438 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
439 .xword 0
440
441 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xe8)
442 .xword 0xffffffffffffffff
443 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
444 .xword 0
445
446 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xf0)
447 .xword 0xffffffffffffffff
448 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
449 .xword 0
450
451 .xword mpeval(FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR + 0xf8)
452 .xword 0xffffffffffffffff
453 .xword 0xcfffffffffffffff ! bits 61-62 are parity gen'd by hw
454 .xword 0
455
456
457 .xword FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR
458 .xword ~FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_POR_VALUE
459 .xword 0xffffffffffffffff
460 .xword 0
461
462 .xword FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR
463 .xword 0xffffffffffffffff
464 .xword 0xffffffffffffffff
465 .xword 0
466
467 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR
468 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_POR_VALUE
469 .xword 0xffffffffffffffff
470 .xword 0
471
472 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_ADDR
473 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_POR_VALUE
474 .xword 0xffffffffffffffff
475 .xword 0
476
477 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR
478 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_POR_VALUE
479 .xword 0xffffffffffffffff
480 .xword 0
481
482 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_ADDR
483 .xword 0xffffffffffffffff
484 .xword 0xffffffffffffffff
485 .xword 0
486
487 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_ADDR
488 .xword 0xffffffffffffffff
489 .xword 0xffffffffffffffff
490 .xword 0
491
492 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_ADDR
493 .xword 0xffffffffffffffff
494 .xword 0xffffffffffffffff
495 .xword 0
496
497 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_ADDR
498 .xword 0xffffffffffffffff
499 .xword 0xffffffffffffffff
500 .xword 0
501
502 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_ADDR
503 .xword 0xffffffffffffffff
504 .xword 0xffffffffffffffff
505 .xword 0
506
507 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_ADDR
508 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_POR_VALUE
509 .xword 0xffffffffffffffff
510 .xword 0
511
512 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_ADDR
513 .xword 0xffffffffffffffff
514 .xword 0xffffffffffffffff
515 .xword 0
516
517 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_ADDR
518 .xword 0xffffffffffffffff
519 .xword 0xffffffffffffffff
520 .xword 0
521
522 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_ADDR
523 .xword 0xffffffffffffffff
524 .xword 0xffffffffffffffff
525 .xword 0
526
527 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_ADDR
528 .xword 0xffffffffffffffff
529 .xword 0xffffffffffffffff
530 .xword 0
531
532 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_ADDR
533 .xword 0xffffffffffffffff
534 .xword 0xffffffffffffffff
535 .xword 0
536
537 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_ADDR
538 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_POR_VALUE
539 .xword 0xffffffffffffffff
540 .xword 0
541
542 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_ADDR
543 .xword 0xffffffffffffffff
544 .xword 0xffffffffffffffff
545 .xword 0
546
547 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_ADDR
548 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_POR_VALUE
549 .xword 0xffffffffffffffff
550 .xword 0
551
552 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_ADDR
553 .xword 0xffffffffffffffff
554 .xword 0xffffffffffffffff
555 .xword 0
556
557 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_ADDR
558 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_POR_VALUE
559 .xword 0xffffffffffffffff
560 .xword 0
561
562 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR + 0x00)
563 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE
564 .xword 0xffffffffffffffff
565 .xword 0
566
567 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR + 0x08)
568 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE
569 .xword 0xffffffffffffffff
570 .xword 0
571
572 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR + 0x10)
573 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE
574 .xword 0xffffffffffffffff
575 .xword 0
576
577 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR + 0x18)
578 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE
579 .xword 0xffffffffffffffff
580 .xword 0
581
582 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR + 0x20)
583 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE
584 .xword 0xffffffffffffffff
585 .xword 0
586
587 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR + 0x28)
588 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE
589 .xword 0xffffffffffffffff
590 .xword 0
591
592 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR + 0x30)
593 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE
594 .xword 0xffffffffffffffff
595 .xword 0
596
597 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR + 0x38)
598 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE
599 .xword 0xffffffffffffffff
600 .xword 0
601
602 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR + 0x00)
603 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE
604 .xword 0xffffffffffffffff
605 .xword 0
606
607 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR + 0x08)
608 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE
609 .xword 0xffffffffffffffff
610 .xword 0
611
612 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR + 0x10)
613 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE
614 .xword 0xffffffffffffffff
615 .xword 0
616
617 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR + 0x18)
618 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE
619 .xword 0xffffffffffffffff
620 .xword 0
621
622 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR + 0x20)
623 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE
624 .xword 0xffffffffffffffff
625 .xword 0
626
627 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR + 0x28)
628 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE
629 .xword 0xffffffffffffffff
630 .xword 0
631
632 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR + 0x30)
633 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE
634 .xword 0xffffffffffffffff
635 .xword 0
636
637 .xword mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR + 0x38)
638 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE
639 .xword 0xffffffffffffffff
640 .xword 0
641
642 .xword FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_ADDR
643 .xword ~FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_POR_VALUE
644 .xword 0xffffffffffffffff
645 .xword 0
646
647 .xword 0 ! the end
648 .xword 0
649 .xword 0
650 .xword 0
651
652 .xword 0 ! the end
653 .xword 0
654 .xword 0
655 .xword 0
656
Full OpenSPARC design & verification tarball including full HDL.