[OpenSPARC-T2-DV] / verif / diag / assembly / spc / spc_tlu_rml_asr.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: spc_tlu_rml_asr.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define PORTABLE_CORE
		
!#include "bw_default_defines.h"
#include "defines.h"
#include "old_boot.s"

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:		/* test begin */

	ta	T_RD_THID
	mov	%o1, %l7
	umul	%l7, 256, %l7


	!# Initialize registers ..

	!# Global registers
	set	0xB,	%g1
	set	0x5,	%g2
	set	0x7,	%g3
	set	0xE,	%g4
	set	0x7,	%g5
	set	0xB,	%g6
	set	0x3,	%g7
	!# Input registers
	set	-0x4,	%i0
	set	-0xC,	%i1
	set	-0x8,	%i2
	set	-0xF,	%i3
	set	-0x1,	%i4
	set	-0xB,	%i5
	set	-0x4,	%i6
	set	-0x0,	%i7
	!# Local registers
	set	0x08538AD0,	%l0
	set	0x07398F35,	%l1
	set	0x4B289E70,	%l2
	set	0x0004A8EF,	%l3
	set	0x7750ABA7,	%l4
	set	0x0E460AC4,	%l5
	set	0x7AA8D017,	%l6
	!# Output registers
	set	0x170F,	%o0
	set	0x14E1,	%o1
	set	0x1B1D,	%o2
	set	-0x0859,	%o3
	set	0x0DF7,	%o4
	set	-0x112E,	%o5
	set	0x1988,	%o6
	set	-0x0D3D,	%o7

	!# Execute some ALU ops ..

	!# set up operands for testing asi instructions    
    ta  T_RD_THID
    mov %o1, %l0
    srl %l0, 0x4, %l1
	
	!# test PIL
	wrpr %g0, %l0, %pil
	rdpr %pil, %l7
	cmp %l0, %l7
	bne bad
 	wrpr %l0, 0x8, %pil
 	rdpr %pil, %l7
 	xor %l0, 0x8, %l6
 	cmp %l6, %l7
 	bne bad
	
	!# test TICK
 	wrpr %l0, 0x1, %tick
	!# in reality, can't be the same value - e.g., some clocks have passed
	!# but simics thinks they are the same, so can't test yet
! 	rdpr %tick, %l1
!	cmp %l0, %l1
!	beq bad
	or %g0, 0xff, %l2
	wrpr %l2, %g0, %tick
! 	rdpr %tick, %l1
! 	cmp %l2, %l1
! 	beq bad

	!# test TICK using RD
 	wrpr %l0, 0x1, %tick
	!# in reality, can't be the same value - e.g., some clocks have passed
	!# but simics thinks they are the same, so can't test yet
! 	rd %tick, %l1
!	cmp %l0, %l1
!	beq bad
	or %g0, 0xff, %l2
	wrpr %l2, %g0, %tick
! 	rd %tick, %l1
! 	cmp %l2, %l1
! 	beq bad
	
	!# test STICK
 	wr %l0, 0x1, %sys_tick
	!# in reality, can't be the same value - e.g., some clocks have passed
	!# but simics thinks they are the same, so can't test yet
! 	rd %sys_tick, %l1
!	cmp %l0, %l1
!	beq bad
	or %g0, 0xff, %l2
	wr %l2, %g0, %sys_tick
! 	rd %sys_tick, %l1
! 	cmp %l2, %l1
! 	beq bad

	!# test TL
 	wrpr %g0, 0x1,%tl
 	rdpr %tl, %l2
 	cmp %l2, 0x1	
 	bne bad
	or %g0, 0x5, %l2
	wrpr %l2, %g0, %tl
 	rdpr %tl, %l7
 	cmp %l7, 0x5
 	bne bad

	!# test CWP
	mov %l0, %g2 ! save tid in g2
	wrpr %l0, 0x0, %cwp
	rdpr %cwp, %l1
	cmp %g2, %l1
	bne bad
	wrpr %g2, %g0, %cwp
	rdpr %cwp, %l1
	cmp %g2, %l1
	bne bad
	
	!# test CLEANWIN
	wrpr %l0, 0x0, %cleanwin
	rdpr %cleanwin, %l1
	cmp %l0, %l1
	bne bad
	wrpr %l0, %g0, %cleanwin
	rdpr %cleanwin, %l1
	cmp %l0, %l1
	bne bad
	
	!# test CANSAVE
	wrpr %l0, 0x0, %cansave
	rdpr %cansave, %l1
	cmp %l0, %l1
	bne bad
	wrpr %l0, %g0, %cansave
	rdpr %cansave, %l1
	cmp %l0, %l1
	bne bad
	
	!# test CANRESTORE
	wrpr %l0, 0x0, %canrestore
	rdpr %canrestore, %l1
	cmp %l0, %l1
	bne bad
	wrpr %l0, %g0, %canrestore
	rdpr %canrestore, %l1
	cmp %l0, %l1
	bne bad
	
	!# test OTHERWIN
	wrpr %l0, 0x0, %otherwin
	rdpr %otherwin, %l1
	cmp %l0, %l1
	bne bad
	wrpr %l0, %g0, %otherwin
	rdpr %otherwin, %l1
	cmp %l0, %l1
	bne bad
	
	!# test WSTATE
	wrpr %l0, 0x0, %wstate
	rdpr %wstate, %l1
	cmp %l0, %l1
	bne bad
	wrpr %l0, %g0, %wstate
	rdpr %wstate, %l1
	cmp %l0, %l1
	bne bad
	
	!# now reset TL to 1

	wrpr %g0, 0x1, %tl
	rd %pc, %l1
	add %l1, 0x4, %l2

	!# test tpc, tnpc
	wrpr %l1, 0x0, %tpc
	wrpr %l2, 0x0, %tnpc
	rdpr %tpc, %l3
	cmp %l3, %l1
	bne bad
	rdpr %tnpc, %l4
	cmp %l2, %l4
	bne bad

	rd %pc, %l1
	add %l1, 0x4, %l2
	wrpr %l1, %g0, %tpc
	wrpr %l2, %g0, %tnpc
	rdpr %tpc, %l3
	cmp %l3, %l1
	bne bad
	rdpr %tnpc, %l4
	cmp %l2, %l4
	bne bad

	!# test TT
	wrpr %l0, 0x0, %tt
	rdpr %tt, %l3
	cmp %l0, %l3
	bne bad
	wrpr %l0, %g0, %tt
	rdpr %tt, %l3
	cmp %l0, %l3
	bne bad
	
	!# test tstate == {ccr, asi, pstate, cwp}
	setx 0xf0feedf00d, %g3, %l6
	wrpr %l6, 0x0, %tstate
	rdpr %tstate, %l2
	!# use mask, which is AND of defined TSTATE bits accounting for 0 <= CWP <= 7, MM=0, RED=0, PEF=1
	setx 0xffff031f17, %g3, %l1
	and %l6, %l1, %l4
	cmp %l2, %l4
	bne bad
	wrpr %l6, %g0, %tstate
	rdpr %tstate, %l2
	cmp %l2, %l4
	bne bad

	!# check TBA
	rdpr %tba, %l7
	srl %l0, 0xe, %l2
	wrpr %l2, 0xf, %tba
	rdpr %tba, %l1
	cmp %l1, %l2
	bne bad
	wrpr %l2, %g0, %tba
	rdpr %tba, %l1
	cmp %l1, %l2
	bne bad
	wrpr %l7, %g0, %tba

	!# check GL
	xor %l0, 0x3, %l3
	and %l3, 0x3, %l3
	wrpr %l0, 0xf, %gl
	rdpr %gl, %l2
	cmp %l3, %l2
	bne bad
	wrpr %l0, %g0, %gl
	rdpr %gl, %l2
	cmp %l0, %l2
	bne bad

	!# check the wrhpr/rdhpr ops...
	!# start with hpstate
	or %l0, 0x4, %l2 !stay in hpriv state, not critical if tlz is set/reset, keep ibe and red off
	wrhpr %l2, 0x0, %hpstate
	rdhpr %hpstate, %l3
	cmp %l3, %l2
	bne bad 
	wrhpr %l2, %g0, %hpstate
	rdhpr %hpstate, %l3
	cmp %l3, %l2
	bne bad 

	!# HTSTATE
	wrhpr %l2, 0x0, %htstate
	rdhpr %htstate, %l3
	cmp %l3, %l2
	bne bad 
	wrhpr %l2, %g0, %htstate
	rdhpr %htstate, %l3
	cmp %l3, %l2
	bne bad 

	!# HINTP (only bit 0 is defined)
	and %l0, 0x1, %l2
	wrhpr %l2, 0x0, %hintp
	rdhpr %hintp, %l3
	cmp %l3, %l2
	bne bad 
	wrhpr %l2, %g0, %hintp
	rdhpr %hintp, %l3
	cmp %l3, %l2
	bne bad 

	!# HTBA
	rdhpr %htba, %l7
	srl %l0, 0xe, %l2
	wrhpr %l2, 0xf, %htba
	rdhpr %htba, %l1
	cmp %l1, %l2
	bne bad
	wrhpr %l2, %g0, %htba
	rdhpr %htba, %l1
	cmp %l1, %l2
	bne bad
	wrhpr %l7, %g0, %htba

	!# HVER (read-only)
	! expect N1 values for now
	setx 0x003e002401006607, %o2, %l4
!	rdhpr %ver, %l1
!	cmp %l1, %l4
!	bne bad

	!# Make sure INT_DIS bits are set...
	!# TICK_CMPR
	setx 0x1000000000000000, %g0, %l4
	srl %l0, 0xe, %l2
	or %l2, %l4, %l2
	xor %l2, 0xf, %l3
	wr %l2, 0xf, %tick_cmpr
	rd %tick_cmpr, %l1
	cmp %l1, %l3
	bne bad
	wr %l2, %g0, %tick_cmpr
	rd %tick_cmpr, %l1
	cmp %l1, %l2
	bne bad
	
	!# STICK_CMPR
	setx 0x1000000000000000, %g0, %l4
	srl %l0, 0xe, %l2
	or %l2, %l4, %l2
	xor %l2, 0xf, %l3
	wr %l2, 0xf, %sys_tick_cmpr
	rd %sys_tick_cmpr, %l1
	cmp %l1, %l3
	bne bad
	wr %l2, %g0, %sys_tick_cmpr
	rd %sys_tick_cmpr, %l1
	cmp %l1, %l2
	bne bad
		
	!# HSTICK_COMPARE
	setx 0x1000000000000000, %g0, %l4
	srl %l0, 0xe, %l2
	or %l2, %l4, %l2
	xor %l2, 0xf, %l3
	wrhpr %l2, 0xf, %hsys_tick_cmpr
	rdhpr %hsys_tick_cmpr, %l1
	cmp %l1, %l3
	bne bad
	wrhpr %l2, %g0, %hsys_tick_cmpr
	rdhpr %hsys_tick_cmpr, %l1
	cmp %l1, %l2
	bne bad
		
	!# SOFTINT
	setx 0x1ffff, %g3, %l2 ! bits 16..0 are defined
	xor %l2, %l0, %l2
	wr %l2, 0x0, %softint
	rd %softint, %l3
	cmp %l2, %l3
	bne bad	
	wr %l2, %g0, %softint
	rd %softint, %l3
	cmp %l2, %l3
	bne bad	

	!# SET_SOFTINT
	! clear all bits first
	setx 0x1ffff, %g3, %l2
	wr %l3, 0x0, %clear_softint
	rd %softint, %l3
	cmp %l3, %g0
	bne bad
	setx 0x1f0f0, %g3, %l2 ! bits 16..0 are defined
	xor %l2, %l0, %l2
	wr %l2, 0x0, %set_softint
	rd %softint, %l3
	cmp %l2, %l3
	bne bad
	
	!# CLEAR_SOFTINT
	setx 0x1ffff, %g3, %l2	
	wr %l2, %g0, %clear_softint
	rd %softint, %l3
	cmp %l3, %g0
	bne bad
	setx 0x10f0f, %g3, %l2 ! bits 16..0 are defined
	xor %l2, %l0, %l2
	wr %l2, %g0, %set_softint
	rd %softint, %l3
	cmp %l2, %l3
	bne bad
				
	nop
	
	EXIT_GOOD	/* test finish  */


bad:	
	EXIT_BAD
		
/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
.word 0x3C2D3A79
.word 0xA4FF68F0
.word 0x13C701A5
.word 0xC99B6312
.word 0xA4F4C560
.word 0x5BABF289
.word 0xFCE126DE
.word 0x192FB03E
.word 0x6E8EE4BD
.word 0x2B2C2E3E
.word 0xB6DED02A
.word 0xC01083B1
.word 0x44988A1F
.word 0x9DE7EB5A
.word 0xB74AA760
.word 0xE4BEBA23
.word 0x91772362
.word 0x0EFD27D4
.word 0x0A6D28DF
.word 0x1E6E6B20
.word 0x37CF0203
.word 0x08A35333
.word 0x37D2B902
.word 0x40B11BA1
.word 0x753FB53E
.word 0x915CE10C
.word 0xEA67753F
.word 0xAF5B00C5
.word 0xBDB94A52
.word 0x1D0FD9E3
.word 0x9EA12949
.word 0xF6D465AC
.word 0x3D702202
.word 0x3142FEAE
.word 0x1C59D52C
.word 0xCFA86D05
.word 0xE2CCEFBC
.word 0xB384E260
.word 0x9479CC2D
.word 0x9F49FC0A
.word 0xFA0AFE12
.word 0x9BADD844
.word 0x7ABF68B6
.word 0xD79B2787
.word 0x2DABAA5B
.word 0x2A7D2369
.word 0xEBC7D953
.word 0xC91A563E
.word 0x21899566
.word 0x5545E80A
.word 0xD551D8ED
.word 0xECBD2D1B
.word 0x5F55E84B
.word 0x51D80E1A
.word 0x8D1CE3BC
.word 0xD126CC9F
.word 0x3939976F
.word 0xD0E0B2D5
.word 0xD7524BD8
.word 0x86F9D052
.word 0x005953F7
.word 0xB834B88A
.word 0x0B2A90E3
.word 0x0F749E26
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: spc_tlu_rml_asr.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define PORTABLE_CORE
	39
	40	!#include "bw_default_defines.h"
	41	#include "defines.h"
	42	#include "old_boot.s"
	43
	44	/************************************************************************
	45	Test case code start
	46	************************************************************************/
	47
	48	.text
	49	.global main
	50
	51	main: /* test begin */
	52
	53	ta T_RD_THID
	54	mov %o1, %l7
	55	umul %l7, 256, %l7
	56
	57
	58	!# Initialize registers ..
	59
	60	!# Global registers
	61	set 0xB, %g1
	62	set 0x5, %g2
	63	set 0x7, %g3
	64	set 0xE, %g4
65	set 0x7, %g5
66	set 0xB, %g6
67	set 0x3, %g7
68	!# Input registers
69	set -0x4, %i0
70	set -0xC, %i1
71	set -0x8, %i2
72	set -0xF, %i3
73	set -0x1, %i4
74	set -0xB, %i5
75	set -0x4, %i6
76	set -0x0, %i7
77	!# Local registers
78	set 0x08538AD0, %l0
79	set 0x07398F35, %l1
80	set 0x4B289E70, %l2
81	set 0x0004A8EF, %l3
82	set 0x7750ABA7, %l4
83	set 0x0E460AC4, %l5
84	set 0x7AA8D017, %l6
85	!# Output registers
86	set 0x170F, %o0
87	set 0x14E1, %o1
88	set 0x1B1D, %o2
89	set -0x0859, %o3
90	set 0x0DF7, %o4
91	set -0x112E, %o5
92	set 0x1988, %o6
93	set -0x0D3D, %o7
94
95	!# Execute some ALU ops ..
96
97	!# set up operands for testing asi instructions
98	ta T_RD_THID
99	mov %o1, %l0
100	srl %l0, 0x4, %l1
101
102	!# test PIL
103	wrpr %g0, %l0, %pil
104	rdpr %pil, %l7
105	cmp %l0, %l7
106	bne bad
107	wrpr %l0, 0x8, %pil
108	rdpr %pil, %l7
109	xor %l0, 0x8, %l6
110	cmp %l6, %l7
111	bne bad
112
113	!# test TICK
114	wrpr %l0, 0x1, %tick
115	!# in reality, can't be the same value - e.g., some clocks have passed
116	!# but simics thinks they are the same, so can't test yet
117	! rdpr %tick, %l1
118	! cmp %l0, %l1
119	! beq bad
120	or %g0, 0xff, %l2
121	wrpr %l2, %g0, %tick
122	! rdpr %tick, %l1
123	! cmp %l2, %l1
124	! beq bad
125
126	!# test TICK using RD
127	wrpr %l0, 0x1, %tick
128	!# in reality, can't be the same value - e.g., some clocks have passed
129	!# but simics thinks they are the same, so can't test yet
130	! rd %tick, %l1
131	! cmp %l0, %l1
132	! beq bad
133	or %g0, 0xff, %l2
134	wrpr %l2, %g0, %tick
135	! rd %tick, %l1
136	! cmp %l2, %l1
137	! beq bad
138
139	!# test STICK
140	wr %l0, 0x1, %sys_tick
141	!# in reality, can't be the same value - e.g., some clocks have passed
142	!# but simics thinks they are the same, so can't test yet
143	! rd %sys_tick, %l1
144	! cmp %l0, %l1
145	! beq bad
146	or %g0, 0xff, %l2
147	wr %l2, %g0, %sys_tick
148	! rd %sys_tick, %l1
149	! cmp %l2, %l1
150	! beq bad
151
152	!# test TL
153	wrpr %g0, 0x1,%tl
154	rdpr %tl, %l2
155	cmp %l2, 0x1
156	bne bad
157	or %g0, 0x5, %l2
158	wrpr %l2, %g0, %tl
159	rdpr %tl, %l7
160	cmp %l7, 0x5
161	bne bad
162
163	!# test CWP
164	mov %l0, %g2 ! save tid in g2
165	wrpr %l0, 0x0, %cwp
166	rdpr %cwp, %l1
167	cmp %g2, %l1
168	bne bad
169	wrpr %g2, %g0, %cwp
170	rdpr %cwp, %l1
171	cmp %g2, %l1
172	bne bad
173
174	!# test CLEANWIN
175	wrpr %l0, 0x0, %cleanwin
176	rdpr %cleanwin, %l1
177	cmp %l0, %l1
178	bne bad
179	wrpr %l0, %g0, %cleanwin
180	rdpr %cleanwin, %l1
181	cmp %l0, %l1
182	bne bad
183
184	!# test CANSAVE
185	wrpr %l0, 0x0, %cansave
186	rdpr %cansave, %l1
187	cmp %l0, %l1
188	bne bad
189	wrpr %l0, %g0, %cansave
190	rdpr %cansave, %l1
191	cmp %l0, %l1
192	bne bad
193
194	!# test CANRESTORE
195	wrpr %l0, 0x0, %canrestore
196	rdpr %canrestore, %l1
197	cmp %l0, %l1
198	bne bad
199	wrpr %l0, %g0, %canrestore
200	rdpr %canrestore, %l1
201	cmp %l0, %l1
202	bne bad
203
204	!# test OTHERWIN
205	wrpr %l0, 0x0, %otherwin
206	rdpr %otherwin, %l1
207	cmp %l0, %l1
208	bne bad
209	wrpr %l0, %g0, %otherwin
210	rdpr %otherwin, %l1
211	cmp %l0, %l1
212	bne bad
213
214	!# test WSTATE
215	wrpr %l0, 0x0, %wstate
216	rdpr %wstate, %l1
217	cmp %l0, %l1
218	bne bad
219	wrpr %l0, %g0, %wstate
220	rdpr %wstate, %l1
221	cmp %l0, %l1
222	bne bad
223
224	!# now reset TL to 1
225
226	wrpr %g0, 0x1, %tl
227	rd %pc, %l1
228	add %l1, 0x4, %l2
229
230	!# test tpc, tnpc
231	wrpr %l1, 0x0, %tpc
232	wrpr %l2, 0x0, %tnpc
233	rdpr %tpc, %l3
234	cmp %l3, %l1
235	bne bad
236	rdpr %tnpc, %l4
237	cmp %l2, %l4
238	bne bad
239
240	rd %pc, %l1
241	add %l1, 0x4, %l2
242	wrpr %l1, %g0, %tpc
243	wrpr %l2, %g0, %tnpc
244	rdpr %tpc, %l3
245	cmp %l3, %l1
246	bne bad
247	rdpr %tnpc, %l4
248	cmp %l2, %l4
249	bne bad
250
251	!# test TT
252	wrpr %l0, 0x0, %tt
253	rdpr %tt, %l3
254	cmp %l0, %l3
255	bne bad
256	wrpr %l0, %g0, %tt
257	rdpr %tt, %l3
258	cmp %l0, %l3
259	bne bad
260
261	!# test tstate == {ccr, asi, pstate, cwp}
262	setx 0xf0feedf00d, %g3, %l6
263	wrpr %l6, 0x0, %tstate
264	rdpr %tstate, %l2
265	!# use mask, which is AND of defined TSTATE bits accounting for 0 <= CWP <= 7, MM=0, RED=0, PEF=1
266	setx 0xffff031f17, %g3, %l1
267	and %l6, %l1, %l4
268	cmp %l2, %l4
269	bne bad
270	wrpr %l6, %g0, %tstate
271	rdpr %tstate, %l2
272	cmp %l2, %l4
273	bne bad
274
275	!# check TBA
276	rdpr %tba, %l7
277	srl %l0, 0xe, %l2
278	wrpr %l2, 0xf, %tba
279	rdpr %tba, %l1
280	cmp %l1, %l2
281	bne bad
282	wrpr %l2, %g0, %tba
283	rdpr %tba, %l1
284	cmp %l1, %l2
285	bne bad
286	wrpr %l7, %g0, %tba
287
288	!# check GL
289	xor %l0, 0x3, %l3
290	and %l3, 0x3, %l3
291	wrpr %l0, 0xf, %gl
292	rdpr %gl, %l2
293	cmp %l3, %l2
294	bne bad
295	wrpr %l0, %g0, %gl
296	rdpr %gl, %l2
297	cmp %l0, %l2
298	bne bad
299
300	!# check the wrhpr/rdhpr ops...
301	!# start with hpstate
302	or %l0, 0x4, %l2 !stay in hpriv state, not critical if tlz is set/reset, keep ibe and red off
303	wrhpr %l2, 0x0, %hpstate
304	rdhpr %hpstate, %l3
305	cmp %l3, %l2
306	bne bad
307	wrhpr %l2, %g0, %hpstate
308	rdhpr %hpstate, %l3
309	cmp %l3, %l2
310	bne bad
311
312	!# HTSTATE
313	wrhpr %l2, 0x0, %htstate
314	rdhpr %htstate, %l3
315	cmp %l3, %l2
316	bne bad
317	wrhpr %l2, %g0, %htstate
318	rdhpr %htstate, %l3
319	cmp %l3, %l2
320	bne bad
321
322	!# HINTP (only bit 0 is defined)
323	and %l0, 0x1, %l2
324	wrhpr %l2, 0x0, %hintp
325	rdhpr %hintp, %l3
326	cmp %l3, %l2
327	bne bad
328	wrhpr %l2, %g0, %hintp
329	rdhpr %hintp, %l3
330	cmp %l3, %l2
331	bne bad
332
333	!# HTBA
334	rdhpr %htba, %l7
335	srl %l0, 0xe, %l2
336	wrhpr %l2, 0xf, %htba
337	rdhpr %htba, %l1
338	cmp %l1, %l2
339	bne bad
340	wrhpr %l2, %g0, %htba
341	rdhpr %htba, %l1
342	cmp %l1, %l2
343	bne bad
344	wrhpr %l7, %g0, %htba
345
346	!# HVER (read-only)
347	! expect N1 values for now
348	setx 0x003e002401006607, %o2, %l4
349	! rdhpr %ver, %l1
350	! cmp %l1, %l4
351	! bne bad
352
353	!# Make sure INT_DIS bits are set...
354	!# TICK_CMPR
355	setx 0x1000000000000000, %g0, %l4
356	srl %l0, 0xe, %l2
357	or %l2, %l4, %l2
358	xor %l2, 0xf, %l3
359	wr %l2, 0xf, %tick_cmpr
360	rd %tick_cmpr, %l1
361	cmp %l1, %l3
362	bne bad
363	wr %l2, %g0, %tick_cmpr
364	rd %tick_cmpr, %l1
365	cmp %l1, %l2
366	bne bad
367
368	!# STICK_CMPR
369	setx 0x1000000000000000, %g0, %l4
370	srl %l0, 0xe, %l2
371	or %l2, %l4, %l2
372	xor %l2, 0xf, %l3
373	wr %l2, 0xf, %sys_tick_cmpr
374	rd %sys_tick_cmpr, %l1
375	cmp %l1, %l3
376	bne bad
377	wr %l2, %g0, %sys_tick_cmpr
378	rd %sys_tick_cmpr, %l1
379	cmp %l1, %l2
380	bne bad
381
382	!# HSTICK_COMPARE
383	setx 0x1000000000000000, %g0, %l4
384	srl %l0, 0xe, %l2
385	or %l2, %l4, %l2
386	xor %l2, 0xf, %l3
387	wrhpr %l2, 0xf, %hsys_tick_cmpr
388	rdhpr %hsys_tick_cmpr, %l1
389	cmp %l1, %l3
390	bne bad
391	wrhpr %l2, %g0, %hsys_tick_cmpr
392	rdhpr %hsys_tick_cmpr, %l1
393	cmp %l1, %l2
394	bne bad
395
396	!# SOFTINT
397	setx 0x1ffff, %g3, %l2 ! bits 16..0 are defined
398	xor %l2, %l0, %l2
399	wr %l2, 0x0, %softint
400	rd %softint, %l3
401	cmp %l2, %l3
402	bne bad
403	wr %l2, %g0, %softint
404	rd %softint, %l3
405	cmp %l2, %l3
406	bne bad
407
408	!# SET_SOFTINT
409	! clear all bits first
410	setx 0x1ffff, %g3, %l2
411	wr %l3, 0x0, %clear_softint
412	rd %softint, %l3
413	cmp %l3, %g0
414	bne bad
415	setx 0x1f0f0, %g3, %l2 ! bits 16..0 are defined
416	xor %l2, %l0, %l2
417	wr %l2, 0x0, %set_softint
418	rd %softint, %l3
419	cmp %l2, %l3
420	bne bad
421
422	!# CLEAR_SOFTINT
423	setx 0x1ffff, %g3, %l2
424	wr %l2, %g0, %clear_softint
425	rd %softint, %l3
426	cmp %l3, %g0
427	bne bad
428	setx 0x10f0f, %g3, %l2 ! bits 16..0 are defined
429	xor %l2, %l0, %l2
430	wr %l2, %g0, %set_softint
431	rd %softint, %l3
432	cmp %l2, %l3
433	bne bad
434
435	nop
436
437	EXIT_GOOD /* test finish */
438
439
440	bad:
441	EXIT_BAD
442
443	/************************************************************************
444	Test case data start
445	************************************************************************/
446	.data
447	user_data_start:
448	.word 0x3C2D3A79
449	.word 0xA4FF68F0
450	.word 0x13C701A5
451	.word 0xC99B6312
452	.word 0xA4F4C560
453	.word 0x5BABF289
454	.word 0xFCE126DE
455	.word 0x192FB03E
456	.word 0x6E8EE4BD
457	.word 0x2B2C2E3E
458	.word 0xB6DED02A
459	.word 0xC01083B1
460	.word 0x44988A1F
461	.word 0x9DE7EB5A
462	.word 0xB74AA760
463	.word 0xE4BEBA23
464	.word 0x91772362
465	.word 0x0EFD27D4
466	.word 0x0A6D28DF
467	.word 0x1E6E6B20
468	.word 0x37CF0203
469	.word 0x08A35333
470	.word 0x37D2B902
471	.word 0x40B11BA1
472	.word 0x753FB53E
473	.word 0x915CE10C
474	.word 0xEA67753F
475	.word 0xAF5B00C5
476	.word 0xBDB94A52
477	.word 0x1D0FD9E3
478	.word 0x9EA12949
479	.word 0xF6D465AC
480	.word 0x3D702202
481	.word 0x3142FEAE
482	.word 0x1C59D52C
483	.word 0xCFA86D05
484	.word 0xE2CCEFBC
485	.word 0xB384E260
486	.word 0x9479CC2D
487	.word 0x9F49FC0A
488	.word 0xFA0AFE12
489	.word 0x9BADD844
490	.word 0x7ABF68B6
491	.word 0xD79B2787
492	.word 0x2DABAA5B
493	.word 0x2A7D2369
494	.word 0xEBC7D953
495	.word 0xC91A563E
496	.word 0x21899566
497	.word 0x5545E80A
498	.word 0xD551D8ED
499	.word 0xECBD2D1B
500	.word 0x5F55E84B
501	.word 0x51D80E1A
502	.word 0x8D1CE3BC
503	.word 0xD126CC9F
504	.word 0x3939976F
505	.word 0xD0E0B2D5
506	.word 0xD7524BD8
507	.word 0x86F9D052
508	.word 0x005953F7
509	.word 0xB834B88A
510	.word 0x0B2A90E3
511	.word 0x0F749E26
512	.end