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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / fc / fc_ecc_err.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_ecc_err.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<sys(fc_all)>
36<ecc_err_adv_mcu name=ecc_err_adv_mcu>
37
38<runargs -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -vcs_run_args=+l2cpx_mon_off>
39<runargs -vcs_run_args=+debug -vcs_run_args=+ccxPktPrint=spc -vcs_run_args=+info -config_cpp_args=-DIDT_AMB>
40<runargs -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+nb_crc_mon_disable>
41<runargs -vcs_run_args=+show_delta -nosas>
42<runargs -vcs_run_args=+bad_trap=00000000a0 -vcs_run_args=+bad_trap=0000000040 -vcs_run_args=+bad_trap=0000080040>
43<runargs -vcs_run_args=+bad_trap=0000083420>
44
45
46//n2_ecc_err_adv_mcu___SCRUB_CE n2_err_adv_mcu_scrub_trap_h.s -midas_args=-DSCRUB_CE
47//n2_ecc_err_adv_mcu___SCRUB_UE n2_err_adv_mcu_scrub_trap_h.s -midas_args=-DSCRUB_UE
48
49//n2_ecc_err_adv_mcu___IMISS_CE n2_err_adv_mcu_icache_miss_trap_h.s -midas_args=-DECC_CE -vcs_run_args=+CHNL0_ERR_ENABLE -vcs_run_args=+1BIT_DATA_ERROR -vcs_run_args=+FLIP4
50//n2_ecc_err_adv_mcu___IMISS_UE n2_err_adv_mcu_icache_miss_trap_h.s -midas_args=-DECC_UE -vcs_run_args=+CHNL0_ERR_ENABLE -vcs_run_args=+MULTI_BIT_DATA_ERROR -vcs_run_args=+FLIP4
51
52
53//OLD CE and UE
54n2_ecc_err_adv_mcu___CE_CHNL0 n2_err_adv_mcu_trap_h.s -midas_args=-DECC_CE -vcs_run_args=+CHNL0_ERR_ENABLE -vcs_run_args=+1BIT_DATA_ERROR -vcs_run_args=+FLIP2
55n2_ecc_err_adv_mcu___CE_CHNL1 n2_err_adv_mcu_trap_h.s -midas_args=-DECC_CE -vcs_run_args=+CHNL1_ERR_ENABLE -vcs_run_args=+1BIT_DATA_ERROR -vcs_run_args=+FLIP3
56n2_ecc_err_adv_mcu___UE_CHNL0 n2_err_adv_mcu_trap_h.s -midas_args=-DECC_UE -vcs_run_args=+CHNL0_ERR_ENABLE -vcs_run_args=+MULTI_BIT_DATA_ERROR -vcs_run_args=+FLIP1
57n2_ecc_err_adv_mcu___UE_CHNL1 n2_err_adv_mcu_trap_h.s -midas_args=-DECC_UE -vcs_run_args=+CHNL1_ERR_ENABLE -vcs_run_args=+MULTI_BIT_DATA_ERROR -vcs_run_args=+FLIP4
58
59//NEW CE
60n2_ecc_err_adv_mcu___CE_QUADWORD_1_ON_WRITE_ON_DATA n2_err_adv_mcu_trap_h.s -vcs_run_args=+ONE_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=2 -midas_args=-DECC_CE -vcs_run_args=+QUADWORD_NEW=1 -vcs_run_args=+ON_WRITE_NEW -debussy -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_ENV -vcs_run_args=+DUMP_MCU0 -vcs_run_args=+DUMP_MON -start_dump=14000000
61n2_ecc_err_adv_mcu___CE_QUADWORD_2_ON_WRITE_ON_ECC n2_err_adv_mcu_trap_h.s -vcs_run_args=+ONE_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=2 -midas_args=-DECC_CE -vcs_run_args=+QUADWORD_NEW=2 -vcs_run_args=+ON_ECC_NEW -vcs_run_args=+ON_WRITE_NEW
62n2_ecc_err_adv_mcu___CE_QUADWORD_3_ON_READ_ON_DATA n2_err_adv_mcu_trap_h.s -vcs_run_args=+ONE_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=3 -midas_args=-DECC_CE -vcs_run_args=+QUADWORD_NEW=3
63n2_ecc_err_adv_mcu___CE_QUADWORD_4_ON_READ_ON_ECC n2_err_adv_mcu_trap_h.s -vcs_run_args=+ONE_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=3 -midas_args=-DECC_CE -vcs_run_args=+QUADWORD_NEW=4 -vcs_run_args=+ON_ECC_NEW -debussy -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_ENV -vcs_run_args=+DUMP_MCU0 -vcs_run_args=+DUMP_MON -start_dump=14000000
64
65//NEW UE
66n2_ecc_err_adv_mcu___UE_QUADWORD_1_ON_WRITE_ON_DATA n2_err_adv_mcu_trap_h.s -vcs_run_args=+MULTI_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=2 -midas_args=-DECC_UE -vcs_run_args=+QUADWORD_NEW=1 -vcs_run_args=+ON_WRITE_NEW
67n2_ecc_err_adv_mcu___UE_QUADWORD_2_ON_WRITE_ON_ECC n2_err_adv_mcu_trap_h.s -vcs_run_args=+MULTI_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=2 -midas_args=-DECC_UE -vcs_run_args=+QUADWORD_NEW=2 -vcs_run_args=+ON_ECC_NEW -vcs_run_args=+ON_WRITE_NEW -debussy -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_ENV -vcs_run_args=+DUMP_MCU0 -vcs_run_args=+DUMP_MON -start_dump=14000000
68n2_ecc_err_adv_mcu___UE_QUADWORD_3_ON_READ_ON_DATA n2_err_adv_mcu_trap_h.s -vcs_run_args=+MULTI_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=3 -midas_args=-DECC_UE -vcs_run_args=+QUADWORD_NEW=3 -debussy -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_ENV -vcs_run_args=+DUMP_MCU0 -vcs_run_args=+DUMP_MON -start_dump=14000000
69n2_ecc_err_adv_mcu___UE_QUADWORD_4_ON_READ_ON_ECC n2_err_adv_mcu_trap_h.s -vcs_run_args=+MULTI_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=3 -midas_args=-DECC_UE -vcs_run_args=+QUADWORD_NEW=4 -vcs_run_args=+ON_ECC_NEW
70
71</runargs>
72</runargs>
73</runargs>
74</runargs>
75</runargs>
76</runargs>
77
78</ecc_err_adv_mcu>
79
80<ecc_err_adv_mcu_MT name=ecc_err_adv_mcu_MT>
81
82<runargs -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -vcs_run_args=+l2cpx_mon_off>
83<runargs -vcs_run_args=+debug -vcs_run_args=+ccxPktPrint=spc -vcs_run_args=+info -config_cpp_args=-DIDT_AMB>
84<runargs -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+nb_crc_mon_disable>
85<runargs -vcs_run_args=+show_delta -nosas>
86<runargs -vcs_run_args=+bad_trap=00000000a0 -vcs_run_args=+bad_trap=0000000040 -vcs_run_args=+bad_trap=0000080040>
87<runargs -vcs_run_args=+bad_trap=0000083420>
88
89//<runargs -midas_args=-DCMP_THREAD_START=0xff -vcs_run_args=+finish_mask=0xff -midas_args=-DTHREAD_COUNT=8 -midas_args=-DSYNC_THREADS=0xff>
90<runargs -midas_args=-DCMP_THREAD_START=0x7fffffff -vcs_run_args=+finish_mask=0x7fffffff -midas_args=-DTHREAD_COUNT=31 -midas_args=-DSYNC_THREADS=0x7fffffff>
91
92//OLD CE and UE
93n2_ecc_err_adv_mcu___CE_CHNL0_MT n2_err_adv_mcu_trap_h_31T.s -midas_args=-DECC_CE -vcs_run_args=+CHNL0_ERR_ENABLE -vcs_run_args=+1BIT_DATA_ERROR -vcs_run_args=+FLIP2
94n2_ecc_err_adv_mcu___CE_CHNL1_MT n2_err_adv_mcu_trap_h_31T.s -midas_args=-DECC_CE -vcs_run_args=+CHNL1_ERR_ENABLE -vcs_run_args=+1BIT_DATA_ERROR -vcs_run_args=+FLIP3
95n2_ecc_err_adv_mcu___UE_CHNL0_MT n2_err_adv_mcu_trap_h_31T.s -midas_args=-DECC_UE -vcs_run_args=+CHNL0_ERR_ENABLE -vcs_run_args=+MULTI_BIT_DATA_ERROR -vcs_run_args=+FLIP1
96n2_ecc_err_adv_mcu___UE_CHNL1_MT n2_err_adv_mcu_trap_h_31T.s -midas_args=-DECC_UE -vcs_run_args=+CHNL1_ERR_ENABLE -vcs_run_args=+MULTI_BIT_DATA_ERROR -vcs_run_args=+FLIP4
97
98
99<runargs -vcs_run_args=+DELAY_ECC_NEW=2>
100
101//NEW CE
102n2_ecc_err_adv_mcu___CE_QUADWORD_1_ON_WRITE_ON_DATA_MT n2_err_adv_mcu_trap_h_31T.s -vcs_run_args=+ONE_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=2 -midas_args=-DECC_CE -vcs_run_args=+QUADWORD_NEW=1 -vcs_run_args=+ON_WRITE_NEW -debussy -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_ENV -vcs_run_args=+DUMP_MCU0 -vcs_run_args=+DUMP_MON -start_dump=14000000
103n2_ecc_err_adv_mcu___CE_QUADWORD_2_ON_WRITE_ON_ECC_MT n2_err_adv_mcu_trap_h_31T.s -vcs_run_args=+ONE_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=2 -midas_args=-DECC_CE -vcs_run_args=+QUADWORD_NEW=2 -vcs_run_args=+ON_ECC_NEW -vcs_run_args=+ON_WRITE_NEW
104n2_ecc_err_adv_mcu___CE_QUADWORD_3_ON_READ_ON_DATA_MT n2_err_adv_mcu_trap_h_31T.s -vcs_run_args=+ONE_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=3 -midas_args=-DECC_CE -vcs_run_args=+QUADWORD_NEW=3
105n2_ecc_err_adv_mcu___CE_QUADWORD_4_ON_READ_ON_ECC_MT n2_err_adv_mcu_trap_h_31T.s -vcs_run_args=+ONE_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=3 -midas_args=-DECC_CE -vcs_run_args=+QUADWORD_NEW=4 -vcs_run_args=+ON_ECC_NEW -debussy -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_ENV -vcs_run_args=+DUMP_MCU0 -vcs_run_args=+DUMP_MON -start_dump=14000000
106
107//NEW UE
108n2_ecc_err_adv_mcu___UE_QUADWORD_1_ON_WRITE_ON_DATA_MT n2_err_adv_mcu_trap_h_31T.s -vcs_run_args=+MULTI_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=2 -midas_args=-DECC_UE -vcs_run_args=+QUADWORD_NEW=1 -vcs_run_args=+ON_WRITE_NEW
109n2_ecc_err_adv_mcu___UE_QUADWORD_2_ON_WRITE_ON_ECC_MT n2_err_adv_mcu_trap_h_31T.s -vcs_run_args=+MULTI_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=2 -midas_args=-DECC_UE -vcs_run_args=+QUADWORD_NEW=2 -vcs_run_args=+ON_ECC_NEW -vcs_run_args=+ON_WRITE_NEW -debussy -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_ENV -vcs_run_args=+DUMP_MCU0 -vcs_run_args=+DUMP_MON -start_dump=14000000
110n2_ecc_err_adv_mcu___UE_QUADWORD_3_ON_READ_ON_DATA_MT n2_err_adv_mcu_trap_h_31T.s -vcs_run_args=+MULTI_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=3 -midas_args=-DECC_UE -vcs_run_args=+QUADWORD_NEW=3 -debussy -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_ENV -vcs_run_args=+DUMP_MCU0 -vcs_run_args=+DUMP_MON -start_dump=14000000
111n2_ecc_err_adv_mcu___UE_QUADWORD_4_ON_READ_ON_ECC_MT n2_err_adv_mcu_trap_h_31T.s -vcs_run_args=+MULTI_NIBBLE_ERROR -vcs_run_args=+FLIP_NEW=3 -midas_args=-DECC_UE -vcs_run_args=+QUADWORD_NEW=4 -vcs_run_args=+ON_ECC_NEW
112
113</runargs>
114
115</runargs>
116
117</runargs>
118</runargs>
119</runargs>
120</runargs>
121</runargs>
122</runargs>
123
124</ecc_err_adv_mcu_MT>
125</sys(fc_all)>
Full OpenSPARC design & verification tarball including full HDL.