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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / pmu / spc_pmu.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: spc_pmu.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
36
37<sys(pmu) name=sys(pmu)>
38<sys(all)>
39<sys(all_T2)>
40<sys(nightly)>
41<runargs -nosas -midas_args=-DNOPMUENABLE>
42 isa3_pmu_e2_t1 isa3_pmu_e2_t1.s
43 isa3_pmu_imiss_idle isa3_pmu_imiss_idle.s
44 isa3_pmu_int15 isa3_pmu_int15.s
45// isa3_pmu_spu_desbusy isa3_pmu_spu_desbusy.s
46// isa3_pmu_sl6 isa3_pmu_sl6.s
47 isa3_pmu_cpu_ldst isa3_pmu_cpu_ldst.s
48 isa3_pmu_dmiss_idle isa3_pmu_dmiss_idle.s
49 isa3_pmu_other isa3_pmu_other.s
50
51// test plan
52
53<runargs -vcs_run_args=+TIMEOUT=500000 -vcs_run_args=+skt_timeout=500000 -max_cycle=+5000000 -rtl_timeout=5000000>
54
55//select 5 CCX
56
57//SPU loads to CCX (stream loads)
58//pmu_ccx_sel5_0x01_th0 pmu_ccx_sel5_0x01_th0.s
59// pmu_ccx_sel5_0x01_thAll pmu_ccx_sel5_0x01_thAll.s -vcs_run_args=+thread=ff
60
61//SPU stores to CCX (stream stores)
62// pmu_ccx_sel5_0x02_th0 pmu_ccx_sel5_0x02_th0.s
63// pmu_ccx_sel5_0x02_thAll pmu_ccx_sel5_0x02_thAll.s -vcs_run_args=+thread=ff
64
65//CPU loads to CCX
66pmu_ccx_sel5_0x04_thAll pmu_ccx_sel5_0x04_thAll.s -vcs_run_args=+thread=ff
67
68//CPU stores to CCX
69pmu_ccx_sel5_0x10_thAll pmu_ccx_sel5_0x10_thAll.s -vcs_run_args=+thread=ff
70
71//select 6 SPU operations
72
73// diags are under spu
74// DES/3DES
75// spu_des_pmu_sel6 spu_des_pmu_sel6.s -vcs_run_args=+thread=ff
76// spu_3des_pmu_sel6 spu_3des_pmu_sel6.s
77
78// AES
79// spu_aes_pmu_sel6 spu_aes_pmu_sel6.s -vcs_run_args=+thread=ff
80
81// RC4
82// spu_rc4_pmu_sel6 spu_rc4_pmu_sel6.s -vcs_run_args=+thread=ff
83
84// HASH (md5/sha1/sha256)
85// spu_md5_pmu_sel6 spu_md5_pmu_sel6.s
86// spu_sha1_pmu_sel6 spu_sha1_pmu_sel6.s -vcs_run_args=+thread=ff
87// spu_sha256_pmu_sel6 spu_sha256_pmu_sel6.s
88
89// MA
90// spu_ma_pmu_sel6 spu_ma_pmu_sel6.s -vcs_run_args=+thread=ff
91
92// CRC (32c - tcpip)
93// spu_tcpip_pmu_sel6 spu_tcpip_pmu_sel6.s -vcs_run_args=+thread=ff
94// spu_crc32c_pmu_sel6 spu_crc32c_pmu_sel6.s
95
96// subset (MA and something else)
97
98//select 7 SPU busy
99
100// diags are under spu
101// DES/3DES
102// spu_des_pmu_sel7 spu_des_pmu_sel7.s -vcs_run_args=+thread=ff
103// spu_3des_pmu_sel7 spu_3des_pmu_sel7.s
104
105// AES
106// spu_aes_pmu_sel7 spu_aes_pmu_sel7.s -vcs_run_args=+thread=ff
107
108// RC4
109// spu_rc4_pmu_sel7 spu_rc4_pmu_sel7.s -vcs_run_args=+thread=ff
110
111// HASH
112// spu_md5_pmu_sel7 spu_md5_pmu_sel7.s
113// spu_sha1_pmu_sel7 spu_sha1_pmu_sel7.s -vcs_run_args=+thread=ff
114// spu_sha256_pmu_sel7 spu_sha256_pmu_sel7.s
115
116// MA
117// spu_ma_pmu_sel7 spu_ma_pmu_sel7.s -vcs_run_args=+thread=ff
118
119// CRC (32c,tcpip)
120// spu_tcpip_pmu_sel7 spu_tcpip_pmu_sel7.s -vcs_run_args=+thread=ff
121// spu_crc32c_pmu_sel7 spu_tcpip_pmu_sel7.s
122
123// subset (MA and something else)
124</runargs> // timeout
125</runargs> // -nosas
126
127//ICMiss with errors
128// had to comment out because it relies on stable RAS_ENV for counting
129// however changes in the model can change the ENV_RAS causing this test to fail
130// icMissVariations icMissVariations.pal -vcs_run_args=+err_l2c_on -vcs_run_args=+err_l2c_freq=30 -vcs_run_args=+err_sync_on -tg_seed=1 -midas_args=-DINC_ERR_TRAPS -nosas.
131
132//TLB Misses
133 itlbMiss0 itlbSl3.pal -vcs_run_args=+thread=01
134 itlbMiss1 itlbSl3.pal -vcs_run_args=+thread=02
135 itlbMiss2 itlbSl3.pal -vcs_run_args=+thread=04
136 itlbMiss3 itlbSl3.pal -vcs_run_args=+thread=08
137 itlbMiss4 itlbSl3.pal -vcs_run_args=+thread=10
138 itlbMiss5 itlbSl3.pal -vcs_run_args=+thread=20
139 itlbMiss6 itlbSl3.pal -vcs_run_args=+thread=40
140 itlbMiss7 itlbSl3.pal -vcs_run_args=+thread=80
141
142 dtlbMiss0 dtlbSl3.pal -vcs_run_args=+thread=01
143 dtlbMiss1 dtlbSl3.pal -vcs_run_args=+thread=02
144 dtlbMiss2 dtlbSl3.pal -vcs_run_args=+thread=04
145 dtlbMiss3 dtlbSl3.pal -vcs_run_args=+thread=08
146 dtlbMiss4 dtlbSl3.pal -vcs_run_args=+thread=10
147 dtlbMiss5 dtlbSl3.pal -vcs_run_args=+thread=20
148 dtlbMiss6 dtlbSl3.pal -vcs_run_args=+thread=40
149 dtlbMiss7 dtlbSl3.pal -vcs_run_args=+thread=80
150
151 itlbMissLoOv0 itlbSl3OvL.pal -vcs_run_args=+thread=01
152 itlbMissLoOv1 itlbSl3OvL.pal -vcs_run_args=+thread=02
153 itlbMissLoOv2 itlbSl3OvL.pal -vcs_run_args=+thread=04
154 itlbMissLoOv3 itlbSl3OvL.pal -vcs_run_args=+thread=08
155 itlbMissLoOv4 itlbSl3OvL.pal -vcs_run_args=+thread=10
156 itlbMissLoOv5 itlbSl3OvL.pal -vcs_run_args=+thread=20
157 itlbMissLoOv6 itlbSl3OvL.pal -vcs_run_args=+thread=40
158 itlbMissLoOv7 itlbSl3OvL.pal -vcs_run_args=+thread=80
159
160 itlbMissHiOv0 itlbSl3OvH.pal -vcs_run_args=+thread=01
161 itlbMissHiOv1 itlbSl3OvH.pal -vcs_run_args=+thread=02
162 itlbMissHiOv2 itlbSl3OvH.pal -vcs_run_args=+thread=04
163 itlbMissHiOv3 itlbSl3OvH.pal -vcs_run_args=+thread=08
164 itlbMissHiOv4 itlbSl3OvH.pal -vcs_run_args=+thread=10
165 itlbMissHiOv5 itlbSl3OvH.pal -vcs_run_args=+thread=20
166 itlbMissHiOv6 itlbSl3OvH.pal -vcs_run_args=+thread=40
167 itlbMissHiOv7 itlbSl3OvH.pal -vcs_run_args=+thread=80
168
169 dtlbMissLoOv0 dtlbSl3OvL.pal -vcs_run_args=+thread=01
170 dtlbMissLoOv1 dtlbSl3OvL.pal -vcs_run_args=+thread=02
171 dtlbMissLoOv2 dtlbSl3OvL.pal -vcs_run_args=+thread=04
172 dtlbMissLoOv3 dtlbSl3OvL.pal -vcs_run_args=+thread=08
173 dtlbMissLoOv4 dtlbSl3OvL.pal -vcs_run_args=+thread=10
174 dtlbMissLoOv5 dtlbSl3OvL.pal -vcs_run_args=+thread=20
175 dtlbMissLoOv6 dtlbSl3OvL.pal -vcs_run_args=+thread=40
176 dtlbMissLoOv7 dtlbSl3OvL.pal -vcs_run_args=+thread=80
177
178 dtlbMissHiOv0 dtlbSl3OvH.pal -vcs_run_args=+thread=01
179 dtlbMissHiOv1 dtlbSl3OvH.pal -vcs_run_args=+thread=02
180 dtlbMissHiOv2 dtlbSl3OvH.pal -vcs_run_args=+thread=04
181 dtlbMissHiOv3 dtlbSl3OvH.pal -vcs_run_args=+thread=08
182 dtlbMissHiOv4 dtlbSl3OvH.pal -vcs_run_args=+thread=10
183 dtlbMissHiOv5 dtlbSl3OvH.pal -vcs_run_args=+thread=20
184 dtlbMissHiOv6 dtlbSl3OvH.pal -vcs_run_args=+thread=40
185 dtlbMissHiOv7 dtlbSl3OvH.pal -vcs_run_args=+thread=80
186
187//Cache misses
188 icacheMiss0 icacheMissSl3.s -vcs_run_args=+thread=01
189 icacheMiss1 icacheMissSl3.s -vcs_run_args=+thread=02
190 icacheMiss2 icacheMissSl3.s -vcs_run_args=+thread=04
191 icacheMiss3 icacheMissSl3.s -vcs_run_args=+thread=08
192 icacheMiss4 icacheMissSl3.s -vcs_run_args=+thread=10
193 icacheMiss5 icacheMissSl3.s -vcs_run_args=+thread=20
194 icacheMiss6 icacheMissSl3.s -vcs_run_args=+thread=40
195 icacheMiss7 icacheMissSl3.s -vcs_run_args=+thread=80
196
197 dcacheMiss0 dcacheMissSl3.s -vcs_run_args=+thread=01
198 dcacheMiss1 dcacheMissSl3.s -vcs_run_args=+thread=02
199 dcacheMiss2 dcacheMissSl3.s -vcs_run_args=+thread=04
200 dcacheMiss3 dcacheMissSl3.s -vcs_run_args=+thread=08
201 dcacheMiss4 dcacheMissSl3.s -vcs_run_args=+thread=10
202 dcacheMiss5 dcacheMissSl3.s -vcs_run_args=+thread=20
203 dcacheMiss6 dcacheMissSl3.s -vcs_run_args=+thread=40
204 dcacheMiss7 dcacheMissSl3.s -vcs_run_args=+thread=80
205
206 dcacheOvH0 dcacheOvH.s -vcs_run_args=+thread=01
207 dcacheOvH1 dcacheOvH.s -vcs_run_args=+thread=02
208 dcacheOvH2 dcacheOvH.s -vcs_run_args=+thread=04
209 dcacheOvH3 dcacheOvH.s -vcs_run_args=+thread=08
210 dcacheOvH4 dcacheOvH.s -vcs_run_args=+thread=10
211 dcacheOvH5 dcacheOvH.s -vcs_run_args=+thread=20
212 dcacheOvH6 dcacheOvH.s -vcs_run_args=+thread=40
213 dcacheOvH7 dcacheOvH.s -vcs_run_args=+thread=80
214
215 dcacheOvL0 dcacheOvL.s -vcs_run_args=+thread=01
216 dcacheOvL1 dcacheOvL.s -vcs_run_args=+thread=02
217 dcacheOvL2 dcacheOvL.s -vcs_run_args=+thread=04
218 dcacheOvL3 dcacheOvL.s -vcs_run_args=+thread=08
219 dcacheOvL4 dcacheOvL.s -vcs_run_args=+thread=10
220 dcacheOvL5 dcacheOvL.s -vcs_run_args=+thread=20
221 dcacheOvL6 dcacheOvL.s -vcs_run_args=+thread=40
222 dcacheOvL7 dcacheOvL.s -vcs_run_args=+thread=80
223
224#ifdef SPC
225 dcacheMissL20 dcacheL2MissSl3.s -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1 -nosas
226 dcacheMissL21 dcacheL2MissSl3.s -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
227 dcacheMissL22 dcacheL2MissSl3.s -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
228 dcacheMissL23 dcacheL2MissSl3.s -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
229 dcacheMissL24 dcacheL2MissSl3.s -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
230 dcacheMissL25 dcacheL2MissSl3.s -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
231 dcacheMissL26 dcacheL2MissSl3.s -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
232 dcacheMissL27 dcacheL2MissSl3.s -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1
233
234
235 icMiss0 icMissL2Miss.pal -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1
236 icMiss1 icMissL2Miss.pal -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
237 icMiss2 icMissL2Miss.pal -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
238 icMiss3 icMissL2Miss.pal -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
239 icMiss4 icMissL2Miss.pal -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
240 icMiss5 icMissL2Miss.pal -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
241 icMiss6 icMissL2Miss.pal -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
242 icMiss7 icMissL2Miss.pal -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1
243#endif
244
245 pmuAtomic pmuAtomic.s -vcs_run_args=+thread=all
246
247 pmuOverflowBit ovBitTest.pal -vcs_run_args=+thread=all
248
249#ifdef SPC
250//SL 4 test
251 serviceLevel4 pmu_sl4_mask_n2.pal -vcs_run_args=+l2miss_type=1 -nosas
252#endif
253
254</sys(nightly)>
255</sys(all_T2)>
256</sys(all)>
257</sys(pmu)>
258
259#endif
Full OpenSPARC design & verification tarball including full HDL.