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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_cov_defines.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | integer dmu_back_to_back; | |
36 | ||
37 | bit [5:0] dmu_cmd; | |
38 | bit dmubypass; | |
39 | bit dmudatareq; | |
40 | bit dmudatareq16; | |
41 | bit [127:0] dmudata; | |
42 | bit [15:0] dmc_tag; | |
43 | ||
44 | bit [15:0] dmu_id_out; | |
45 | ||
46 | bit sio_dmu_req; | |
47 | bit [127:0] sio_dmu_data; | |
48 | integer sio_dmu_back_to_back; | |
49 | ||
50 | // concatinate {dmu_cmd,dmubypass} | |
51 | bit [6:0] this_dmu_cmd, last_dmu_cmd; | |
52 | bit last_dmu_cmd_valid = 1'b0; | |
53 | ||
54 | bit [5:0] sio_dmu_this_cmd, sio_dmu_last_cmd; | |
55 | bit sio_dmu_last_cmd_valid = 1'b0; | |
56 | ||
57 | event dmu_sii_sample_evnt_trig; | |
58 | event sio_dmu_sample_evnt_trig; | |
59 | bit sio_dmu_rd_return_de; | |
60 | bit sio_dmu_rd_return_ue; | |
61 | bit [5:0] sio_dmu_rd_return_ctagecc; | |
62 | ||
63 | // -------------DMU-SII----------------- | |
64 | bit dmu_sii_even_addr_par; | |
65 | bit dmu_sii_odd_addr_par; | |
66 | bit dmu_sii_pio_cpl_to_err; | |
67 | bit dmu_sii_pio_cpl_bus_err; | |
68 | bit dmu_sii_pio_cpl_ue_err; | |
69 | bit [15:0] dmu_sii_byte_en; | |
70 | bit [1:0] dmu_sii_parity; | |
71 | bit dmu_sii_datareq; | |
72 | bit dmu_sii_datareq16; | |
73 | bit [1:0] dmu_sii_reqtype; | |
74 | ||
75 | ||
76 | //----------PIO------------------- | |
77 | event pio_sample_evnt_trig; | |
78 | reg [31:0] ncu_pio_b2b; | |
79 | reg [3:0] ncu_pio_credit; | |
80 | reg ncu_pio_wr; | |
81 | reg [2:0] ncu_pio_size; | |
82 | reg [7:0] ncu_pio_bmsk; | |
83 | reg [1:0] ncu_pio_cmap; | |
84 | reg [1:0] ncu_pio_bufid; | |
85 | reg [1:0] ncu_pio_cmd; | |
86 | reg [5:0] ncu_pio_cpu; | |
87 | reg [35:0] ncu_pio_add; | |
88 | ||
89 | //----------IOMMU Invalidates------------------- | |
90 | event iommu_inv_sample_evnt_trig; | |
91 | reg [33:0] ncu_iommu_inv_addr; | |
92 | ||
93 | //----------------ILU-DMU Ingress------------------- | |
94 | // Ingress PEC Record | |
95 | event ilu_dmu_iHdr_sample_evnt_trig; | |
96 | reg [1:0] ilu_dmu_hdr_F; | |
97 | reg [4:0] ilu_dmu_hdr_Type; | |
98 | reg [6:0] ilu_dmu_hdr_F_Type; | |
99 | reg [2:0] ilu_dmu_hdr_TC; | |
100 | reg [1:0] ilu_dmu_hdr_Atr; | |
101 | reg [9:0] ilu_dmu_hdr_Len; | |
102 | reg [15:0] ilu_dmu_hdr_ReqID; | |
103 | reg [7:0] ilu_dmu_hdr_TLPTag; | |
104 | reg [3:0] ilu_dmu_hdr_LastDWBE; | |
105 | reg [3:0] ilu_dmu_hdr_FirstDWBE; | |
106 | reg [61:0] ilu_dmu_hdr_Addr; | |
107 | reg [2:0] ilu_dmu_mps; | |
108 | reg ilu_dmu_b2b; | |
109 | reg [7:0] ilu_dmu_hdr_msg_code; | |
110 | ||
111 | // Ingress Address/Data | |
112 | event dmu_ilu_iBufAddr_sample_evnt_trig; | |
113 | ||
114 | // Ingress Release Record | |
115 | event dmu_ilu_iRel_sample_evnt_trig; | |
116 | reg [8:0] dmu_ilu_irel_rcd; | |
117 | ||
118 | // dmu _ilu egress data path | |
119 | //reg dmu_ilu_idp_addr_vld; | |
120 | // dmu_ilu egress release | |
121 | // reg [8:0] dmu_ilu_erel_rcd; | |
122 | ||
123 | //----------------DMU-ILU Egress-------------------- | |
124 | event dmu_ilu_eHdr_sample_evnt_trig; | |
125 | reg [1:0] dmu_ilu_hdr_F; | |
126 | reg [4:0] dmu_ilu_hdr_Type; | |
127 | reg [6:0] dmu_ilu_hdr_F_Type; | |
128 | reg [2:0] dmu_ilu_hdr_TC; | |
129 | reg [1:0] dmu_ilu_hdr_Atr; | |
130 | reg [9:0] dmu_ilu_hdr_Len; | |
131 | reg [15:0] dmu_ilu_hdr_ReqID; | |
132 | reg [7:0] dmu_ilu_hdr_TLPTag; | |
133 | reg [3:0] dmu_ilu_hdr_LastDWBE; | |
134 | reg [3:0] dmu_ilu_hdr_FirstDWBE; | |
135 | reg [63:0] dmu_ilu_hdr_Addr; | |
136 | reg [5:0] dmu_ilu_hdr_Dptr; | |
137 | reg dmu_ilu_b2b; | |
138 | ||
139 | // Egress Address/Data | |
140 | event ilu_dmu_eBufAddr_sample_evnt_trig; | |
141 | ||
142 | // Egress Release Record | |
143 | event ilu_dmu_eRel_sample_evnt_trig; | |
144 | reg [8:0] ilu_dmu_erel_rcd; | |
145 | ||
146 | //reg [7:0] ilu_dmu_edp_addr; | |
147 | //-----------------ILU-DMU-egress rel-------------- | |
148 | // ilu_dmu egress data path | |
149 | //reg ilu_dmu_edp_addr_vld; | |
150 | // ilu_dmu egress release | |
151 | ||
152 | //reg [7:0] dmu_ilu_idp_addr; | |
153 | ||
154 | //----------------DMU Internal---------------------- | |
155 | event dmu_im2di_sample_evnt_trig; | |
156 | reg [3:0] diu_im2di_addr; | |
157 | reg [15:0] diu_im2di_bmask; | |
158 | ||
159 | event dmu_cl2di_sample_evnt_trig; | |
160 | reg [8:0] diu_cl2di_addr; | |
161 | ||
162 | event dmu_cmu_sample_evnt_trig; | |
163 | reg [6:0] dmu_cmu_Type; | |
164 | reg [9:0] dmu_cmu_Len; | |
165 | reg [11:0] dmu_cmu_Byte; | |
166 | reg [4:0] dmu_cmu_Cntxt; | |
167 | reg [4:0] dmu_cmu_Pkseq; | |
168 | reg [40:0] dmu_cmu_Addr; | |
169 | reg dmu_cmu_Addr_err; | |
170 | reg dmu_cmu_b2b; | |
171 | ||
172 | //----------------PEU_DEM_INT ---------------------- | |
173 | ||
174 | reg [2:0] assert_inta_b2b = 0; | |
175 | reg [2:0] assert_intb_b2b = 0; | |
176 | reg [2:0] assert_intc_b2b = 0; | |
177 | reg [2:0] assert_intd_b2b = 0; | |
178 | reg [2:0] de_assert_inta_b2b = 0; | |
179 | reg [2:0] de_assert_intb_b2b = 0; | |
180 | reg [2:0] de_assert_intc_b2b = 0; | |
181 | reg [2:0] de_assert_intd_b2b = 0; | |
182 | reg [7:0] intx_dup_reg = 0; |