Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / dmu / dmu_int_relocation_sample.vrhpal

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// 
// OpenSPARC T2 Processor File: dmu_int_relocation_sample.vrhpal
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sample dmu_intr_thread_relocation_cov (dmu_int_relocation_if.reloc_cov_seq)
{
  //state   s_DMU_INTCTL_RELOC_SEQ_20    (42'h000_0000_0001);
  //state   s_DMU_INTCTL_RELOC_SEQ_21    (42'h000_0000_0002);
  //state   s_DMU_INTCTL_RELOC_SEQ_22    (42'h000_0000_0004);
  //state   s_DMU_INTCTL_RELOC_SEQ_23    (42'h000_0000_0008);
  state   s_DMU_INTCTL_RELOC_SEQ_24    (42'h000_0000_0010);
  state   s_DMU_INTCTL_RELOC_SEQ_25    (42'h000_0000_0020);
  state   s_DMU_INTCTL_RELOC_SEQ_26    (42'h000_0000_0040);
  state   s_DMU_INTCTL_RELOC_SEQ_27    (42'h000_0000_0080);
  state   s_DMU_INTCTL_RELOC_SEQ_28    (42'h000_0000_0100);
  state   s_DMU_INTCTL_RELOC_SEQ_29    (42'h000_0000_0200);

  state   s_DMU_INTCTL_RELOC_SEQ_30    (42'h000_0000_0400);
  state   s_DMU_INTCTL_RELOC_SEQ_31    (42'h000_0000_0800);
  state   s_DMU_INTCTL_RELOC_SEQ_32    (42'h000_0000_1000);
  state   s_DMU_INTCTL_RELOC_SEQ_33    (42'h000_0000_2000);
  state   s_DMU_INTCTL_RELOC_SEQ_34    (42'h000_0000_4000);
  state   s_DMU_INTCTL_RELOC_SEQ_35    (42'h000_0000_8000);
  state   s_DMU_INTCTL_RELOC_SEQ_36    (42'h000_0001_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_37    (42'h000_0002_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_38    (42'h000_0004_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_39    (42'h000_0008_0000);

  state   s_DMU_INTCTL_RELOC_SEQ_40    (42'h000_0010_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_41    (42'h000_0020_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_42    (42'h000_0040_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_43    (42'h000_0080_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_44    (42'h000_0100_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_45    (42'h000_0200_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_46    (42'h000_0400_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_47    (42'h000_0800_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_48    (42'h000_1000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_49    (42'h000_2000_0000);

  state   s_DMU_INTCTL_RELOC_SEQ_50    (42'h000_4000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_51    (42'h000_8000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_52    (42'h001_0000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_53    (42'h002_0000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_54    (42'h004_0000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_55    (42'h008_0000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_56    (42'h010_0000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_57    (42'h020_0000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_58    (42'h040_0000_0000);
  state   s_DMU_INTCTL_RELOC_SEQ_59    (42'h080_0000_0000);

  //state   s_DMU_INTCTL_RELOC_SEQ_62    (42'h100_0000_0000);
  //state   s_DMU_INTCTL_RELOC_SEQ_63    (42'h200_0000_0000);

}