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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fc_cov.if.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC_FC_COV_IF_VRH | |
36 | #define INC_FC_COV_IF_VRH | |
37 | ||
38 | #include <vera_defines.vrh> | |
39 | #include "fc_cov_defines.vrh" | |
40 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
41 | //This interface works with the verilog module csr_cabinet, which contains references to different | |
42 | //CSR's and other environment related variables. | |
43 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
44 | interface fc_modes_cov_if { | |
45 | input clk CLOCK verilog_node "`TOP.core_clk"; | |
46 | ||
47 | input [5:0] pll_div1 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.ccu_ctl_reg_div1"; | |
48 | input [5:0] pll_div2 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.ccu_ctl_reg_div2"; | |
49 | input [5:0] pll_div3 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.ccu_ctl_reg_div3"; | |
50 | input [5:0] pll_div4 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.ccu_ctl_reg_div4"; | |
51 | ||
52 | input [1:0] system_clock INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.system_clock"; | |
53 | ||
54 | input [22:0] l2_ctl_reg INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.l2_ctl_reg"; | |
55 | ||
56 | input [4:0] mem_density INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.mem_density"; | |
57 | ||
58 | input rank_sel INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.rank_sel"; | |
59 | ||
60 | input single_channel INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.single_channel"; | |
61 | ||
62 | input stack_dimm INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.stack_dimm"; | |
63 | ||
64 | input [2:0] no_of_dimms INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.no_of_dimms"; | |
65 | ||
66 | input ncu_clk_ratio INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.ncu_clk_ratio"; | |
67 | ||
68 | input hash_enable INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.hash_enable"; | |
69 | ||
70 | input [2:0] pcie_mps INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.pcie_mps"; | |
71 | ||
72 | input [2:0] pcie_ref_clk INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.pcie_ref_clk"; | |
73 | ||
74 | input RANDOM_REDUNDANCY_VALUES INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.RANDOM_REDUNDANCY_VALUES"; | |
75 | ||
76 | input RANDOM_POR_RST INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.RANDOM_POR_RST"; | |
77 | ||
78 | input RANDOM_PB_RST INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.RANDOM_PB_RST"; | |
79 | ||
80 | input amb_used INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.amb_used"; | |
81 | ||
82 | input [3:0] denali_link_width INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.denali_link_width"; | |
83 | ||
84 | input boot_done INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.boot_done"; | |
85 | ||
86 | //Partial mode signals | |
87 | input spc0_core_available INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.spc0_core_available"; | |
88 | input spc1_core_available INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.spc1_core_available"; | |
89 | input spc2_core_available INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.spc2_core_available"; | |
90 | input spc3_core_available INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.spc3_core_available"; | |
91 | input spc4_core_available INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.spc4_core_available"; | |
92 | input spc5_core_available INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.spc5_core_available"; | |
93 | input spc6_core_available INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.spc6_core_available"; | |
94 | input spc7_core_available INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.spc7_core_available"; | |
95 | ||
96 | ||
97 | input l2t_pm INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.l2t_pm"; | |
98 | input l2t_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.l2t_ba01"; | |
99 | input l2t_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.l2t_ba23"; | |
100 | input l2t_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.l2t_ba45"; | |
101 | input l2t_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.l2t_ba67"; | |
102 | ||
103 | //sun4v mode | |
104 | input sun4v_mode INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.sun4v_mode"; | |
105 | ||
106 | //FIRE dead lock | |
107 | ||
108 | input p2d_npwr_stall_en INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.p2d_npwr_stall_en"; | |
109 | input im2crm_ilu_stall_en INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.im2crm_ilu_stall_en"; | |
110 | //power_throttle | |
111 | ||
112 | input power_throttle_en INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.power_throttle_en"; | |
113 | //FSR_RTL used | |
114 | input FSR_RTL INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.FSR_RTL"; | |
115 | //scrub happened in one of the L2 banks | |
116 | input scrub_happened INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.scrub_happened"; | |
117 | ||
118 | } | |
119 | ||
120 | //FC coverage object interface files | |
121 | interface fc_cov_ccx { | |
122 | ||
123 | input clk CLOCK verilog_node "`TOP.core_clk"; | |
124 | ||
125 | .for($b=0; $b<=7; $b++){ | |
126 | input [129:0] spc${b}_pcx_data_pa INPUT_EDGE INPUT_SKEW verilog_node "`CCX.spc${b}_pcx_data_pa"; | |
127 | input [8:0] spc${b}_pcx_req_pq INPUT_EDGE INPUT_SKEW verilog_node "`CCX.spc${b}_pcx_req_pq"; | |
128 | ||
129 | input [145:0] cpx_spc${b}_data_cx2 INPUT_EDGE INPUT_SKEW verilog_node "`CCX.cpx_spc${b}_data_cx2"; | |
130 | ||
131 | .} | |
132 | input [7:0] cpx_io_grant_cx INPUT_EDGE INPUT_SKEW verilog_node "`CCX.cpx_io_grant_cx"; | |
133 | } | |
134 | ||
135 | // *********************************************************** | |
136 | // SIGNALS FOR RAS VCOs - MAQ | |
137 | // *********************************************************** | |
138 | interface fc_MCU_L2_NCU_ESR_intf | |
139 | { | |
140 | input clk CLOCK verilog_node "`MCU0.iol2clk"; | |
141 | input mcu_meu_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_meu_error"; | |
142 | input mcu_mec_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_mec_error"; | |
143 | input mcu_dac_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_dac_error"; | |
144 | input mcu_dau_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_dau_error"; | |
145 | input mcu_dsc_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_dsc_error"; | |
146 | input mcu_dsu_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_dsu_error"; | |
147 | input mcu_dbu_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_dbu_error"; | |
148 | input mcu_meb_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_meb_error"; | |
149 | input mcu_fbu_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_fbu_error"; | |
150 | input mcu_fbr_error PSAMPLE INPUT_SKEW verilog_node "`MCU0.rdpctl.rdpctl_fbr_error"; | |
151 | ||
152 | ||
153 | input [63:0] l2_esr PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.l2t0.csr.csr_l2_errstate_reg[63:0]"; | |
154 | ||
155 | input [63:0] ncu_esr PSAMPLE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_esr[63:0]"; | |
156 | } | |
157 | ||
158 | #endif | |
159 | ||
160 | interface fc_cov_ncu { | |
161 | ||
162 | input clk CLOCK verilog_node "`TOP.core_clk"; | |
163 | input [145:0] ncu_cpx_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpx_data_ca"; | |
164 | ||
165 | } | |
166 | ||
167 | interface fc_cov_l2 { | |
168 | ||
169 | input clk CLOCK verilog_node "`TOP.core_clk"; | |
170 | input [145:0] l2t0_cpx_data INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.l2t0.l2t_cpx_data_ca"; | |
171 | ||
172 | } | |
173 | ||
174 |