Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / ilu_peu / ilu_dmu_egress_sample.vrhpal

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// OpenSPARC T2 Processor File: ilu_dmu_egress_sample.vrhpal
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#inc "ilu_peu_cov_inc.pal"


sample dmu_ilu_PEC_egress_F_sample (dmu_ilu_hdr_F_Type) {
  wildcard state PEC_Egress_PIO_MRd ( 7'b0x00000);
  wildcard state PEC_Egress_PIO_IORd ( 7'b0000010);
  wildcard state PEC_Egress_PIO_CfgRd0 ( 7'b0000100);
  wildcard state PEC_Egress_PIO_CfgRd1 ( 7'b0000101);

  wildcard state PEC_Egress_PIO_MemWr ( 7'b1x00000);
  wildcard state PEC_Egress_PIO_IOWr ( 7'b1000010);
  wildcard state PEC_Egress_PIO_CfgWr0 ( 7'b1000100);
  wildcard state PEC_Egress_PIO_CfgWr1 ( 7'b1000101);

  wildcard state PEC_Egress_DMA_Cpl ( 7'b0001010);
  wildcard state PEC_Egress_DMA_CplLk ( 7'b0001011);
  wildcard state PEC_Egress_DMA_CplD ( 7'b1001010);
}

sample dmu_ilu_PEC_egress_TC_sample (dmu_ilu_hdr_TC) {
. &toggle( 3 );

  cov_weight = 1;
}

sample dmu_ilu_PEC_egress_Atr_sample (dmu_ilu_hdr_Atr) {
. &toggle( 2 );

  cov_weight = 1;
}

sample dmu_ilu_PEC_egress_Len_sample (dmu_ilu_hdr_Len) {
. &toggle( 8);
  cov_weight = 1;
}
sample dmu_ilu_PEC_egress_Len1_sample  (dmu_ilu_coverage_ifc.k2y_rcd[110]) 
           {
               state S_k2y_rcd_enq  (1'b0);
           }
sample dmu_ilu_PEC_egress_Len2_sample  (dmu_ilu_coverage_ifc.k2y_rcd[111])
           {
               state S_k2y_rcd_enq  (1'b0);
           }

sample dmu_ilu_PEC_egress_ReqID_sample (dmu_ilu_hdr_ReqID) {
. &toggle( 16);
  cov_weight = 1;
}

sample dmu_ilu_PEC_egress_TLPtag_sample (dmu_ilu_hdr_TLPTag) {
  // Since bit 6 cannot be set to 1, cannot use &toggle any more:
  wildcard state s_bit_07_0 ( 8'b0xxxxxxx );
  wildcard state s_bit_07_1 ( 8'b1xxxxxxx );
  wildcard state s_bit_06_0 ( 8'bx0xxxxxx );
  //wildcard state s_bit_06_1 ( 8'bx1xxxxxx );
  wildcard state s_bit_05_0 ( 8'bxx0xxxxx );
  wildcard state s_bit_05_1 ( 8'bxx1xxxxx );
  wildcard state s_bit_04_0 ( 8'bxxx0xxxx );
  wildcard state s_bit_04_1 ( 8'bxxx1xxxx );
  wildcard state s_bit_03_0 ( 8'bxxxx0xxx );
  wildcard state s_bit_03_1 ( 8'bxxxx1xxx );
  wildcard state s_bit_02_0 ( 8'bxxxxx0xx );
  wildcard state s_bit_02_1 ( 8'bxxxxx1xx );
  wildcard state s_bit_01_0 ( 8'bxxxxxx0x );
  wildcard state s_bit_01_1 ( 8'bxxxxxx1x );
  wildcard state s_bit_00_0 ( 8'bxxxxxxx0 );
  wildcard state s_bit_00_1 ( 8'bxxxxxxx1 );
  
  cov_weight = 1;
}
sample dmu_ilu_PEC_egress_DWBE_sample_last (dmu_ilu_hdr_LastDWBE) {
. &toggle(4 );
  cov_weight = 1;
}
sample dmu_ilu_PEC_egress_DWBE_sample_first (dmu_ilu_hdr_FirstDWBE) {
. &toggle(4 );
  cov_weight = 1;
}

sample dmu_ilu_PEC_egress_Addr (dmu_ilu_hdr_Addr) {
. &toggle(64 );
  cov_weight = 1;
}

sample dmu_ilu_PEC_egress_Dptr_sample (dmu_ilu_hdr_Dptr) {
. &toggle(6 );
  cov_weight = 1;
}