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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / ilu_peu / ilu_peu_cov.vconpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ilu_peu_cov.vconpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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27// may be used, or where a choice of which version of the GPL is applied is
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35connect input dmu_ilu_coverage_ifc.ilu_clk = "`TOP.cpu.dmu.iol2clk" iskew -1
36connect input dmu_ilu_coverage_ifc.peu_clk = "`PEU.pc_clk" iskew -1
37
38
39 connect input dmu_ilu_coverage_ifc.j2d_por_l = "`PEU.rst_por_";
40 connect input dmu_ilu_coverage_ifc.j2d_rst_l = "`PEU.rst_wmr_";
41
42 //------------------------------------------------------------------------
43 // data path -
44 // note: k2y_buf_addr_vld_monitor & y2k_buf_addr_vld_monitor are added
45 // for the use in DMU-ILU monitor only
46 //------------------------------------------------------------------------
47// connect input k2y_buf_addr_vld_monitor = "MAQ";
48 connect input [7:0] dmu_ilu_coverage_ifc.k2y_buf_addr = "`ILU.k2y_buf_addr";// read pointer to IDB
49 connect input [127:0] dmu_ilu_coverage_ifc.y2k_buf_data = "`ILU.y2k_buf_data";// 16-byte data
50 connect input [3:0] dmu_ilu_coverage_ifc.y2k_buf_dpar = "`ILU.y2k_buf_dpar";// data parity
51 connect input y2k_buf_addr_vld_monitor = "`ILU.y2k_buf_addr_vld_monitor";
52 connect input [7:0] dmu_ilu_coverage_ifc.y2k_buf_addr = "`ILU.y2k_buf_addr";// read address to DOU
53 connect input [127:0] dmu_ilu_coverage_ifc.k2y_buf_data = "`ILU.k2y_buf_data";// payload
54 connect input [3:0] dmu_ilu_coverage_ifc.k2y_buf_dpar = "`ILU.k2y_buf_dpar";// word parity for the payload
55
56 //------------------------------------------------------------------------
57 // record interface to TMU
58 //------------------------------------------------------------------------
59 connect input dmu_ilu_coverage_ifc.k2y_rcd_deq = "`ILU.k2y_rcd_deq";// ingress record fifo dequeue
60 //DMU is 116 bits wide so add 10'b0 to LSB when hooking up to DMUXtr in ilu_peu_top.vcon
61 connect input [115:0] dmu_ilu_coverage_ifc.y2k_rcd = "`ILU.y2k_rcd";// ingress PEC record
62 connect input dmu_ilu_coverage_ifc.y2k_rcd_enq = "`ILU.y2k_rcd_enq";// ingress PEC record enqueue
63 connect input [125:0] dmu_ilu_coverage_ifc.k2y_rcd = "`ILU.k2y_rcd";// egress PEC rcd
64 connect input dmu_ilu_coverage_ifc.k2y_rcd_enq = "`ILU.k2y_rcd_enq";// egress enqueue for PEC rcd
65 connect input dmu_ilu_coverage_ifc.y2k_rcd_deq = "`ILU.y2k_rcd_deq";// egress rcd fifo dequeue
66
67 //------------------------------------------------------------------------
68 // release interface with TMU
69 //------------------------------------------------------------------------
70 connect input [8:0] dmu_ilu_coverage_ifc.k2y_rel_rcd = "`ILU.k2y_rel_rcd";// ingress 1 PCIE FC data credit (16-byte data) w/ d_ptr
71 connect input dmu_ilu_coverage_ifc.k2y_rel_enq = "`ILU.k2y_rel_enq"; // ingress enqueue for release record
72 connect input [8:0] dmu_ilu_coverage_ifc.y2k_rel_rcd = "`ILU.y2k_rel_rcd";// egress release rcd
73 connect input dmu_ilu_coverage_ifc.y2k_rel_enq = "`ILU.y2k_rel_enq";// egress enqueue for release rcd
74
75 //------------------------------------------------------------------------
76 // DOU DMA Rd Cpl Buffer status rcd interface with CLU
77 //------------------------------------------------------------------------
78 connect input [5:0] dmu_ilu_coverage_ifc.k2y_dou_dptr = "`ILU.k2y_dou_dptr";
79 connect input dmu_ilu_coverage_ifc.k2y_dou_err = "`ILU.k2y_dou_err";
80 connect input dmu_ilu_coverage_ifc.k2y_dou_vld = "`ILU.k2y_dou_vld";
81
82 //------------------------------------------------------------------------
83 // DMU misc. interface
84 //------------------------------------------------------------------------
85 connect input [2:0] dmu_ilu_coverage_ifc.y2k_mps = "`ILU.y2k_mps";// max. payld size to CMU
86 connect input dmu_ilu_coverage_ifc.y2k_int_l = "`ILU.y2k_int_l";// interrupt req to IMU
87 connect input dmu_ilu_coverage_ifc.p2d_drain = "`ILU.p2d_drain"; // drain req to ILU
88
89 //------------------------------------------------------------------------
90 // CSR ring to DMU
91 //------------------------------------------------------------------------
92 connect input [31:0] dmu_ilu_coverage_ifc.k2y_csr_ring_out = "`ILU.k2y_csr_ring_out";
93 connect input [31:0] dmu_ilu_coverage_ifc.y2k_csr_ring_in = "`ILU.y2k_csr_ring_in";
94
95 //------------------------------------------------------------------------
96 // debug ports
97 //------------------------------------------------------------------------
98 connect input [5:0] dmu_ilu_coverage_ifc.k2y_dbg_sel_a = "`ILU.k2y_dbg_sel_a";
99 connect input [5:0] dmu_ilu_coverage_ifc.k2y_dbg_sel_b = "`ILU.k2y_dbg_sel_b";
100 connect input [7:0] dmu_ilu_coverage_ifc.y2k_dbg_a = "`ILU.y2k_dbg_a";
101 connect input [7:0] dmu_ilu_coverage_ifc.y2k_dbg_b = "`ILU.y2k_dbg_b";
102
103 //------------------------------------------------------------------------
104 // ILU to PEU interface
105 //------------------------------------------------------------------------
106 connect input dmu_ilu_coverage_ifc.p2d_ue_int = "`PEU.p2d_ue_int";
107 connect input dmu_ilu_coverage_ifc.p2d_ce_int = "`PEU.p2d_ce_int";
108 connect input dmu_ilu_coverage_ifc.p2d_oe_int = "`PEU.p2d_oe_int";
109
110
111 //Clock
112 connect input if_ILU_PEU_PCIE_coverage.refclk CLOCK = "`TOP.PCIE_Clock_250";// inputclock 250 MHz
113 // Denali Clocks
114 connect input if_ILU_PEU_PCIE_coverage.DEN_CLK_TX = "`TOP.DEN_CLK_TX";
115 connect input if_ILU_PEU_PCIE_coverage.DEN_CLK_RX = "`TOP.DEN_CLK_RX";
116
117 // Misc Port in FNXPCIEXactor
118 connect input if_ILU_PEU_PCIE_coverage.DEN_RESET = "`TOP.DEN_RESET";
119
120 //The Recieve Detect signals were used in FNX , Included here but not connected to N2
121 connect input if_ILU_PEU_PCIE_coverage.RCV_DET_MODE ;//1bit
122
123
124// connect input [7:0] if_ILU_PEU_PCIE_coverage.RCV_DET_LANES PRZ = "`TOP.TX_P"; //8bit
125
126
127//------------------------------------------------------------------
128// peu registers coverage interface
129//------------------------------------------------------------------
130 connect input peu_registers_coverage_ifc.peu_clk = "`PEU.peu_ptl.l2t_clk" iskew -1 ;
131// connect input peu_registers_coverage_ifc.peu_reg_clk = "`PEU.pc_clk" iskew -1 ;
132 connect input [2:0] peu_registers_coverage_ifc.peu_debug_select_a_block = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a.tlu_dbg_sel_a_block_hw_read[2:0]" ;
133
134 connect input [2:0] peu_debug_select_a_module = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a.tlu_dbg_sel_a_module_hw_read[2:0]";
135 connect input [2:0] peu_debug_select_a_signal = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a.tlu_dbg_sel_a_signal_hw_read[2:0]";
136
137
138 connect input [2:0] peu_debug_select_b_block = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_b.tlu_dbg_sel_b_block_hw_read[2:0]";
139 connect input [2:0] peu_debug_select_b_module = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_b.tlu_dbg_sel_b_module_hw_read[2:0]";
140 connect input [2:0] peu_debug_select_b_signal = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_b.tlu_dbg_sel_b_signal_hw_read[2:0]";
141
142 // peu control register
143 connect input [7:0] peu_control_reg_los_tim = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_l0s_tim_hw_read[7:0]";
144 connect input peu_control_reg_npwr_en = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_npwr_en_hw_read";
145 connect input [2:0] peu_control_reg_cto_sel = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_cto_sel_hw_read[2:0]";
146 connect input [15:0 ] peu_control_reg_config = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_config_hw_read[15:0]";
147
148
149 // peu pme turn off register
150 connect input peu_trn_off_reg_pto = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.trn_off.trn_off_pto_hw_read";
151
152 // peu Ingress Credits Initial register
153 connect input [7:0] peu_ici_reg_nhc = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_nhc_hw_read[7:0]";
154 connect input [7:0] peu_ici_reg_php = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_php_hw_read[7:0]";
155 connect input [7:0] peu_ici_reg_pdc = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_pdc_hw_read[7:0]";
156
157 // peu performance counter select register
158 connect input [1:0] peu_prfc_reg_sel0 = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_prfc.tlu_prfc_sel0_hw_read[1:0]";
159 connect input [7:0] peu_prfc_reg_sel1 = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_prfc.tlu_prfc_sel1_hw_read[7:0]";
160 connect input [7:0] peu_prfc_reg_sel2 = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_prfc.tlu_prfc_sel2_hw_read[7:0]";
161
162
163 // peu link control register
164 connect input peu_link_control_reg_extended_sync = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[7]";
165 connect input peu_link_control_reg_common_clock = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[6]";
166 connect input peu_link_control_reg_retrain = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[5]";
167 connect input peu_link_control_reg_disable = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[4]";
168 connect input peu_link_control_reg_rcb = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[3]";
169 connect input [1:0] peu_link_control_reg_aspm = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[1:0]";
170
171 // peu link status register
172 connect input peu_link_status_reg_slot_clock = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_sts_hw_read[12]";
173 connect input peu_link_status_reg_train = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_sts_hw_read[11]";
174 connect input peu_link_status_reg_error = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_sts_hw_read[10]";
175 connect input [5:0] peu_link_status_reg_width = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_sts_hw_read[9:4]";
176 connect input [3:0] peu_link_status_reg_speed = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_sts_hw_read[3:0]";
177
178
179 // peu slot capability register ?????????? to add
180 // connect input peu_link_status_reg_slot_clock = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_sts_hw_read[12]";
181
182 // peu dlpl dll control register
183 connect input [7:0] peu_dlpl_dll_control_reg_ack_freq = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_ack_freq_hw_read[15:8]";
184 connect input peu_dlpl_dll_control_reg_flow_disable = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_csrbus_read_data[4]";
185 connect input peu_dlpl_dll_control_reg_other_message_req = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_other_message_request_hw_read";
186 connect input peu_dlpl_dll_control_reg_ack_nak_disable = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_ack_nak_disable_hw_read";
187 connect input peu_dlpl_dll_control_reg_data_link_en = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_data_link_en_hw_read";
188
189 // peu dlpl macl / pcs control register
190 connect input [7:0] peu_dlpl_macl_control_reg_link_num = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_link_num_hw_read[7:0]";
191 connect input [7:0] peu_dlpl_macl_control_reg_nfts = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_n_fts_hw_read[7:0]";
192 connect input [5:0] peu_dlpl_macl_control_reg_link_capable = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_link_capable_hw_read[7:0]";
193 connect input peu_dlpl_macl_control_reg_fast_link_mode = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_fast_link_mode_hw_read";
194 connect input peu_dlpl_macl_control_reg_elastic_buffer_disable = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.elastic_buffer_disable_hw_read";
195 connect input peu_dlpl_macl_control_reg_scramble_disable = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.scramble_disable_hw_read";
196 connect input peu_dlpl_macl_control_reg_reset_assert = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.reset_assert_hw_read";
197
198
199 // peu dlpl lane skew control register
200 connect input peu_dlpl_lane_skew_reg_deskew_disable = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lane_skew.lane_skew_deskew_disable_hw_read";
201
202
203 // peu dlpl symbol number register
204 connect input [2:0] peu_dlpl_sym_num_reg_skip = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_num.symbol_num_skip_symbols_hw_read[2:0]";
205 connect input [3:0] peu_dlpl_sym_num_reg_ts1 = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_num.symbol_num_ts1_symbols_hw_read[3:0]";
206
207 // peu dlpl symbol timer register
208 connect input [10:0] peu_dlpl_sym_timer_reg_skip_interval = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_timer.symbol_timer_skip_interval_hw_read[10:0]";
209
210
211
212
213
214
215
216
217 // peu link bit error counter I register
218 connect input peu_link_bit_error_counter_I_reg_ber_en = "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_ber_count_en_ext_read_data";
219 connect input peu_link_bit_error_counter_I_reg_ber_clr = "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_ber_count_clr_ext_read_data";
220
221 connect input [7:0] peu_link_bit_error_counter_I_reg_cnt_bad_dllp = "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_cnt_bad_dllp_ext_read_data[7:0]";
222 connect input [7:0] peu_link_bit_error_counter_I_reg_cnt_bad_tlp = "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_cnt_bad_tlp_ext_read_data[7:0]";
223 connect input [9:0] peu_link_bit_error_counter_I_reg_cnt_pre = "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_cnt_pre_ext_read_data[9:0]";
224
225 // peu link bit error counter II register
226 connect input [63:0] peu_link_bit_error_counter_II_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_bit_err_cnt_2_ext_read_data[63:0]";
227
228
229 // peu serdes receiver lane control register
230 connect input peu_ser_receiver_lane_ctl0_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_0[0]";
231 connect input peu_ser_receiver_lane_ctl1_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_1[0]";
232 connect input peu_ser_receiver_lane_ctl2_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_2[0]";
233 connect input peu_ser_receiver_lane_ctl3_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_3[0]";
234 connect input peu_ser_receiver_lane_ctl4_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_4[0]";
235 connect input peu_ser_receiver_lane_ctl5_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_5[0]";
236 connect input peu_ser_receiver_lane_ctl6_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_6[0]";
237 connect input peu_ser_receiver_lane_ctl7_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_7[0]";
238
239
240// // peu serdes receiver lane status register: los
241// connect input peu_ser_receiver_lane_status0_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_0[3]";
242// connect input peu_ser_receiver_lane_status1_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_1[3]";
243// connect input peu_ser_receiver_lane_status2_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_2[3]";
244// connect input peu_ser_receiver_lane_status3_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_3[3]";
245// connect input peu_ser_receiver_lane_status4_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_4[3]";
246// connect input peu_ser_receiver_lane_status5_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_5[3]";
247// connect input peu_ser_receiver_lane_status6_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_6[3]";
248// connect input peu_ser_receiver_lane_status7_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_7[3]";
249//
250//
251// // peu serdes receiver lane status register : odd group
252// connect input peu_ser_receiver_lane_status0_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_0[2]";
253// connect input peu_ser_receiver_lane_status1_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_1[2]";
254// connect input peu_ser_receiver_lane_status2_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_2[2]";
255// connect input peu_ser_receiver_lane_status3_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_3[2]";
256// connect input peu_ser_receiver_lane_status4_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_4[2]";
257// connect input peu_ser_receiver_lane_status5_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_5[2]";
258// connect input peu_ser_receiver_lane_status6_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_6[2]";
259// connect input peu_ser_receiver_lane_status7_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_hw_read_7[2]";
260
261// // peu serdes receiver lane status register: los
262// connect input peu_ser_receiver_lane_status0_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_0[3]";
263// connect input peu_ser_receiver_lane_status1_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_1[3]";
264// connect input peu_ser_receiver_lane_status2_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_2[3]";
265// connect input peu_ser_receiver_lane_status3_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_3[3]";
266// connect input peu_ser_receiver_lane_status4_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_4[3]";
267// connect input peu_ser_receiver_lane_status5_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_5[3]";
268// connect input peu_ser_receiver_lane_status6_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_6[3]";
269// connect input peu_ser_receiver_lane_status7_reg_los_detect = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_7[3]";
270//
271//
272// // peu serdes receiver lane status register : odd group
273// connect input peu_ser_receiver_lane_status0_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_0[2]";
274// connect input peu_ser_receiver_lane_status1_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_1[2]";
275// connect input peu_ser_receiver_lane_status2_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_2[2]";
276// connect input peu_ser_receiver_lane_status3_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_3[2]";
277// connect input peu_ser_receiver_lane_status4_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_4[2]";
278// connect input peu_ser_receiver_lane_status5_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_5[2]";
279// connect input peu_ser_receiver_lane_status6_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_6[2]";
280// connect input peu_ser_receiver_lane_status7_reg_odd_group = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_7[2]";
281
282
283 // peu serdes transmitter lane control register
284 connect input peu_ser_xmitter_ctl_lane0_reg_invert_polarity = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_0[1]";
285 connect input peu_ser_xmitter_ctl_lane1_reg_invert_polarity = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_1[1]";
286 connect input peu_ser_xmitter_ctl_lane2_reg_invert_polarity = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_2[1]";
287 connect input peu_ser_xmitter_ctl_lane3_reg_invert_polarity = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_3[1]";
288 connect input peu_ser_xmitter_ctl_lane4_reg_invert_polarity = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_4[1]";
289 connect input peu_ser_xmitter_ctl_lane5_reg_invert_polarity = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_5[1]";
290 connect input peu_ser_xmitter_ctl_lane6_reg_invert_polarity = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_6[1]";
291 connect input peu_ser_xmitter_ctl_lane7_reg_invert_polarity = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_7[1]";
292
293
294 // peu serdes transmitter lane control register
295 connect input peu_ser_xmitter_ctl_lane0_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_0[0]";
296 connect input peu_ser_xmitter_ctl_lane1_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_1[0]";
297 connect input peu_ser_xmitter_ctl_lane2_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_2[0]";
298 connect input peu_ser_xmitter_ctl_lane3_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_3[0]";
299 connect input peu_ser_xmitter_ctl_lane4_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_4[0]";
300 connect input peu_ser_xmitter_ctl_lane5_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_5[0]";
301 connect input peu_ser_xmitter_ctl_lane6_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_6[0]";
302 connect input peu_ser_xmitter_ctl_lane7_reg_entest = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_7[0]";
303
304
305 //-----------------------
306 // register connections for above registers but with full register range
307 //-----------------------
308
309 // debug_select_a
310 connect input [8:0] peu_debug_select_a_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a.tlu_dbg_sel_a_csrbus_read_data[8:0]";
311
312 connect input [8:0] peu_debug_select_b_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_b.tlu_dbg_sel_b_csrbus_read_data[8:0]";
313
314 // peu control register
315 connect input [31:0] peu_control_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_csrbus_read_data[31:0]";
316
317 // peu Ingress Credits Initial register
318 connect input [59:0] peu_ici_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_csrbus_read_data[59:0]";
319
320 // peu performance counter select register
321 connect input [17:0] peu_prfc_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_prfc.tlu_prfc_csrbus_read_data[17:0]";
322
323
324 // peu link control register
325 connect input [63:0] peu_link_control_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_csrbus_read_data[63:0]";
326
327 // peu link status register
328 connect input [63:0] peu_link_status_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_sts.lnk_sts_csrbus_read_data[63:0]";
329
330
331 // peu slot capability register ?????????? to add
332 // connect input peu_link_status_reg_slot_clock = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_sts_csrbus_read_data[63:0]";
333
334 // peu dlpl dll control register
335 connect input [63:0] peu_dlpl_dll_control_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_csrbus_read_data[63:0]";
336
337 // peu dlpl macl / pcs control register
338 connect input [63:0] peu_dlpl_macl_control_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_csrbus_read_data[63:0]";
339
340
341 // peu dlpl lane skew control register
342 connect input [63:0] peu_dlpl_lane_skew_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lane_skew.lane_skew_csrbus_read_data";
343
344
345 // peu dlpl symbol number register
346 connect input [63:0] peu_dlpl_sym_num_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_num.symbol_num_csrbus_read_data[63:0]";
347
348 // peu dlpl symbol timer register
349 connect input [63:0] peu_dlpl_sym_timer_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_timer.symbol_timer_csrbus_read_data[63:0]";
350
351
352 connect input [63:0] peu_dlpl_core_status_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.core_status.core_status_csrbus_read_data[63:0]";
353
354
355 // peu serdes receiver lane control register
356 connect input [63:0] peu_ser_receiver_lane_ctl0_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_csrbus_read_data_0[63:0]";
357
358
359 // peu serdes receiver lane status register: los
360 connect input [63:0] peu_ser_receiver_lane_status0_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_0[63:0]";
361
362
363 // peu serdes transmitter lane control register
364 connect input [63:0] peu_ser_xmitter_ctl_lane0_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_csrbus_read_data_0[63:0]";
365
366
367
368 //------------------------------------------------------------------------
369 // peu ras
370 //------------------------------------------------------------------------
371
372 // peu_oe_log_en register
373 connect input peu_oe_log_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_log.oe_log_w_ld";
374 connect input [23:0] peu_oe_log_en_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_log.oe_log_en_hw_read[23:0]";
375
376
377 // peu_oe_int_en register
378 connect input peu_oe_int_en_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_int_en.oe_int_en_w_ld";
379 connect input [63:0] peu_oe_int_en_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_int_en.oe_int_en_hw_read[63:0]";
380
381 // peu_oe_err register
382 connect input peu_oe_err_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_w_ld";
383 connect input peu_oe_err_rw1c = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.rw1c_alias";
384 connect input peu_oe_err_rw1s = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.rw1s_alias";
385 connect input [63:0] peu_oe_err_hw_set = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_hw_set[63:0]";
386 connect input [63:0] peu_oe_err_csrbus_wr_data = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.csrbus_wr_data[63:0]";
387 connect input [63:0] peu_oe_err_csrbus_read_data = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_csrbus_read_data[63:0]";
388
389
390 // peu_ue_log_en register
391 connect input peu_ue_log_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_log.ue_log_w_ld";
392 connect input [23:0] peu_ue_log_en_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_log.ue_log_en_hw_read[23:0]";
393
394
395 // peu_ue_int_en register
396 connect input peu_ue_int_en_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_int_en.ue_int_en_w_ld";
397 connect input [63:0] peu_ue_int_en_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_int_en.ue_int_en_hw_read[63:0]";
398
399 // peu_ue_err register
400 connect input peu_ue_err_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_w_ld";
401 connect input peu_ue_err_rw1c = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.rw1c_alias";
402 connect input peu_ue_err_rw1s = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.rw1s_alias";
403 connect input [63:0] peu_ue_err_hw_set = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_hw_set[63:0]";
404 connect input [63:0] peu_ue_err_csrbus_wr_data = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.csrbus_wr_data[63:0]";
405 connect input [63:0] peu_ue_err_csrbus_read_data = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_csrbus_read_data[63:0]";
406
407
408 // peu_ce_log_en register
409 connect input peu_ce_log_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_log.ce_log_w_ld";
410 connect input [23:0] peu_ce_log_en_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_log.ce_log_en_hw_read[23:0]";
411
412
413 // peu_ce_int_en register
414 connect input peu_ce_int_en_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_int_en.ce_int_en_w_ld";
415 connect input [63:0] peu_ce_int_en_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_int_en.ce_int_en_hw_read[63:0]";
416
417 // peu_ce_err register
418 connect input peu_ce_err_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.ce_err_w_ld";
419 connect input peu_ce_err_rw1c = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.rw1c_alias";
420 connect input peu_ce_err_rw1s = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.rw1s_alias";
421 connect input [63:0] peu_ce_err_hw_set = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.ce_err_hw_set[63:0]";
422 connect input [63:0] peu_ce_err_csrbus_wr_data = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.csrbus_wr_data[63:0]";
423 connect input [63:0] peu_ce_err_csrbus_read_data = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.ce_err_csrbus_read_data[63:0]";
424
425
426 // peu_event_log_en register
427 connect input peu_event_log_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_log.event_err_log_en_w_ld";
428 connect input [63:0] peu_event_log_en_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_log.event_err_log_en_csrbus_read_data[63:0]";
429
430
431 // peu_event_int_en register
432 connect input peu_event_int_en_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_int_en.event_err_int_en_w_ld";
433 connect input [63:0] peu_event_int_en_reg = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_int_en.event_err_int_en_hw_read[63:0]";
434
435
436 // peu_event_err status register
437 connect input peu_event_err_w_ld = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.event_err_sts_clr_w_ld";
438 connect input peu_event_err_rw1c = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.rw1c_alias";
439 connect input peu_event_err_rw1s = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.rw1s_alias";
440 connect input [63:0] peu_event_err_hw_set = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.event_err_sts_clr_hw_set[63:0]";
441 connect input [63:0] peu_event_err_csrbus_wr_data = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.csrbus_wr_data[63:0]";
442 connect input [63:0] peu_event_err_csrbus_read_data = "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.event_err_sts_clr_csrbus_read_data[63:0]";
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450 } // end of interface peu_registers_coverage_ifc
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Full OpenSPARC design & verification tarball including full HDL.