projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2_cpx_fields_sample.vrhpal
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2_cpx_fields_sample.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35wildcard state LOAD_miss_1 ( {1'b1, LOAD_RET, 1'b1, 2'bxx, 1'bx, 3'bx, 1'bx, 3'bxxx, 2'b00, 5'bx} );
36wildcard state LOAD_ce ( {1'b1, LOAD_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 1'bx, 3'bxxx, 2'b00, 5'bx} );
37wildcard state LOAD_ue ( {1'b1, LOAD_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 1'bx, 3'bxxx, 2'b00, 5'bx} );
38wildcard state LOAD_invway_0( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b000, 2'b00, 5'bx} );
39wildcard state LOAD_invway_1( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b001, 2'b00, 5'bx} );
40wildcard state LOAD_invway_2( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b010, 2'b00, 5'bx} );
41wildcard state LOAD_invway_3( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b011, 2'b00, 5'bx} );
42wildcard state LOAD_invway_4( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b100, 2'b00, 5'bx} );
43wildcard state LOAD_invway_5( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b101, 2'b00, 5'bx} );
44wildcard state LOAD_invway_6( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b110, 2'b00, 5'bx} );
45wildcard state LOAD_invway_7( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b111, 2'b00, 5'bx} );
46wildcard state LOAD_wv_0 ( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'b0, 3'bxxx, 2'b00, 5'bx} );
47wildcard state LOAD_wv_1 ( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'b1, 3'bxxx, 2'b00, 5'bx} );
48
49// PREFETCH_RET vld reqtype miss err nc thr invway f4b at pf data[127:123]
50wildcard state PREFETCH_miss_0 ( {1'b1, LOAD_RET, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b01, 5'bx} );
51wildcard state PREFETCH_miss_1 ( {1'b1, LOAD_RET, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b01, 5'bx} );
52wildcard state PREFETCH_ce ( {1'b1, LOAD_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b01, 5'bx} );
53wildcard state PREFETCH_ue ( {1'b1, LOAD_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b01, 5'bx} );
54wildcard state PREFETCH_invway_0( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b000, 1'bx, 2'b01, 5'bx} );
55wildcard state PREFETCH_invway_1( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b000, 1'bx, 2'b01, 5'bx} );
56wildcard state PREFETCH_invway_2( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b000, 1'bx, 2'b01, 5'bx} );
57wildcard state PREFETCH_invway_3( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b000, 1'bx, 2'b01, 5'bx} );
58
59// IFILL_RET vld reqtype miss err nc thr invway f4b at pf data[127:123]
60wildcard state IFILL_miss_0 ( {1'b1, IFILL_RET, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'b0, 2'bx0, 5'bx} );
61wildcard state IFILL_miss_1 ( {1'b1, IFILL_RET, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'b0, 2'bx0, 5'bx} );
62wildcard state IFILL_ce ( {1'b1, IFILL_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'b0, 2'bx0, 5'bx} );
63wildcard state IFILL_ue ( {1'b1, IFILL_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'b0, 2'bx0, 5'bx} );
64wildcard state IFILL_invway_0( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'bx00, 1'b0, 2'bx0, 5'bx} );
65wildcard state IFILL_invway_1( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'bx01, 1'b0, 2'bx0, 5'bx} );
66wildcard state IFILL_invway_2( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'bx10, 1'b0, 2'bx0, 5'bx} );
67wildcard state IFILL_invway_3( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'bx11, 1'b0, 2'bx0, 5'bx} );
68wildcard state IFILL_wv_0 ( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b0xx, 1'b0, 2'bx0, 5'bx} );
69wildcard state IFILL_wv_1 ( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b1xx, 1'b0, 2'bx0, 5'bx} );
70
71// ST_ACK vld reqtype miss err nc thr invway f4b at pf data[127:123]
72wildcard state STORE_miss_0( {1'b1, ST_ACK, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b00, 5'b0} );
73wildcard state STORE_miss_1( {1'b1, ST_ACK, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b00, 5'b0} );
74
75// BLKSTORE_ACK/BLKINITST_ACK vld reqtype miss err nc thr invway f4b at pf data[127:123]
76wildcard state BLKINITST_miss_0( {1'b1, ST_ACK, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b00, 5'b00100} );
77wildcard state BLKINITST_miss_1( {1'b1, ST_ACK, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b00, 5'b00100} );
78
79// CAS_RET/SWAP_RET vld reqtype miss err nc thr invway f4b at pf data[127:123]
80wildcard state CAS_SWAP_ce( {1'b1, LOAD_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b10, 5'bx} );
81wildcard state CAS_SWAP_ue( {1'b1, LOAD_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b10, 5'bx} );
82
83// STRLOAD_RET vld reqtype miss err nc thr invway f4b at pf data[127:123]
84wildcard state STRLOAD_miss_0( {1'b1, STRLOAD_RET, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
85wildcard state STRLOAD_miss_1( {1'b1, STRLOAD_RET, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
86wildcard state STRLOAD_ce ( {1'b1, STRLOAD_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
87wildcard state STRLOAD_ue ( {1'b1, STRLOAD_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
88
89// FWDRQ_LOAD_RET vld reqtype miss err nc thr invway f4b at pf data[127:123]
90/*wildcard state FWDRQ_LOAD_miss_0( {1'b1, FWD_RPY_RET, 1'b0, 2'bxx, 1'b1, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
91wildcard state FWDRQ_LOAD_miss_1( {1'b1, FWD_RPY_RET, 1'b1, 2'bxx, 1'b1, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
92wildcard state FWDRQ_LOAD_ce ( {1'b1, FWD_RPY_RET, 1'bx, 2'bx1, 1'b1, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
93wildcard state FWDRQ_LOAD_ue ( {1'b1, FWD_RPY_RET, 1'bx, 2'b1x, 1'b1, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
94*/
95// FWDRQ_STORE_ACK vld reqtype miss err nc thr invway f4b at pf data[127:123]
96/*wildcard state FWDRQ_STORE_miss_0( {1'b1, FWD_RPY_RET, 1'b0, 2'bxx, 1'b0, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'b0} );
97wildcard state FWDRQ_STORE_miss_1( {1'b1, FWD_RPY_RET, 1'b1, 2'bxx, 1'b0, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'b0} );
98*/
99// ERR_RET vld reqtype miss err nc thr invway f4b at pf data[127:123]
100wildcard state ERR_RET_ce ( {1'b1, ERR_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx, 5'bx} );
101wildcard state ERR_RET_ue ( {1'b1, ERR_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx, 5'bx} );
102wildcard state ERR_RET_tid_0( {1'b1, ERR_RET, 1'bx, 2'bxx, 1'bx, 3'h0, 3'bxxx, 1'bx, 2'bx, 5'bx} );
103wildcard state ERR_RET_tid_1( {1'b1, ERR_RET, 1'bx, 2'bxx, 1'bx, 3'h1, 3'bxxx, 1'bx, 2'bx, 5'bx} );
104wildcard state ERR_RET_tid_2( {1'b1, ERR_RET, 1'bx, 2'bxx, 1'bx, 3'h2, 3'bxxx, 1'bx, 2'bx, 5'bx} );
105wildcard state ERR_RET_tid_3( {1'b1, ERR_RET, 1'bx, 2'bxx, 1'bx, 3'h3, 3'bxxx, 1'bx, 2'bx, 5'bx} );
106
107//review add new cpx packet types
Full OpenSPARC design & verification tarball including full HDL.