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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / ncu / ncu_cov.if.vrhpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ncu_cov.if.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef INC_NCU_COV_IF_VRH
36#define INC_NCU_COV_IF_VRH
37
38#include <vera_defines.vrh>
39#include "ncu_cov_defines.vrh"
40
41#define NCU_C2ISC tb_top.cpu.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_c2isc_ctl
42#define NCU_I2CSD tb_top.cpu.ncu.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csd_ctl
43#define NCU_I2CSC tb_top.cpu.ncu.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csc_ctl
44#define NCU_C2IFC tb_top.cpu.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifc_ctl
45#define NCU_I2CFC tb_top.cpu.ncu.ncu_fcd_ctl.ncu_i2cfcd_ctl.ncu_i2cfc_ctl
46
47interface ncu_cov_ccx {
48
49 input clk CLOCK verilog_node "`NCU.gclk";
50
51 input ncu_pcx_stall_pq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ncu_pcx_stall_pq";
52 input ncu_pcx_stall_pq1 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ncu_pcx_stall_pq1";
53
54#ifdef FC_COVERAGE
55 input pcx_ncu_data_rdy_px1 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.pcx_ncu_data_rdy_px1";
56 input [129:0] pcx_ncu_data_px2 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.pcx_ncu_data_px2";
57 input pcx_ncu_data_rdy_px1_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.pcx_ncu_data_rdy_px1";
58 input [129:0] pcx_ncu_data_px2_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.pcx_ncu_data_px2";
59#else
60 input pcx_ncu_data_rdy_px1 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.pcx_ncu_data_rdy_px1";
61 input [129:0] pcx_ncu_data_px2 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.pcx_ncu_data_px2";
62 input pcx_ncu_data_rdy_px1_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.pcx_ncu_data_rdy_px1";
63 input [129:0] pcx_ncu_data_px2_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.pcx_ncu_data_px2";
64#endif
65
66
67 input [7:0] cpx_ncu_grant_cx INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpx_ncu_grant_cx";
68 input [7:0] ncu_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ncu_cpx_req_cq";
69 input [7:0] cpx_ncu_grant_cx_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpx_ncu_grant_cx";
70 input [145:0] ncu_cpx_data_ca INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpx_data_ca";
71
72}
73
74interface ncu_cov_ios {
75
76
77 input clk CLOCK verilog_node "`NCU.iol2clk";
78 input int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csc_ctl.int_vld";
79 input lhs_intman_acc INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csc_ctl.lhs_intman_acc";
80
81 input [6:0] lhs_intman_addr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.lhs_intman_addr";
82 input [6:0] io_intman_addr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.io_intman_addr";
83
84 input [1:0] ssi_scksel INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_ncu_scksel";
85
86 input ncu_mio_ssi_mosi INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mio_ssi_mosi";
87 input mio_ncu_ssi_miso INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mio_ncu_ssi_miso";
88 input mio_ncu_ext_int_l INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mio_ncu_ext_int_l";
89
90 input [2:0] ssi_sm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssitop_ctl.ncu_ssisif_ctl.ssi_sm";
91 input [1:0] if_sm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssitop_ctl.ncu_ssiuif_ctl.if_sm";
92
93//interface ncu_cov_siu
94 input siu_ncu_req INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_req";
95 input ncu_siu_gnt INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_gnt";
96 input [31:0] siu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_data";
97 input ncu_dmu_mondo_ack INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_mondo_ack";
98 input ncu_dmu_mondo_nack INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_mondo_nack";
99 input [5:0] ncu_dmu_mondo_id INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_mondo_id";
100 input [31:0] siu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_data";
101
102.for($b=0; $b<4; $b++){
103//interface ncu_cov_mcu${b}
104
105 input mcu${b}_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_stall";
106 input mcu${b}_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.mcu${b}_ncu_stall_in";
107 input ncu_mcu${b}_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_vld";
108 input [3:0] ncu_mcu${b}_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_data";
109
110 input ncu_mcu${b}_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_stall";
111 input mcu${b}_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_vld";
112 input [3:0] mcu${b}_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_data";
113
114 input mcu${b}_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_vld";
115 input [3:0] mcu${b}_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_data";
116
117.}
118
119//interface ncu_cov_niu
120
121 input niu_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_stall";
122 input niu_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.niu_ncu_stall_in";
123 input ncu_niu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_vld";
124 input [31:0] ncu_niu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_data";
125
126 input ncu_niu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_stall";
127
128 input niu_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_vld";
129 input [31:0] niu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_data";
130
131 input niu_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_vld";
132 input [31:0] niu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_data";
133//interface ncu_cov_dmu
134
135 input ncu_dmu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_vld";
136 input [31:0] ncu_dmu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_data";
137 input dmu_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_vld";
138
139 input ncu_dmu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_stall";
140 input [31:0] dmu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_data";
141 input dmu_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_stall";
142 input dmu_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.dmu_ncu_stall_in";
143
144 input dmu_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_vld";
145 input [31:0] dmu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_data";
146//interface ncu_cov_dmupio
147
148 input dmu_ncu_wrack_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_wrack_vld";
149 input [3:0] dmu_ncu_wrack_tag INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_wrack_tag";
150 input ncu_dmu_pio_hdr_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_pio_hdr_vld";
151 input ncu_dmu_mmu_addr_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_mmu_addr_vld";
152 input [63:0] ncu_dmu_pio_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_pio_data";
153//interface ncu_cov_rst
154
155 input [3:0] ncu_rst_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_rst_data";
156 input rst_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_stall";
157 input rst_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.rst_ncu_stall_in";
158 input ncu_rst_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_rst_vld";
159 input ncu_rst_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_rst_stall";
160 input rst_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_vld";
161 input [3:0] rst_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_data";
162
163 input rst_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_vld";
164 input [3:0] rst_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_data";
165//interface ncu_cov_tcu
166
167 input [7:0] ncu_tcu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_tcu_data";
168 input tcu_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_stall";
169 input tcu_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.tcu_ncu_stall_in";
170 input ncu_tcu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_tcu_vld";
171 input ncu_tcu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_tcu_stall";
172 input tcu_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_vld";
173 input [7:0] tcu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_data";
174 input tcu_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_vld";
175 input [7:0] tcu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_data";
176
177//interface ncu_cov_dbg1
178
179 input [3:0] ncu_dbg1_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dbg1_data";
180 input dbg1_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_stall";
181 input dbg1_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.dbg1_ncu_stall_in";
182 input ncu_dbg1_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dbg1_vld";
183 input ncu_dbg1_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dbg1_stall";
184 input dbg1_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_vld";
185 input [3:0] dbg1_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_data";
186 input dbg1_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_vld";
187 input [3:0] dbg1_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_data";
188
189
190//interface ncu_cov_ssi
191
192 input [3:0] ncu_ssi_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssi_data";
193 input ssi_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_stall";
194 input ssi_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ssi_ncu_stall_in";
195 input ncu_ssi_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssi_vld";
196 input ncu_ssi_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssi_stall";
197 input ssi_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_vld";
198 input [3:0] ssi_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_data";
199 input ssi_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_vld";
200 input [3:0] ssi_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_data";
201
202
203//interface ncu_cov_ccu
204
205 input ccu_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_stall";
206 input ccu_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ccu_ncu_stall_in";
207 input ncu_ccu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ccu_vld";
208 input [3:0] ncu_ccu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ccu_data";
209 input ncu_ccu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ccu_stall";
210 input ccu_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_vld";
211 input [3:0] ccu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_data";
212 input ccu_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_vld";
213 input [3:0] ccu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_data";
214
215//interface ncu_cov_efu
216
217 input efu_ncu_coreavl_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_coreavl_xfer_en";
218 input efu_ncu_bankavl_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_bankavl_xfer_en";
219 input efu_ncu_fuse_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_fuse_data";
220 input efu_ncu_fusestat_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_fusestat_xfer_en";
221 input efu_ncu_srlnum0_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_srlnum0_xfer_en";
222 input efu_ncu_srlnum1_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_srlnum1_xfer_en";
223 input efu_ncu_srlnum2_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_srlnum2_xfer_en";
224
225
226
227//interface ncu_cov_asi
228
229 input rst_ncu_unpark_thread INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_unpark_thread";
230 input rst_ncu_xir_ INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_xir_";
231 input rst_ncu_unpark_thread_in INPUT_EDGE verilog_node "`NCU.rst_ncu_unpark_thread";
232 input ncu_rst_xir_done INPUT_EDGE verilog_node "`NCU.ncu_rst_xir_done";
233 input ncu_spc0_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc0_core_available";
234 input ncu_spc1_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc1_core_available";
235 input ncu_spc2_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc2_core_available";
236 input ncu_spc3_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc3_core_available";
237 input ncu_spc4_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc4_core_available";
238 input ncu_spc5_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc5_core_available";
239 input ncu_spc6_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc6_core_available";
240 input ncu_spc7_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc7_core_available";
241 input ncu_spc0_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc0_core_enable_status";
242 input ncu_spc1_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc1_core_enable_status";
243 input ncu_spc2_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc2_core_enable_status";
244 input ncu_spc3_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc3_core_enable_status";
245 input ncu_spc4_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc4_core_enable_status";
246 input ncu_spc5_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc5_core_enable_status";
247 input ncu_spc6_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc6_core_enable_status";
248 input ncu_spc7_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc7_core_enable_status";
249 input [7:0] ncu_spc0_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc0_core_running";
250 input [7:0] ncu_spc1_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc1_core_running";
251 input [7:0] ncu_spc2_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc2_core_running";
252 input [7:0] ncu_spc3_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc3_core_running";
253 input [7:0] ncu_spc4_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc4_core_running";
254 input [7:0] ncu_spc5_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc5_core_running";
255 input [7:0] ncu_spc6_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc6_core_running";
256 input [7:0] ncu_spc7_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc7_core_running";
257 input [7:0] spc0_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc0_ncu_core_running_status";
258 input [7:0] spc1_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc1_ncu_core_running_status";
259 input [7:0] spc2_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc2_ncu_core_running_status";
260 input [7:0] spc3_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc3_ncu_core_running_status";
261 input [7:0] spc4_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc4_ncu_core_running_status";
262 input [7:0] spc5_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc5_ncu_core_running_status";
263 input [7:0] spc6_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc6_ncu_core_running_status";
264 input [7:0] spc7_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc7_ncu_core_running_status";
265 // end of interface ncu_cov
266//interface ncu_cov_bank
267
268
269 input ncu_spc_pm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_pm";
270 input ncu_spc_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_ba01";
271 input ncu_spc_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_ba23";
272 input ncu_spc_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_ba45";
273 input ncu_spc_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_ba67";
274 input ncu_spc_l2_idx_hash_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_l2_idx_hash_en";
275
276 input ncu_sii_pm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_pm";
277 input ncu_sii_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_ba01";
278 input ncu_sii_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_ba23";
279 input ncu_sii_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_ba45";
280 input ncu_sii_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_ba67";
281 input ncu_sii_l2_idx_hash_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_l2_idx_hash_en";
282 input ncu_l2t_pm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_pm";
283 input ncu_l2t_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_ba01";
284 input ncu_l2t_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_ba23";
285 input ncu_l2t_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_ba45";
286 input ncu_l2t_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_ba67";
287
288 input ncu_mcu_pm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_pm";
289 input ncu_mcu_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_ba01";
290 input ncu_mcu_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_ba23";
291 input ncu_mcu_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_ba45";
292 input ncu_mcu_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_ba67";
293 input ssi_int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.ssi_int_vld";
294 input niu_int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.niu_int_vld";
295 input spc_int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.ncu_man_int_vld";
296 input sii_mondo_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.sii_mondo_vld";
297
298}
299/*
300
301//interface ncu_cov_l2t {
302
303
304 input [41:0] l2t0_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t0_dbgbus_out";
305 input [41:0] l2t1_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t1_dbgbus_out";
306 input [41:0] l2t2_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t2_dbgbus_out";
307 input [41:0] l2t3_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t3_dbgbus_out";
308 input [41:0] l2t4_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t4_dbgbus_out";
309 input [41:0] l2t5_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t5_dbgbus_out";
310 input [41:0] l2t6_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t6_dbgbus_out";
311 input [41:0] l2t7_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t7_dbgbus_out";
312} // end of interface ncu_cov
313*/
314
315interface ncu_rtl_io_cov {
316
317input clk CLOCK verilog_node "`NCU.iol2clk";
318
319 input [6:0] intman_tbl_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intman_tbl_raddr";
320 input [6:0] intman_tbl_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intman_tbl_waddr";
321 input intman_tbl_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intman_tbl_wr";
322 input intman_tbl_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intman_tbl_rden";
323
324
325 input [5:0] io_buf_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.iobuf_tail_ptr";
326 input io_buf_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.iobuf_wr";
327 input [6:0] io_intman_addr INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSD.io_intman_addr";
328 input int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.int_vld";
329
330 input [4:0] cpu_buf_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpubuf_head_ptr";
331 input cpu_buf_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpubuf_rden";
332 input cpu_buf_rd_sel INPUT_EDGE INPUT_SKEW verilog_node "`NCU_C2ISC.head_inc";
333}
334
335
336interface ncu_rtl_ccx_cov {
337
338 input clk CLOCK verilog_node "`NCU.gclk";
339
340 input [5:0] io_buf_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.iobuf_head_ptr";
341 input io_buf_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU.iobuf_rden";
342
343 input [5:0] mondo_data_tbl_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mondo_data_addr_p0";
344 input [5:0] mondo_data_tbl_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mondo_data_addr_p1";
345 input mondo_data0_tbl_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mondo_data0_wr";
346 input mondo_data1_tbl_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mondo_data1_wr";
347 input mondo_data_tbl_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU_C2IFC.cpu_mondo_acc";
348
349
350 input [4:0] cpu_buf_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpubuf_tail_ptr";
351 input cpu_buf_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpubuf_wr";
352
353 input [4:0] int_buf_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intbuf_head_ptr";
354 input [4:0] int_buf_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intbuf_tail_ptr";
355 input int_buf_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intbuf_wr";
356 //input int_buf_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intbuf_rd_en";
357 input int_buf_rd_sel INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CFC.intbuf_head_inc";
358
359}
360interface ncu_ras_cov {
361
362 input clk CLOCK verilog_node "`NCU.iol2clk";
363 input ncu_rst_fatal_error INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_rst_fatal_error";
364
365 input [3:0] siisyn INPUT_EDGE INPUT_SKEW verilog_node "{`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_siisyn[63], `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_siisyn[58:56]}";
366 input [10:0] ncusyn INPUT_EDGE INPUT_SKEW verilog_node "{`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_ncusyn[63:58], `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_ncusyn[55:51]}";
367
368 input [42:0] ncu_ras_esr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasesr";
369 input [42:0] ncu_ras_ele INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasele";
370 input [42:0] ncu_ras_eie INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.raseie";
371 input [42:0] ncu_ras_fee INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasfee";
372 input [5:0] ncu_ras_steering INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.ras_err_steering";
373 input [42:0] raserr_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.raserr_in";
374 input siisyn_v INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.siisyn_v";
375 input rasesr_v INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasesr_v";
376 input rasper_v INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasper_v";
377 input c2i_packet_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.c2i_packet_vld";
378
379 input dmu_ncu_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_ctag_ue";
380 input dmu_ncu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_ctag_ce";
381 input dmu_ncu_d_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_d_pe";
382 input dmu_ncu_siicr_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_siicr_pe";
383 input dmu_ncu_ncucr_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_ncucr_pe";
384 input dmu_ncu_ie INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_ie";
385 input niu_ncu_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_ctag_ue";
386 input niu_ncu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_ctag_ce";
387 input niu_ncu_d_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_d_pe";
388 input sii_ncu_niua_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_niua_pe";
389 input sii_ncu_niuctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_niuctag_ue";
390 input sii_ncu_niuctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_niuctag_ce";
391 input sii_ncu_niud_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_niud_pe";
392 input sii_ncu_dmua_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_dmua_pe";
393 input sii_ncu_dmuctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_dmuctag_ue";
394 input sii_ncu_dmuctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_dmuctag_ce";
395 input sii_ncu_dmud_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_dmud_pe";
396 input sio_ncu_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sio_ncu_ctag_ue";
397 input sio_ncu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sio_ncu_ctag_ce";
398// input sio_ncu_d_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sio_ncu_d_pe";
399.for($b=0; $b<4; $b++){
400 input mcu${b}_ncu_ecc INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_ecc";
401 input mcu${b}_ncu_fbr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_fbr";
402.}
403 input ncu_dmu_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_ctag_uei";
404 input ncu_dmu_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_ctag_cei";
405 input ncu_dmu_d_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_d_pei";
406 input ncu_dmu_siicr_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_siicr_pei";
407 input ncu_dmu_ncucr_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_ncucr_pei";
408 input ncu_dmu_iei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_iei";
409 input ncu_niu_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_ctag_uei";
410 input ncu_niu_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_ctag_cei";
411 input ncu_niu_d_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_d_pei";
412 input ncu_sii_niua_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_niua_pei";
413 input ncu_sii_niuctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_niuctag_uei";
414 input ncu_sii_niuctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_niuctag_cei";
415 input ncu_sii_niud_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_niud_pei";
416 input ncu_sii_dmua_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_dmua_pei";
417 input ncu_sii_dmuctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_dmuctag_uei";
418 input ncu_sii_dmuctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_dmuctag_cei";
419 input ncu_sii_dmud_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_dmud_pei";
420 input ncu_sio_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sio_ctag_uei";
421 input ncu_sio_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sio_ctag_cei";
422 input ncu_sio_d_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sio_d_pei";
423.for($b=0; $b<4; $b++){
424 input ncu_mcu${b}_ecci INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_ecci";
425 input ncu_mcu${b}_fbri INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_fbri";
426.}
427 input pio_hdr_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.pio_hdr_vld";
428 input mondo_hdr_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.mondo_hdr_vld";
429 input ncuctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.hdrctag_ce";
430 input ncuctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.hdrctag_ue";
431 input dperr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.dperr";
432 input pldvld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.pldvld[0]";
433 input c2i_rd_intman INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.c2i_rd_intman";
434 input io_rd_intman_d2 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.io_rd_intman_d2";
435 input intman_pe_n INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.intman_pe_n";
436}
437// ******************************************************************
438// Interface for FC coverage Objects
439// ******************************************************************
440
441interface cpx_to_ncu_fifo_cpu_buf {
442
443 input wrclk CLOCK verilog_node "`NCU.ncu_cpu_buf_rf_cust.wrclk";
444 input rdclk INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.rdclk";
445 input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.wr_en";
446 input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.rd_en";
447 input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.wr_adr";
448 input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.rd_adr";
449}
450
451interface ncu_to_cpx_fifo_iobuf {
452
453 input rdclk CLOCK verilog_node "`NCU.ncu_iobuf0_rf_cust.rdclk";
454 input wrclk INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.wrclk";
455 input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.wr_en";
456 input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.rd_en";
457 input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.wr_adr";
458 input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.rd_adr";
459}
460
461interface ncu_to_cpx_fifo_intbuf {
462
463 input rdclk CLOCK verilog_node "`NCU.ncu_intbuf_rf_cust.rdclk";
464 input wrclk INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.wrclk";
465 input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.wr_en";
466 input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.rd_en";
467 input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.wr_adr";
468 input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.rd_adr";
469}
470
471
472// ******************************************************************
473
474
475#endif
Full OpenSPARC design & verification tarball including full HDL.