Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / siu / siu_l2intf_ob_cmd_sample.vrhpal

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// 
// OpenSPARC T2 Processor File: siu_l2intf_ob_cmd_sample.vrhpal
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#inc "siu_cov_inc.pal";

#ifndef SIU_INTF_COV
. for ($bank=0; $bank<8; $bank++)
. {
    sample siu_l2intf_bank${bank}_ob_cmd_sample_this (this_l2${bank}_ob_cmd)
                                     // <6:4>=O-P-S; 
	   		             // <3:0>= 0001->RDD; 0000->WR8; 0000->WRI
    {
      state DMU_ob_RDD_ord_npt	       ( 7'b1010001 );
      state DMU_ob_WR8_ord_pst         ( 7'b1110000 );
      state DMU_ob_WRI_ord_pst         ( 7'b1110000 );

      state NIU_ob_RDD_ord_npt         ( 7'b1000001 );
      state NIU_ob_RDD_byp_npt         ( 7'b0000001 );

      state NIU_ob_WRI_ord_npt         ( 7'b1000000 );
      state NIU_ob_WRI_byp_npt         ( 7'b0000000 );

      state NIU_ob_WRI_ord_pst         ( 7'b1100000 );
      state NIU_ob_WRI_byp_pst         ( 7'b0100000 );
      cov_weight = 0;
    }

    sample siu_l2intf_bank${bank}_ob_cmd_sample_last (last_l2${bank}_ob_cmd)
    {
      state DMU_ob_RDD_ord_npt_last    ( 7'b1010001 ) if (l2${bank}_ob_back_to_back==1'b1);
      state DMU_ob_WR8_ord_pst_last    ( 7'b1110000 ) if (l2${bank}_ob_back_to_back==1'b1);
      state DMU_ob_WRI_ord_pst_last    ( 7'b1110000 ) if (l2${bank}_ob_back_to_back==1'b1);

      state NIU_ob_RDD_ord_npt_last    ( 7'b1000001 ) if (l2${bank}_ob_back_to_back==1'b1);
      state NIU_ob_RDD_byp_npt_last    ( 7'b0000001 ) if (l2${bank}_ob_back_to_back==1'b1);

      state NIU_ob_WRI_ord_npt_last    ( 7'b1000000 ) if (l2${bank}_ob_back_to_back==1'b1);
      state NIU_ob_WRI_byp_npt_last    ( 7'b0000000 ) if (l2${bank}_ob_back_to_back==1'b1);

      state NIU_ob_WRI_ord_pst_last    ( 7'b1100000 ) if (l2${bank}_ob_back_to_back==1'b1);
      state NIU_ob_WRI_byp_pst_last    ( 7'b0100000 ) if (l2${bank}_ob_back_to_back==1'b1);
      
      cov_weight = 0;

    }

  cross l2siu_intf_bank${bank}_ob_cross ( siu_l2intf_bank${bank}_ob_cmd_sample_last, siu_l2intf_bank${bank}_ob_cmd_sample_this);

. }

#else
// FC
. for ($bank=0; $bank<8; $bank++)
. {
    sample siu_l2intf_bank${bank}_ob_cmd_sample_this (this_l2${bank}_ob_cmd)
                                     // <6:4>=O-P-S;
                                     // <3:0>= 0001->RDD; 0000->WR8; 0000->WRI
    {
      state DMU_ob_RDD_ord_npt         ( 7'b1010001 );
      state DMU_ob_WR8_ord_pst         ( 7'b1110000 );
      state DMU_ob_WRI_ord_pst         ( 7'b1110000 );

      state NIU_ob_RDD_byp_npt         ( 7'b0000001 );
      state NIU_ob_WRI_ord_npt         ( 7'b1000000 );
      state NIU_ob_WRI_byp_pst         ( 7'b0100000 );
    }

    sample siu_l2intf_bank${bank}_ob_cmd_sample_last (last_l2${bank}_ob_cmd)
    {
      state DMU_ob_RDD_ord_npt_last    ( 7'b1010001 ) if (l2${bank}_ob_back_to_back==1'b1);
      state DMU_ob_WR8_ord_pst_last    ( 7'b1110000 ) if (l2${bank}_ob_back_to_back==1'b1);
      state DMU_ob_WRI_ord_pst_last    ( 7'b1110000 ) if (l2${bank}_ob_back_to_back==1'b1);

      state NIU_ob_RDD_byp_npt_last    ( 7'b0000001 ) if (l2${bank}_ob_back_to_back==1'b1);
      state NIU_ob_WRI_ord_npt_last    ( 7'b1000000 ) if (l2${bank}_ob_back_to_back==1'b1);
      state NIU_ob_WRI_byp_pst_last    ( 7'b0100000 ) if (l2${bank}_ob_back_to_back==1'b1);

      cov_weight = 0;

    }
. }

  cross l2siu_intf_bank0_ob_cross ( siu_l2intf_bank0_ob_cmd_sample_last, siu_l2intf_bank0_ob_cmd_sample_this);

#endif