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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_cxint_chkr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ncu_cxint_chkr ; | |
36 | ||
37 | reg ncu_cxint_check_off; | |
38 | reg ncu_cxint_core_only; | |
39 | initial begin // { | |
40 | @(posedge `SYSTEMCLOCK) ; | |
41 | if ($test$plusargs("ncu_cxint_check_off")) begin // { | |
42 | ncu_cxint_check_off <= 1; | |
43 | `PR_ALWAYS("ncu_cxint", `ALWAYS, "NCU Cross-thread interrupt Checker is OFF"); | |
44 | end // } | |
45 | else begin // { | |
46 | ncu_cxint_check_off <= 0; | |
47 | ||
48 | if ($test$plusargs("ncu_cxint_core_only")) begin // { | |
49 | ncu_cxint_core_only <= 1; | |
50 | `PR_ALWAYS("ncu_cxint", `ALWAYS, "Checking for CORE-ONLY interrupts. IO interrupts will F a i l"); | |
51 | end // } | |
52 | else begin // { | |
53 | ncu_cxint_core_only <= 0; | |
54 | `PR_ALWAYS("ncu_cxint", `ALWAYS, "Checker allowing for IO interrupts. Spurious interrupts may be undetected"); | |
55 | end // } | |
56 | end // } | |
57 | end //} | |
58 | ||
59 | // Keep core-only values in bit vector | |
60 | // If ncu_cxint_core_only is set, check ALL vectors, | |
61 | // otherwise check only if return vector is set | |
62 | ||
63 | ||
64 | /* 0in create_wire -module cpu -var cxiint_resetpulse -width 1*/ | |
65 | /* 0in create_assign -module cpu -var_out cxiint_resetpulse | |
66 | -var $0in_rising_edge(`TOP.flush_reset_complete, `CPU.ncu.l2clk) | |
67 | */ | |
68 | ||
69 | /* 0in create_wire -module cpu -var cxiint_intreq -width 1*/ | |
70 | /* 0in create_assign -module cpu -var_out cxiint_intreq | |
71 | -var ($0in_delay(pcx_ncu_data_rdy_px1,1, `CPU.ncu.l2clk) & | |
72 | (pcx_ncu_data_px2[129:124] == 'b100001) & | |
73 | (pcx_ncu_data_px2[103:96] == 8'h90) & | |
74 | (pcx_ncu_data_px2[89:64] == {8'h73,18'h0})) | |
75 | */ | |
76 | ||
77 | /* 0in create_wire -module cpu -var cxiint_intret -width 1*/ | |
78 | /* 0in create_assign -module cpu -var_out cxiint_intret | |
79 | -var ($0in_delay(|ncu_cpx_req_cq,1,`CPU.ncu.l2clk) & | |
80 | (ncu_cpx_data_ca[145:141]== 'b10111) & | |
81 | (ncu_cpx_data_ca[15:14] == 2'b0) & | |
82 | ((cxiint_coreval[ncu_cpx_data_ca[5:0]] == 1'b1) | | |
83 | ncu_cxint_chkr.ncu_cxint_core_only)) | |
84 | */ | |
85 | /* 0in create_wire -module cpu -var cxiint_coreval -width 64*/ | |
86 | /* 0in create_assign -module cpu -var_out cxiint_coreval | |
87 | -var ($0in_delay(((`TOP.in_reset) ? 64'b0 : | |
88 | (cxiint_intreq ? | |
89 | (cxiint_coreval|(1'b1<<pcx_ncu_data_px2[5:0])) | |
90 | : cxiint_coreval)),1, | |
91 | (`CPU.ncu.l2clk&(cxiint_intreq|`TOP.in_reset)))) | |
92 | */ | |
93 | ||
94 | /* 0in create_wire -module cpu -var cxiint_reqcnt -width 10*/ | |
95 | /* 0in create_assign -module cpu -var_out cxiint_reqcnt | |
96 | -var ($0in_delay(((`TOP.in_reset) ? 10'b0 : | |
97 | (cxiint_intreq ? cxiint_reqcnt+1 : cxiint_reqcnt)),1, | |
98 | (`CPU.ncu.l2clk&(cxiint_intreq|`TOP.in_reset)))) | |
99 | ||
100 | */ | |
101 | /* 0in create_wire -module cpu -var cxiint_retcnt -width 10*/ | |
102 | /* 0in create_assign -module cpu -var_out cxiint_retcnt | |
103 | -var ($0in_delay(((`TOP.in_reset) ? 10'b0 : | |
104 | (cxiint_intret ? cxiint_retcnt+1 : cxiint_retcnt)),1, | |
105 | (`CPU.ncu.l2clk&(cxiint_intret|`TOP.in_reset)))) | |
106 | ||
107 | */ | |
108 | ||
109 | /* 0in custom -module cpu -name ncu_cxint_final | |
110 | -fire (cxiint_reqcnt !== cxiint_retcnt) | |
111 | -active $0in_rising_edge(`TOP.sim_status[`ASM_PASS]& ~ncu_cxint_chkr.ncu_cxint_check_off) | |
112 | -message ("End of Asm Diag there are pending cross-core interrupts from NCU (Req %d, Ret %d)",cxiint_reqcnt, cxiint_retcnt) | |
113 | */ | |
114 | // Make sure that all cross-thread interrupts sent to NCU are | |
115 | // reflected back from NCU | |
116 | // Checker should allow non cross-thread interrupts through | |
117 | // without checking .. | |
118 | // | |
119 | // 0in disable_checker -name ncu_cxint* ncu_cxint_check_off | |
120 | ||
121 | /* 0in fifo -module cpu -name ncu_cxint | |
122 | -enq (cxiint_intreq) | |
123 | -enq_data (pcx_ncu_data_px2[17:0]&16'h3f3f) | |
124 | -deq (cxiint_intret) | |
125 | -deq_data (ncu_cpx_data_ca[17:0]) | |
126 | -clock `CPU.ncu.l2clk | |
127 | -depth 66 | |
128 | -active (~ncu_cxint_chkr.ncu_cxint_check_off) | |
129 | -message ("Mismatch in cross-thread interrupts sent/returned from NCU. CPU vectors are 0x%h", cxiint_coreval) | |
130 | */ | |
131 | ||
132 | endmodule |