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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / checkers / siu / siu_wb_chkr.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: siu_wb_chkr.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifdef IOS
36`define TB_TOP tb_top
37`define TB_RST tb_top.reset
38`else
39`ifdef FC_BENCH
40`define TB_TOP tb_top
41`define TB_RST tb_top.reset
42`else
43`define TB_TOP siu_top
44`define TB_RST siu_top.reset
45`endif
46`endif
47
48module siu_wb_chkr();
49
50// set this to -constraint to constrain input signals to SIU
51`define SIU_CONSTRAINT
52// set this to -constraint to constrain input signals to NIU
53`define NIU_CONSTRAINT
54
55 // 0in set_clock -default iol2clk -module sii
56 // 0in set_clock -default iol2clk -module sio
57
58
59///////////////////////////////////////////////////////////////////////////////
60// These signals can be used to disable certain 0-In checkers at runtime,
61// so that testcases forcing interface errors don't die with checker firings.
62///////////////////////////////////////////////////////////////////////////////
63reg disable_siu_checks;
64
65initial begin
66 @(posedge `TB_TOP.cpu.sii.iol2clk) ;
67 if ($test$plusargs("siu_0in_wb_chk_off"))
68 disable_siu_checks <= 1;
69 else
70 disable_siu_checks <= 0;
71end
72
73// 0in disable_checker -name *sii* disable_siu_checks
74// 0in disable_checker -name *sio* disable_siu_checks
75
76
77wire niu_req;
78reg niu_req_d, niu_req_dd, niu_req_ddd, niu_req_dddd;
79
80assign niu_req = `TB_TOP.cpu.niu_sii_hdr_vld;
81always @(posedge `TB_TOP.cpu.sii.iol2clk) begin
82 niu_req_d <= #2 niu_req;
83 niu_req_dd <= #2 niu_req_d;
84 niu_req_ddd <= #2 niu_req_dd;
85 niu_req_dddd <= #2 niu_req_ddd;
86
87end
88
89reg ipdodq0_h_wr_en_d1,ipdodq0_l_wr_en_d1,ipdbdq0_h_wr_en_d1,ipdbdq0_l_wr_en_d1;
90reg ipdodq1_h_wr_en_d1,ipdodq1_l_wr_en_d1,ipdbdq1_h_wr_en_d1,ipdbdq1_l_wr_en_d1;
91reg ipdodq0_h_rd_en_d1,ipdodq0_l_rd_en_d1,ipdbdq0_h_rd_en_d1,ipdbdq0_l_rd_en_d1;
92reg ipdodq1_h_rd_en_d1,ipdodq1_l_rd_en_d1,ipdbdq1_h_rd_en_d1,ipdbdq1_l_rd_en_d1;
93reg [`SII_IPD_DATA_RF_ADDRWIDTH-1:0] ipdodq0_h_wr_adr_d1,ipdodq0_l_wr_adr_d1,ipdbdq0_h_wr_adr_d1,ipdbdq0_l_wr_adr_d1;
94reg [`SII_IPD_DATA_RF_ADDRWIDTH-1:0] ipdodq1_h_wr_adr_d1,ipdodq1_l_wr_adr_d1,ipdbdq1_h_wr_adr_d1,ipdbdq1_l_wr_adr_d1;
95reg [`SII_IPD_DATA_RF_ADDRWIDTH-1:0] ipdodq0_h_rd_adr_d1,ipdodq0_l_rd_adr_d1,ipdbdq0_h_rd_adr_d1,ipdbdq0_l_rd_adr_d1;
96reg [`SII_IPD_DATA_RF_ADDRWIDTH-1:0] ipdodq1_h_rd_adr_d1,ipdodq1_l_rd_adr_d1,ipdbdq1_h_rd_adr_d1,ipdbdq1_l_rd_adr_d1;
97
98reg ipdohq0_wr_en_d1,ipdbhq0_wr_en_d1,ipdohq1_wr_en_d1,ipdbhq1_wr_en_d1;
99reg ipdohq0_rd_en_d1,ipdbhq0_rd_en_d1,ipdohq1_rd_en_d1,ipdbhq1_rd_en_d1;
100
101reg [`SII_IPD_HDR_RF_ADDRWIDTH-1:0] ipdohq0_wr_adr_d1,ipdbhq0_wr_adr_d1,ipdohq1_wr_adr_d1,ipdbhq1_wr_adr_d1;
102reg [`SII_IPD_HDR_RF_ADDRWIDTH-1:0] ipdohq0_rd_adr_d1,ipdbhq0_rd_adr_d1,ipdohq1_rd_adr_d1,ipdbhq1_rd_adr_d1;
103
104
105
106always @(posedge `TB_TOP.cpu.sii.iol2clk) begin
107 ipdodq0_h_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdodq0_wr_en;
108 ipdodq0_h_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdodq0_wr_addr[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
109 ipdodq0_l_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdodq0_wr_en;
110 ipdodq0_l_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdodq0_wr_addr[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
111 ipdbdq0_h_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbdq0_wr_en;
112 ipdbdq0_h_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbdq0_wr_addr[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
113 ipdbdq0_l_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbdq0_wr_en;
114 ipdbdq0_l_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbdq0_wr_addr[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
115
116 ipdodq1_h_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdodq1_wr_en;
117 ipdodq1_h_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdodq1_wr_addr[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
118 ipdodq1_l_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdodq1_wr_en;
119 ipdodq1_l_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdodq1_wr_addr[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
120 ipdbdq1_h_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbdq1_wr_en;
121 ipdbdq1_h_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbdq1_wr_addr[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
122 ipdbdq1_l_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbdq1_wr_en;
123 ipdbdq1_l_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbdq1_wr_addr[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
124
125 ipdohq0_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdohq0_wr_en;
126 ipdohq0_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdohq0_wr_addr[`SII_IPD_HDR_RF_ADDRWIDTH-1:0];
127 ipdbhq0_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbhq0_wr_en;
128 ipdbhq0_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbhq0_wr_addr[`SII_IPD_HDR_RF_ADDRWIDTH-1:0];
129
130 ipdohq1_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdohq1_wr_en;
131 ipdohq1_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdohq1_wr_addr[`SII_IPD_HDR_RF_ADDRWIDTH-1:0];
132 ipdbhq1_wr_en_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbhq1_wr_en;
133 ipdbhq1_wr_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcs_ipdbhq1_wr_addr[`SII_IPD_HDR_RF_ADDRWIDTH-1:0];
134
135 end
136
137
138always @(posedge `TB_TOP.cpu.sii.l2clk) begin
139 ipdodq0_h_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdodq0_rd_en_m;
140 ipdodq0_h_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdodq0_rd_addr_m[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
141 ipdodq0_l_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdodq0_rd_en_m;
142 ipdodq0_l_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdodq0_rd_addr_m[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
143 ipdbdq0_h_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbdq0_rd_en_m;
144 ipdbdq0_h_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbdq0_rd_addr_m[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
145 ipdbdq0_l_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbdq0_rd_en_m;
146 ipdbdq0_l_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbdq0_rd_addr_m[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
147
148 ipdodq1_h_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdodq1_rd_en_m;
149 ipdodq1_h_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdodq1_rd_addr_m[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
150 ipdodq1_l_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdodq1_rd_en_m;
151 ipdodq1_l_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdodq1_rd_addr_m[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
152 ipdbdq1_h_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbdq1_rd_en_m;
153 ipdbdq1_h_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbdq1_rd_addr_m[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
154 ipdbdq1_l_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbdq1_rd_en_m;
155 ipdbdq1_l_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbdq1_rd_addr_m[`SII_IPD_DATA_RF_ADDRWIDTH-1:0];
156
157
158 ipdohq0_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdohq0_rd_en_m;
159 ipdohq0_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdohq0_rd_addr_m[`SII_IPD_HDR_RF_ADDRWIDTH-1:0];
160 ipdbhq0_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbhq0_rd_en_m;
161 ipdbhq0_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbhq0_rd_addr_m[`SII_IPD_HDR_RF_ADDRWIDTH-1:0];
162
163 ipdohq1_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdohq1_rd_en_m;
164 ipdohq1_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdohq1_rd_addr_m[`SII_IPD_HDR_RF_ADDRWIDTH-1:0];
165 ipdbhq1_rd_en_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbhq1_rd_en_m;
166 ipdbhq1_rd_adr_d1 <= #2 `TB_TOP.cpu.sii.ipcc_ipdbhq1_rd_addr_m[`SII_IPD_HDR_RF_ADDRWIDTH-1:0];
167end
168
169 /* 0in custom
170 -fire (ipdodq0_h_rd_en_d1 && ipdodq0_h_wr_en_d1 && (ipdodq0_h_rd_adr_d1 === ipdodq0_h_wr_adr_d1))
171 -message "ipdodq0_h FIFO overrun: rd and wr pointer valid on same addr"
172 -clock `TB_TOP.cpu.sii.l2clk
173 -name sii_ipdodq0_h_ptr_overrun
174 */
175
176
177 /* 0in custom
178 -fire (ipdodq0_l_rd_en_d1 && ipdodq0_l_wr_en_d1 && (ipdodq0_l_rd_adr_d1 === ipdodq0_l_wr_adr_d1))
179 -message "ipdodq0_l FIFO overrun: rd and wr pointer valid on same addr"
180 -clock `TB_TOP.cpu.sii.l2clk
181 -name sii_ipdodq0_l_ptr_overrun
182 */
183
184 /* 0in custom
185 -fire (ipdbdq0_h_rd_en_d1 && ipdbdq0_h_wr_en_d1 && (ipdbdq0_h_rd_adr_d1 === ipdbdq0_h_wr_adr_d1))
186 -message "ipdbdq0_h FIFO overrun: rd and wr pointer valid on same addr"
187 -clock `TB_TOP.cpu.sii.l2clk
188 -name sii_ipdbdq0_h_ptr_overrun
189 */
190
191
192 /* 0in custom
193 -fire (ipdbdq0_l_rd_en_d1 && ipdbdq0_l_wr_en_d1 && (ipdbdq0_l_rd_adr_d1 === ipdbdq0_l_wr_adr_d1))
194 -message "ipdbdq0_l FIFO overrun: rd and wr pointer valid on same addr"
195 -clock `TB_TOP.cpu.sii.l2clk
196 -name sii_ipdbdq0_l_ptr_overrun
197 */
198
199
200 /* 0in custom
201 -fire (ipdodq1_h_rd_en_d1 && ipdodq1_h_wr_en_d1 && (ipdodq1_h_rd_adr_d1 === ipdodq1_h_wr_adr_d1))
202 -message "ipdodq1_h FIFO overrun: rd and wr pointer valid on same addr"
203 -clock `TB_TOP.cpu.sii.l2clk
204 -name sii_ipdodq1_h_ptr_overrun
205 */
206
207
208 /* 0in custom
209 -fire (ipdodq1_l_rd_en_d1 && ipdodq1_l_wr_en_d1 && (ipdodq1_l_rd_adr_d1 === ipdodq1_l_wr_adr_d1))
210 -message "ipdodq1_l FIFO overrun: rd and wr pointer valid on same addr"
211 -clock `TB_TOP.cpu.sii.l2clk
212 -name sii_ipdodq1_l_ptr_overrun
213 */
214
215 /* 0in custom
216 -fire (ipdbdq1_h_rd_en_d1 && ipdbdq1_h_wr_en_d1 && (ipdbdq1_h_rd_adr_d1 === ipdbdq1_h_wr_adr_d1))
217 -message "ipdbdq1_h FIFO overrun: rd and wr pointer valid on same addr"
218 -clock `TB_TOP.cpu.sii.l2clk
219 -name sii_ipdbdq1_h_ptr_overrun
220 */
221
222
223 /* 0in custom
224 -fire (ipdbdq1_l_rd_en_d1 && ipdbdq1_l_wr_en_d1 && (ipdbdq1_l_rd_adr_d1 === ipdbdq1_l_wr_adr_d1))
225 -message "ipdbdq1_l FIFO overrun: rd and wr pointer valid on same addr"
226 -clock `TB_TOP.cpu.sii.l2clk
227 -name sii_ipdbdq1_l_ptr_overrun
228 */
229
230
231 /* 0in custom
232 -fire (ipdohq0_rd_en_d1 && ipdohq0_wr_en_d1 && (ipdohq0_rd_adr_d1 === ipdohq0_wr_adr_d1))
233 -message "ipdohq0 FIFO overrun: rd and wr pointer valid on same addr"
234 -clock `TB_TOP.cpu.sii.l2clk
235 -name sii_ipdohq0_ptr_overrun
236 */
237
238
239 /* 0in custom
240 -fire (ipdohq1_rd_en_d1 && ipdohq1_wr_en_d1 && (ipdohq1_rd_adr_d1 === ipdohq1_wr_adr_d1))
241 -message "ipdohq1 FIFO overrun: rd and wr pointer valid on same addr"
242 -clock `TB_TOP.cpu.sii.l2clk
243 -name sii_ipdohq1_ptr_overrun
244 */
245
246
247 /* 0in custom
248 -fire (ipdbhq0_rd_en_d1 && ipdbhq0_wr_en_d1 && (ipdbhq0_rd_adr_d1 === ipdbhq0_wr_adr_d1))
249 -message "ipdbhq0 FIFO overrun: rd and wr pointer valid on same addr"
250 -clock `TB_TOP.cpu.sii.l2clk
251 -name sii_ipdbhq0_ptr_overrun
252 */
253
254
255 /* 0in custom
256 -fire (ipdbhq1_rd_en_d1 && ipdbhq1_wr_en_d1 && (ipdbhq1_rd_adr_d1 === ipdbhq1_wr_adr_d1))
257 -message "ipdbhq1 FIFO overrun: rd and wr pointer valid on same addr"
258 -clock `TB_TOP.cpu.sii.l2clk
259 -name sii_ipdbhq1_ptr_overrun
260 */
261
262
263
264
265
266wire dmu_req;
267assign dmu_req = `TB_TOP.cpu.dmu_sii_hdr_vld;
268
269 /* x0in
270 sequence -var cstate[6:0] -val 7'b0000100 7'b0001000 7'b0010000 7'b0100000 7'b1000000
271 -start ~ext_sii_datareq16_r
272 -match_by_cycle
273 -module sii_ipcs_ctl -name sii_niu_ipcs_fsm_wri
274 */
275
276 /* x0in
277 sequence -var cstate[6:0] -val 7'b0010000 7'b0100000 7'b1000000
278 -match_by_cycle
279 -module sii_ipcs_ctl -name sii_ipcs_fsm_wri
280 */
281
282
283
284 /* x0in
285 state -var cstate[6:0] -val 7'b0000001 -next 7'b0000001 7'b0000010 7'b0000100
286 -match_by_cycle
287 -module sii_ipcs_ctl
288 -name sii_ipcs_fsm_start
289 */
290
291 /* x0in
292 state -var cstate[6:0] -val 7'b0000001 -next 7'b0000100
293 -match_by_cycle
294 -cond (ext_sii_hdr_vld & ext_sii_datareq)
295 -module sii_ipcs_ctl
296 -name sii_ipcs_fsm_start_hdr_payld
297 */
298
299 /* x0in
300 state -var cstate[6:0]
301 -val 7'b0000010
302 -next 7'b0000001 7'b0000010 7'b0000100
303 -match_by_cycle
304 -module sii_ipcs_ctl
305 -name sii_ipcs_fsm_hdr
306 */
307
308 /* x0in
309 state -var cstate[6:0]
310 -val 7'b0000100
311 -next 7'b0000001 7'b0001000
312 -match_by_cycle
313 -module sii_ipcs_ctl
314 -name sii_ipcs_fsm_hdrpld
315 */
316
317 /* x0in
318 state -var cstate[6:0]
319 -val 7'b0001000
320 -next 7'b0000001 7'b0000010 7'b0000100 7'b0010000
321 -match_by_cycle
322 -module sii_ipcs_ctl
323 -name sii_ipcs_fsm_data1
324 */
325
326
327 /* x0in
328 state -var cstate[6:0]
329 -val 7'b0010000
330 -next 7'b0000001 7'b0100000
331 -match_by_cycle
332 -module sii_ipcs_ctl
333 -name sii_ipcs_fsm_data2
334 */
335
336 /* x0in
337 state -var cstate[6:0]
338 -val 7'b0100000
339 -next 7'b0000001 7'b1000000
340 -match_by_cycle
341 -module sii_ipcs_ctl
342 -name sii_ipcs_fsm_data3
343 */
344
345 /* x0in
346 state -var cstate[6:0]
347 -val 7'b1000000
348 -next 7'b0000001 7'b0000010 7'b0000100
349 -match_by_cycle
350 -module sii_ipcs_ctl
351 -name sii_ipcs_fsm_data4
352 */
353
354
355
356 /* x0in
357 state -var cstate[6:0] -is_not -val 7'b0000001 -next 7'b0000100
358 -cond (ext_sii_hdr_vld & ~ext_sii_datareq)
359 -module sii_ipcs_ctl
360 -name sii_ipcs_fsm_read_not_start_hdrpld
361 */
362
363
364 /* x0in
365 state -var cstate[6:0] -is_not -val 7'b0000001 -next 7'b0000010
366 -cond (ext_sii_hdr_vld & ext_sii_datareq)
367 -module sii_ipcs_ctl
368 -name sii_ipcs_fsm_write_not_start_hdr
369 */
370
371
372 /* x0in
373 one_hot -var cstate
374 -module sii_ipcs_ctl
375 -name sii_ipcs_fsm_one_hot
376 */
377
378
379 /* 0in
380 bits_on -var nstate -max 2
381 -module sii_ipcs_ctl
382 -reset `TB_RST
383 -name sii_ipcs_nstate
384 */
385
386 /* 0in
387 bits_on -var {arc_start_hdr, arc_start_hdrpayld, arc_hdr_hdrpayld, arc_hdr_hdr, arc_hdrpayld_data1, arc_data1_hdrpayld, arc_data1_hdr, arc_data1_data2, arc_data2_data3, arc_data3_data4, arc_data4_hdr, arc_data4_hdrpayld}
388 -max 1
389 -module sii_ipcs_ctl
390 -reset `TB_RST
391 -name sii_ipcs_arcs
392 */
393
394 /* 0in decoder
395 -in ipcc_ipcs_or_raddr
396 -out {or_clr_v15, or_clr_v14, or_clr_v13, or_clr_v12,
397 or_clr_v11, or_clr_v10, or_clr_v9, or_clr_v8,
398 or_clr_v7, or_clr_v6, or_clr_v5, or_clr_v4,
399 or_clr_v3, or_clr_v2, or_clr_v1, or_clr_v0}
400 -active ipcc_ipcs_or_go
401 -module sii_ipcs_ctl
402 -reset `TB_RST
403 -name sii_ipcs_ctl_decoder_ord
404 */
405
406 /* 0in decoder
407 -in ipcc_ipcs_by_raddr
408 -out {by_clr_v15, by_clr_v14, by_clr_v13, by_clr_v12,
409 by_clr_v11, by_clr_v10, by_clr_v9, by_clr_v8,
410 by_clr_v7, by_clr_v6, by_clr_v5, by_clr_v4,
411 by_clr_v3, by_clr_v2, by_clr_v1, by_clr_v0}
412 -active ipcc_ipcs_by_go
413 -module sii_ipcs_ctl
414 -reset `TB_RST
415 -name sii_ipcs_ctl_decoder_byp
416 */
417
418 /* 0in timeout
419 -var cstate[6:0]
420 -val 50
421 -active ((cstate !== 7'b0000001) && (cstate !== 7'b0000010))
422 -module sii_ipcs_ctl
423 -clock iol2clk
424 -reset `TB_RST
425 -name sii_ipcs_ctl_fsm_to
426 */
427
428 /* x0in mux
429 -in ipcs_ipdohq_wr_addr last_or_wr_r
430 -out last_or_wr_l[3:0]
431 -select (ipcs_ipdohq_wr_en && w_r)
432 -binary
433 -module sii_ipcs_ctl
434 -name sii_ipcs_ctl_mux1
435 */
436
437 /* x0in mux
438 -in gt_wrptr[3:0] lt_wrptr[3:0]
439 -out youngest_match[3:0]
440 -select lt_wrptr[4]
441 -binary
442 -module sii_ipcs_ctl
443 -name sii_ipcs_ctl_mux2
444 */
445
446/*************************************************************************
447*
448* sii_ild_dp.sv
449*
450**************************************************************************/
451
452 /* 0in increment
453 -var ipcc_ipdohq1_rd_addr
454 -module sii_ipcc_ctl
455 -reset `TB_RST
456 -name sii_ipcc_inc
457 */
458
459
460 /* 0in arbiter
461 -req niu_or_go niu_by_go
462 -gnt gnt_r[1] gnt_r[0]
463 -round_robin
464 -no_simultaneous_req_gnt
465 -clock l2clk
466 -reset `TB_RST
467 -module sii_ipcc_ctl
468 -name sii_ipcc_arb1
469 */
470
471 /* 0in arbiter
472 -req dmu_or_go dmu_by_go
473 -gnt gnt_r[3] gnt_r[2]
474 -round_robin
475 -clock l2clk
476 -reset `TB_RST
477 -module sii_ipcc_ctl
478 -name sii_ipcc_arb2
479 */
480
481 /* 0in arbiter
482 -req (dmu_or_go | dmu_by_go) (niu_or_go | niu_by_go)
483 -gnt ((gnt_r[3]== 1'b1) | (gnt_r[2]== 1'b1)) ((gnt_r[1]== 1'b1) | (gnt_r[0]== 1'b1))
484 -no_simultaneous_req_gnt
485 -clock l2clk
486 -reset `TB_RST
487 -round_robin
488 -module sii_ipcc_ctl
489 -name sii_ipcc_arb3
490 */
491
492
493/*************************************************************************
494*
495* sii_ipcc - STATE_TRANSITION
496*
497**************************************************************************/
498
499`define START_ST 14'b00000000000001
500`define DEC_ST 14'b00000000000010
501`define ARB_ST 14'b00000000000100
502`define HDR_ST 14'b00000000001000
503`define HDRDLY_ST 14'b00000000010000
504`define DATA1_ST 14'b00000000100000
505`define DATA2_ST 14'b00000001000000
506`define DATA3_ST 14'b00000010000000
507`define DATA4_ST 14'b00000100000000
508`define DATA5_ST 14'b00001000000000
509`define DATA6_ST 14'b00010000000000
510`define DATA7_ST 14'b00100000000000
511`define DATA8_ST 14'b01000000000000
512`define RDDW_ST 14'b10000000000000
513
514`define START 0
515`define DEC 1
516`define ARB 2
517`define HDR 3
518`define HDRDLY 4
519`define DATA1 5
520`define DATA2 6
521`define DATA3 7
522`define DATA4 8
523`define DATA5 9
524`define DATA6 10
525`define DATA7 11
526`define DATA8 12
527`define RDDW 13
528
529
530/* 0in state_transition -var cstate -val `START_ST -next `DEC_ST -clock l2clk -reset `TB_RST -module sii_ipcc_ctl -name sii_start */
531
532/* 0in state_transition -var cstate -val `DEC_ST -next `ARB_ST `START_ST -clock l2clk -reset `TB_RST -match_by_cycle -module sii_ipcc_ctl -name sii_dec */
533
534/* 0in state_transition -var cstate -val `ARB_ST -next `HDR_ST `START_ST `ARB_ST -clock l2clk -reset `TB_RST -match_by_cycle -module sii_ipcc_ctl -name sii_arb */
535
536/* 0in state_transition -var cstate -val `HDR_ST -next `HDRDLY_ST -clock l2clk -reset `TB_RST -module sii_ipcc_ctl -name sii_hdr */
537
538/* 0in state_transition -var cstate -val `HDRDLY_ST -next `DATA1_ST `RDDW_ST `START_ST -clock l2clk -reset `TB_RST -match_by_cycle -module sii_ipcc_ctl -name sii_hdrdly */
539
540/* 0in state_transition -var cstate -val `RDDW_ST -next `START_ST -clock l2clk -reset `TB_RST -module sii_ipcc_ctl -name sii_rddw */
541
542/* 0in state_transition -var cstate -val `DATA1_ST -next `DATA2_ST `START_ST -clock l2clk -reset `TB_RST -match_by_cycle -module sii_ipcc_ctl -name sii_data1 */
543
544/* 0in state_transition -var cstate -val `DATA2_ST -next `DATA3_ST `START_ST -clock l2clk -reset `TB_RST -match_by_cycle -module sii_ipcc_ctl -name sii_data2 */
545
546/* 0in state_transition -var cstate -val `DATA3_ST -next `DATA4_ST -clock l2clk -reset `TB_RST -module sii_ipcc_ctl -name sii_data3 */
547
548/* 0in state_transition -var cstate -val `DATA4_ST -next `DATA5_ST -clock l2clk -reset `TB_RST -module sii_ipcc_ctl -name sii_data4 */
549
550/* 0in state_transition -var cstate -val `DATA5_ST -next `DATA6_ST -clock l2clk -reset `TB_RST -module sii_ipcc_ctl -name sii_data5 */
551
552/* 0in state_transition -var cstate -val `DATA6_ST -next `DATA7_ST -clock l2clk -reset `TB_RST -module sii_ipcc_ctl -name sii_data6 */
553
554/* 0in state_transition -var cstate -val `DATA7_ST -next `DATA8_ST -clock l2clk -reset `TB_RST -module sii_ipcc_ctl -name sii_data7 */
555
556/* 0in state_transition -var cstate -val `DATA8_ST -next `START_ST -clock l2clk -reset `TB_RST -module sii_ipcc_ctl -name sii_data8 */
557
558
559/*************************************************************************
560*
561* sii_ipcc - ipcc to ipcs pointers
562*
563**************************************************************************/
564
565
566/* 0in custom
567 -fire (($0in_rising_edge(ipcc_ipcs_dmu_or_ptr[0])) && ($0in_rising_edge(ipcc_ipcs_dmu_by_ptr[0])))
568 -clock l2clk
569 -reset `TB_RST
570 -message "ipcc to ipcs pointers: dmu_or[0] and dmu_by[0] pointer asserted at same time"
571 -module sii_ipcc_ctl
572 -name sii_update_dmu0
573*/
574
575/* 0in custom
576 -fire (($0in_rising_edge(ipcc_ipcs_dmu_or_ptr[1])) && ($0in_rising_edge(ipcc_ipcs_dmu_by_ptr[1])))
577 -clock l2clk
578 -reset `TB_RST
579 -message "ipcc to ipcs pointers: dmu_or[1] and dmu_by[1] pointer asserted at same time"
580 -module sii_ipcc_ctl
581 -name sii_update_dmu1
582*/
583
584/* 0in custom
585 -fire (($0in_rising_edge(ipcc_ipcs_dmu_or_ptr[2])) && ($0in_rising_edge(ipcc_ipcs_dmu_by_ptr[2])))
586 -clock l2clk
587 -reset `TB_RST
588 -message "ipcc to ipcs pointers: dmu_or[2] and dmu_by[2] pointer asserted at same time"
589 -module sii_ipcc_ctl
590 -name sii_update_dmu2
591*/
592
593/* 0in custom
594 -fire (($0in_rising_edge(ipcc_ipcs_dmu_or_ptr[3])) && ($0in_rising_edge(ipcc_ipcs_dmu_by_ptr[3])))
595 -clock l2clk
596 -reset `TB_RST
597 -message "ipcc to ipcs pointers: dmu_or[3] and dmu_by[3] pointer asserted at same time"
598 -module sii_ipcc_ctl
599 -name sii_update_dmu3
600*/
601
602/* 0in custom
603 -fire (($0in_rising_edge(ipcc_ipcs_niu_or_ptr[0])) && ($0in_rising_edge(ipcc_ipcs_niu_by_ptr[0])))
604 -clock l2clk
605 -reset `TB_RST
606 -message "ipcc to ipcs pointers: niu_or[0] and niu_by[0] pointer asserted at same time"
607 -module sii_ipcc_ctl
608 -name sii_update_niu0
609*/
610
611/* 0in custom
612 -fire (($0in_rising_edge(ipcc_ipcs_niu_or_ptr[1])) && ($0in_rising_edge(ipcc_ipcs_niu_by_ptr[1])))
613 -clock l2clk
614 -reset `TB_RST
615 -message "ipcc to ipcs pointers: niu_or[1] and niu_by[1] pointer asserted at same time"
616 -module sii_ipcc_ctl
617 -name sii_update_niu1
618*/
619
620/* 0in custom
621 -fire (($0in_rising_edge(ipcc_ipcs_niu_or_ptr[2])) && ($0in_rising_edge(ipcc_ipcs_niu_by_ptr[2])))
622 -clock l2clk
623 -reset `TB_RST
624 -message "ipcc to ipcs pointers: niu_or[2] and niu_by[2] pointer asserted at same time"
625 -module sii_ipcc_ctl
626 -name sii_update_niu2
627*/
628
629/* 0in custom
630 -fire (($0in_rising_edge(ipcc_ipcs_niu_or_ptr[3])) && ($0in_rising_edge(ipcc_ipcs_niu_by_ptr[3])))
631 -clock l2clk
632 -reset `TB_RST
633 -message "ipcc to ipcs pointers: niu_or[3] and niu_by[3] pointer asserted at same time"
634 -module sii_ipcc_ctl
635 -name sii_update_niu3
636*/
637
638
639/*************************************************************************
640*
641* sii_ipcc - WRM counter
642*
643**************************************************************************/
644
645/* 0in overflow
646 -var dmu_wrm_cnt_r[3:0]
647 -max 8
648 -clock l2clk
649 -reset `TB_RST
650 -module sii_ipcc_ctl
651 -name sii_ipcc_dmu_wrm_counter
652*/
653
654
655/* 0in overflow
656 -var dmu_or_cnt_r[4:0]
657 -min 0
658 -max 16
659 -clock l2clk
660 -reset `TB_RST
661 -module sii_ipcc_ctl
662 -name sii_ipcc_dmu_or_counter
663*/
664
665/* 0in overflow
666 -var dmu_by_cnt_r[4:0]
667 -min 0
668 -max 16
669 -clock l2clk
670 -reset `TB_RST
671 -module sii_ipcc_ctl
672 -name sii_ipcc_dmu_by_counter
673*/
674
675/* 0in overflow
676 -var niu_or_cnt_r[4:0]
677 -min 0
678 -max 16
679 -clock l2clk
680 -reset `TB_RST
681 -module sii_ipcc_ctl
682 -name sii_ipcc_niu_or_counter
683*/
684
685/* 0in overflow
686 -var niu_by_cnt_r[4:0]
687 -min 0
688 -max 16
689 -clock l2clk
690 -reset `TB_RST
691 -module sii_ipcc_ctl
692 -name sii_ipcc_niu_by_counter
693*/
694
695
696/*************************************************************************
697*
698* sii_ild_dp.sv
699*
700**************************************************************************/
701 // these should be checked in ilc module
702 /* 0in one_hot
703 -var ilc_ild_de_sel
704 -module sii_ild_dp
705 -clock l2clk
706 -reset `TB_RST
707 -name sii_ild_dp_onehot1
708 */
709
710/*************************************************************************
711*
712* sii_ilc_ctl.sv
713*
714**************************************************************************/
715 /* 0in mux
716 -in full_be0 full_be1 full_be2 full_be3
717 -out cur_be
718 -select hdr_rd_ptr_l
719 -binary
720 -module sii_ilc_ctl
721 -reset `TB_RST
722 -name sii_ilc_ctl_mux1
723 */
724
725/* 0in underflow
726 -var wrm_cnt_r[2:0]
727 -min 0
728 -clock l2clk
729 -module sii_ilc_ctl
730 -reset `TB_RST
731 -name sii_ilc_wrm_under_counter
732*/
733
734/* 0in arithmetic_overflow
735 -var wrm_cnt_l[2:0]
736 -val ((& wrm_cnt_r[2:0] && arc_data2_start ) ? 3'b000 : (wrm && cstate[`DATA2] && make_request) ? (wrm_cnt_r[2:0] + 3'b001) : wrm_cnt_r[2:0])
737 -clock l2clk
738 -reset `TB_RST
739 -module sii_ilc_ctl
740 -name sii_ilc_wrm_over_counter
741*/
742
743
744/* 0in underflow
745 -var sio_cnt_r[2:0]
746 -min 0
747 -clock l2clk
748 -reset `TB_RST
749 -module sii_ilc_ctl
750 -name sii_ilc_buffer_under_counter
751*/
752
753/* 0in arithmetic_overflow
754 -var sio_cnt_l[2:0]
755 -val ((sii_l2t_req_vld && ~posted && ~jtag && ~sio_sii_olc_ilc_dequeue_r )? (sio_cnt_r[2:0]+3'b001) : (sio_sii_olc_ilc_dequeue_r && ~(sii_l2t_req_vld && ~posted))? (sio_cnt_r[2:0] - 3'b001): sio_cnt_r[2:0])
756 -clock l2clk
757 -reset `TB_RST
758 -module sii_ilc_ctl
759 -name sii_ilc_buffer_over_counter
760*/
761
762
763/*************************************************************************
764*
765* sii ipd hdr and data fifo
766*
767**************************************************************************/
768/* NIU & DMU, bypass & order HEADER queue */
769 /* 0in multi_clock_fifo
770 -enq wr_en
771 -deq (rd_adr !== $0in_delay(rd_adr, 1, rdclk))
772 -depth 16
773 -enq_data din
774 -deq_data dout
775 -enq_clock wrclk
776 -deq_clock rdclk
777 -module n2_com_dp_16x72_cust
778 -name sii_ipd_hdr_fifo
779 */
780
781 /* x0in custom
782 -fire ($0in_delay(rd_en, 1, rdclk) && wr_en_d1 && ($0in_delay(rd_adr, 1, rdclk) === wr_adr_d1))
783 -message "ipd hdr FIFO overrun: rd and wr pointer valid on same addr"
784 -module n2_com_dp_16x72_cust
785 -clock rdclk
786 -name sii_ipd_hdr_ptr_overrun
787 */
788
789/* 0in assert_timer
790 -var (wr_en && (wr_adr == $0in_delay(wr_adr, 1,wrclk)))
791 -max 1
792 -clock wrclk
793 -reset `TB_RST
794 -module n2_com_dp_16x72_cust
795 -name sii_ipd_hdr_wr_en
796*/
797
798
799/* NIU & DMU, bypass & order DATA queue */
800 /* 0in multi_clock_fifo
801 -enq wr_en
802 -deq (rd_adr !== $0in_delay(rd_adr, 1, rdclk))
803 -depth 64
804 -enq_data din
805 -deq_data dout
806 -enq_clock wrclk
807 -deq_clock rdclk
808 -module n2_com_dp_64x80_cust
809 -name sii_ipd_data_fifo
810 */
811
812 /* x0in custom
813 -fire ($0in_delay(rd_en, 1, rdclk) && wr_en_d1 && (rd_adr_d1 === wr_adr_d1))
814 -message "ipd data FIFO overrun: rd and wr pointer valid on same addr"
815 -clock rdclk
816 -module n2_com_dp_64x80_cust
817 -name sii_ipd_data_ptr_overrun
818 */
819
820/* 0in assert_timer
821 -var (wr_en && (wr_adr == $0in_delay(wr_adr, 1,wrclk)))
822 -max 1
823 -clock wrclk
824 -reset `TB_RST
825 -module n2_com_dp_64x80_cust
826 -name sii_ipd_data_wr_en
827*/
828
829
830/*************************************************************************
831*
832* sio opd hdr and data fifo
833*
834**************************************************************************/
835/* x0in multi_clock_fifo
836 -enq wr_en
837 -deq (rd_adr !== $0in_delay(rd_adr, 1, rdclk))
838 -depth 16
839 -enq_data din
840 -deq_data dout
841 -enq_clock wrclk
842 -deq_clock rdclk
843 -reset `TB_RST
844 -module n2_com_dp_16x32s_cust
845 -name sio_opd_hdr_fifo
846*/
847
848/* x0in custom
849 -fire ((rd_en && (rd_adr !== $0in_delay(rd_adr, 1, rdclk))) && wr_en && (rd_adr === wr_adr))
850 -message "opd hdr FIFO overrun: rd and wr pointer valid on same addr"
851 -module n2_com_dp_16x32s_cust
852 -name sio_op_hdr_ptr_overrun
853*/
854
855/* 0in assert_timer
856 -var (wr_en && (wr_adr == $0in_delay(wr_adr, 1,wrclk)))
857 -max 1
858 -clock wrclk
859 -reset `TB_RST
860 -module n2_com_dp_16x32s_cust
861 -name sio_op_hdr_wr_en
862*/
863
864/* 0in multi_clock_fifo
865 -enq (wr_en && (wr_adr !== $0in_delay(wr_adr, 1)))
866 -deq (rd_en && (rd_adr !== $0in_delay(rd_adr, 1)))
867 -depth 64
868 -enq_data din
869 -deq_data dout
870 -enq_clock wrclk
871 -deq_clock rdclk
872 -module n2_com_dp_64x72s_cust
873 -name sio_op_data_fifo
874*/
875
876/* 0in custom
877 -fire ((rd_en && (rd_adr !== $0in_delay(rd_adr, 1, rdclk))) && wr_en && (rd_adr === wr_adr))
878 -message "opd data FIFO overrun: rd and wr pointer valid on same addr"
879 -reset `TB_RST
880 -module n2_com_dp_64x72s_cust
881 -name sio_op_data_ptr_overrun
882*/
883
884/* 0in assert_timer
885 -var wr_en
886 -max 1
887 -clock wrclk
888 -reset `TB_RST
889 -module n2_com_dp_64x72s_cust
890 -name sio_op_data_wr_en
891*/
892
893/* 0in assert_follower
894 -leader opddq00.wr_en
895 -follower opddq01.wr_en
896 -min 1
897 -max 1
898 -clock l2clk
899 -reset `TB_RST
900 -module sio
901 -name sio_op_data_opddq00
902*/
903
904
905/* 0in assert_follower
906 -leader opddq10.wr_en
907 -follower opddq11.wr_en
908 -min 1
909 -max 1
910 -clock l2clk
911 -reset `TB_RST
912 -module sio
913 -name sio_op_data_opddq10
914*/
915
916
917/*************************************************************************
918*
919* sio_opcc - arbitration
920*
921**************************************************************************/
922
923/* 0in arbiter
924 -req (olc0_opcc_req && (queuecredit[0] == 1)) (olc1_opcc_req && (queuecredit[1] == 1)) (olc2_opcc_req && (queuecredit[2] == 1)) (olc3_opcc_req && (queuecredit[3] == 1)) (olc4_opcc_req && (queuecredit[4] == 1)) (olc5_opcc_req && (queuecredit[5] == 1)) (olc6_opcc_req && (queuecredit[6] == 1)) (olc7_opcc_req && (queuecredit[7] == 1))
925 -gnt opcc_olc0_gnt opcc_olc1_gnt opcc_olc2_gnt opcc_olc3_gnt opcc_olc4_gnt opcc_olc5_gnt opcc_olc6_gnt opcc_olc7_gnt
926 -round_robin
927 -max_grant 1
928 -no_simultaneous_req_gnt
929 -clock l2clk
930 -reset `TB_RST
931 -module sio_opcc_ctl
932 -name sio_opcc_arb1
933*/
934
935
936
937/*************************************************************************
938*
939* sii ild fifo
940*
941**************************************************************************/
942/* SII to L2 queues */
943 /* 0in fifo
944 -enq wr_en
945 -deq (rd_adr !== $0in_delay(rd_adr, 1))
946 -depth 32
947 -enq_data din
948 -deq_data dout
949 -clock rdclk
950 -reset `TB_RST
951 -module n2_com_dp_32x82_cust
952 -name sii_ild_fifo
953 */
954
955 /* 0in custom
956 -fire ((rd_en && (rd_adr !== $0in_delay(rd_adr, 1))) && wr_en && (rd_adr === wr_adr))
957 -message "ild FIFO overrun: rd and wr pointer valid on same addr"
958 -module n2_com_dp_32x82_cust
959 -clock rdclk
960 -reset `TB_RST
961 -name sii_ild_ptr_overrun
962 */
963
964/*************************************************************************
965*
966* sii ind fifo
967*
968**************************************************************************/
969/* SII to NCU queues */
970 /* 0in fifo
971 -enq indq.wr_en
972 -deq (indq.rd_adr !== $0in_delay(indq.rd_adr, 1))
973 -depth 48
974 -enq_data indq.din
975 -deq_data indq.dout
976 -clock indq.rdclk
977 -reset `TB_RST
978 -module sii
979 -name sii_ind_fifo
980 */
981
982 /* 0in custom
983 -fire ((indq.rd_en && (indq.rd_adr !== $0in_delay(indq.rd_adr, 1))) && indq.wr_en && (indq.rd_adr === indq.wr_adr))
984 -message "ind FIFO overrun: rd and wr pointer valid on same addr"
985 -clock indq.rdclk
986 -reset `TB_RST
987 -module sii
988 -name sii_ind_ptr_overrun
989 */
990
991/*************************************************************************
992*
993* sio old fifo
994*
995**************************************************************************/
996/* L2 to SIO queues */
997 /* Fu: disabled
998 * 8/4 rd_en for olddq00 is not reliable, on for multiple cycles but no address changes
999 * 9/22 32x32 is using by ncu, and the usage is different, so I have to disable it
1000 */
1001 /* x0in fifo
1002 -enq wr_en
1003 -deq (rd_adr !== $0in_delay(rd_adr, 1))
1004 -depth 32
1005 -enq_data din
1006 -deq_data local_dout
1007 -reset `TB_RST
1008 -module n2_com_dp_32x32_cust
1009 -name sio_old_fifo
1010 */
1011
1012 /* 0in custom
1013 -fire (olc_olddq0_rd_en && olc_olddq0_wr_en && (olc_olddq0_rd_addr === olc_olddq0_wr_addr))
1014 -message "olddq0 FIFO overrun: rd and wr pointer valid on same addr"
1015 -module sio_olc_ctl
1016 -clock l2clk
1017 -reset `TB_RST
1018 -name sio_olddq0_ptr_overrun
1019 */
1020 /* 0in custom
1021 -fire (olc_olddq1_rd_en && olc_olddq1_wr_en && (olc_olddq1_rd_addr === olc_olddq1_wr_addr))
1022 -message "olddq1 FIFO overrun: rd and wr pointer valid on same addr"
1023 -module sio_olc_ctl
1024 -clock l2clk
1025 -reset `TB_RST
1026 -name sio_olddq1_ptr_overrun
1027 */
1028
1029/*************************************************************************
1030*
1031* TCU -> SII interface
1032* SIO -> TCU interface
1033*
1034**************************************************************************/
1035
1036/* Fu: 2/1/06 turn off, checkers not correct, */
1037/* x0in assert_follower
1038 -leader tcu_sii_vld
1039 -follower tcu_sii_vld
1040 -min 64
1041 -max 3000
1042 -clock l2clk
1043 -reset `TB_RST
1044 -module sii_ipcc_ctl
1045 -name tcu_sii_hdr_vld
1046*/
1047
1048/* x0in assert_follower
1049 -leader sio_tcu_vld
1050 -follower sio_tcu_vld
1051 -min 64
1052 -max 3000
1053 -clock l2clk
1054 -module sio_opcc_ctl
1055 -name sio_tcu_hdr_vld
1056*/
1057
1058endmodule // siu_wb_chkr
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