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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: plus_args.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifndef PLUS_ARGS_INC | |
36 | `define PLUS_ARGS_INC | |
37 | ||
38 | //---------------------------------------------------------- | |
39 | // Plusarg processing | |
40 | ||
41 | reg [16*8:0] tempstr; | |
42 | integer timeout ; | |
43 | reg nas_check_on; | |
44 | reg dma_memchk_off; | |
45 | reg tlb_sync_on; | |
46 | reg ldst_sync_on; | |
47 | reg icache_sync_on; | |
48 | reg int_sync_on; | |
49 | reg err_sync_on; | |
50 | reg pku_err_inject; | |
51 | reg lsu_mon_on; | |
52 | reg gchkr_on; | |
53 | reg err_chkrs_off; | |
54 | reg show_delta_on; | |
55 | reg show_memop_on; | |
56 | reg show_tlb_on; | |
57 | reg hash_on; | |
58 | reg perf_diag; | |
59 | reg win_check_on; | |
60 | reg axis_debug_on; | |
61 | reg soc_sync_on; | |
62 | reg socket_use_flush; | |
63 | integer max_cycle; | |
64 | integer nas_q_rate; | |
65 | // reg [3:0] pwr_throttle; | |
66 | `ifdef AXIS_TL | |
67 | reg [`TRAP_ADDR_WIDTH-1:0] good_trap_addr; | |
68 | reg [`TRAP_ADDR_WIDTH-1:0] bad_trap_addr1; | |
69 | reg [`TRAP_ADDR_WIDTH-1:0] bad_trap_addr2; | |
70 | reg [`TRAP_ADDR_WIDTH-1:0] bad_trap_addr3; | |
71 | reg [`TRAP_ADDR_WIDTH-1:0] bad_trap_addr4; | |
72 | `else | |
73 | reg [`TRAP_ADDR_WIDTH-1:0] good_trap_addr [`MAX_TRAP_ADDRS-1:0]; | |
74 | reg [`TRAP_ADDR_WIDTH-1:0] bad_trap_addr [`MAX_TRAP_ADDRS-1:0]; | |
75 | `endif | |
76 | reg [6:0] good_trap_count; | |
77 | reg [6:0] bad_trap_count; | |
78 | reg mamon; | |
79 | reg dec_spu_grant; | |
80 | reg [63:0] th_check_enable; | |
81 | reg [63:0] finish_mask; | |
82 | reg [63:0] mp_mask; | |
83 | integer th_timeout; | |
84 | integer skt_timeout; | |
85 | ||
86 | reg [3:0] bank_set_mask; | |
87 | reg [3:0] bank_set_mask_csr; | |
88 | ||
89 | reg [8*(`TRAP_ADDR_CHARS+1)*`MAX_TRAP_ADDRS:0] tmptrapstr; | |
90 | integer i; | |
91 | reg [31:0] tmp32; | |
92 | integer asi_power_throttle_freq; | |
93 | reg [7:0] core_set_mask; | |
94 | reg [63:0] core_set_mask_tids; | |
95 | ||
96 | // | |
97 | // ALL calls to $random MUST look like this!!! $random(`PARGS.seed) | |
98 | // and must be made AFTER time zero!!! <------------- | |
99 | // | |
100 | integer seedin, seed; | |
101 | ||
102 | ||
103 | initial begin // { | |
104 | ||
105 | nas_check_on = 0; | |
106 | dma_memchk_off = 0; | |
107 | tlb_sync_on = 1; // Enabled by default | |
108 | ldst_sync_on = 1; // Enabled by default | |
109 | icache_sync_on = 0; | |
110 | int_sync_on = 1; // Enabled by default | |
111 | err_sync_on = 1; // Enabled by default | |
112 | pku_err_inject = 0; | |
113 | lsu_mon_on = 1; // Enabled by default | |
114 | gchkr_on = 0; | |
115 | err_chkrs_off = 0; | |
116 | show_delta_on = 0; | |
117 | show_memop_on = 0; | |
118 | show_tlb_on = 0; | |
119 | hash_on = 0; | |
120 | perf_diag = 0; | |
121 | win_check_on = 0; | |
122 | axis_debug_on = 0; | |
123 | soc_sync_on = 1; // Enabled by default | |
124 | max_cycle = 0; | |
125 | good_trap_count = 0; | |
126 | bad_trap_count = 0; | |
127 | mamon = 0; | |
128 | dec_spu_grant = 0; | |
129 | timeout = `TIMEOUT; | |
130 | th_timeout = 0; | |
131 | skt_timeout = 0; | |
132 | th_check_enable = 64'b1; | |
133 | finish_mask = 0; | |
134 | seed = 1; | |
135 | seedin = 1; | |
136 | asi_power_throttle_freq = 1500; | |
137 | nas_q_rate = 20; | |
138 | mp_mask = 0; | |
139 | socket_use_flush = 0; | |
140 | bank_set_mask_csr = 0; | |
141 | bank_set_mask = 0; | |
142 | core_set_mask = 8'hff; | |
143 | core_set_mask_tids = 64'hffffffffffffffff; | |
144 | ||
145 | `ifdef CORE_0 | |
146 | mp_mask = mp_mask | 64'h00000000_000000ff; | |
147 | `endif | |
148 | `ifdef CORE_1 | |
149 | mp_mask = mp_mask | 64'h00000000_0000ff00; | |
150 | `endif | |
151 | `ifdef CORE_2 | |
152 | mp_mask = mp_mask | 64'h00000000_00ff0000; | |
153 | `endif | |
154 | `ifdef CORE_3 | |
155 | mp_mask = mp_mask | 64'h00000000_ff000000; | |
156 | `endif | |
157 | `ifdef CORE_4 | |
158 | mp_mask = mp_mask | 64'h000000ff_00000000; | |
159 | `endif | |
160 | `ifdef CORE_5 | |
161 | mp_mask = mp_mask | 64'h0000ff00_00000000; | |
162 | `endif | |
163 | `ifdef CORE_6 | |
164 | mp_mask = mp_mask | 64'h00ff0000_00000000; | |
165 | `endif | |
166 | `ifdef CORE_7 | |
167 | mp_mask = mp_mask | 64'hff000000_00000000; | |
168 | `endif | |
169 | ||
170 | // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
171 | // | |
172 | // These +args must be processed first so other initial blocks can use the values. | |
173 | // Therefore, any initial block that uses `PARGS.var MUST have a #0 or #1 first. | |
174 | // Ideally, you should do NOTHING at time zero since nothing is stable at time zero. | |
175 | // Ideally, you should do NOTHING at time zero since nothing is stable at time zero. | |
176 | // | |
177 | // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
178 | ||
179 | // | |
180 | // ALL calls to $random MUST look like this!!! $random(`PARGS.seed) | |
181 | // and must be made AFTER time zero!!! <------------- | |
182 | // | |
183 | i = $value$plusargs("tg_seed=%d", seedin); | |
184 | tmp32 = seedin; | |
185 | tmp32[31] = 0; | |
186 | seedin = tmp32; // always positive int ([31] = 0) | |
187 | seed = seedin; // seedin is a copy of passed in seedValue. seed var changes as used. | |
188 | `PR_ALWAYS ("arg", `ALWAYS, "The VERILOG random generator initial seed is %0d (should match VERA)",seedin); | |
189 | ||
190 | // | |
191 | // ALL calls to $random MUST look like this!!! $random(`PARGS.seed) | |
192 | // and must be made AFTER time zero!!! <------------- | |
193 | // | |
194 | ||
195 | // initial call | |
196 | i = $random(`PARGS.seed); | |
197 | ||
198 | `ifdef AXIS_TL | |
199 | nas_check_on = 0; | |
200 | `else | |
201 | //-------------- | |
202 | // Misc | |
203 | // !!! Must check for this plusarg (before *sync args since they need to know if ~nas_check_on. | |
204 | if ($test$plusargs("use_sas_tasks")) begin // { | |
205 | nas_check_on = 1; | |
206 | `PR_ALWAYS ("arg", `ALWAYS, "Nas Checking Enabled"); | |
207 | end // } | |
208 | else begin // { | |
209 | `PR_ALWAYS ("arg",`ALWAYS,"-------------------------------"); | |
210 | `PR_ALWAYS ("arg",`ALWAYS,"!!!!! !!!!!"); | |
211 | `PR_ALWAYS ("arg",`ALWAYS,"!!!!! !!!!!"); | |
212 | `PR_ALWAYS ("arg",`ALWAYS," Nas Checking Disabled"); | |
213 | `PR_ALWAYS ("arg",`ALWAYS,"!!!!! !!!!!"); | |
214 | `PR_ALWAYS ("arg",`ALWAYS,"!!!!! !!!!!"); | |
215 | `PR_ALWAYS ("arg",`ALWAYS,"-------------------------------"); | |
216 | end //} | |
217 | `endif | |
218 | ||
219 | //-------------- | |
220 | // NAS Q RATE | |
221 | if ($test$plusargs("nas_q_rate")) begin // { | |
222 | if($value$plusargs("nas_q_rate=%d", nas_q_rate)) begin | |
223 | end | |
224 | end // } | |
225 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - Nas Q Rate is %d", nas_q_rate); | |
226 | //-------------- | |
227 | // SOCKET USE FLUSH | |
228 | if ($test$plusargs("socket_use_flush")) begin // { | |
229 | socket_use_flush = 1; | |
230 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - Socket Sends on Flush ONLY"); | |
231 | end // } | |
232 | //-------------- | |
233 | // TLB SYNC | |
234 | if (($test$plusargs("notlb_sync"))|(nas_check_on==0)) begin // { | |
235 | tlb_sync_on = 0; | |
236 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - tlb_sync Disabled"); | |
237 | end // } | |
238 | else begin // { | |
239 | `PR_ALWAYS ("arg",`ALWAYS,"tlb_sync Enabled"); | |
240 | end //} | |
241 | ||
242 | //-------------- | |
243 | // Icache SYNC - must have nas & ldst_sync & tlb_sync enabled first | |
244 | if (($test$plusargs("noldst_sync"))|($test$plusargs("notlb_sync"))|(nas_check_on==0)) begin // { | |
245 | icache_sync_on = 0; | |
246 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - icache_sync Disabled"); | |
247 | end // } | |
248 | else if ($test$plusargs("icache_sync_on"))begin // { | |
249 | icache_sync_on = 1; | |
250 | `PR_ALWAYS ("arg", `ALWAYS, "icache_sync Enabled"); | |
251 | end //} | |
252 | else begin // { | |
253 | icache_sync_on = 0; | |
254 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - icache_sync Disabled"); | |
255 | end //} | |
256 | ||
257 | //-------------- | |
258 | // LDST SYNC | |
259 | if (($test$plusargs("noldst_sync"))|(nas_check_on==0)) begin // { | |
260 | ldst_sync_on = 0; | |
261 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - ldst_sync Disabled"); | |
262 | end // } | |
263 | else begin // { | |
264 | `PR_ALWAYS ("arg", `ALWAYS, "ldst_sync Enabled"); | |
265 | end //} | |
266 | ||
267 | //-------------- | |
268 | // INT SYNC | |
269 | if (($test$plusargs("noint_sync"))|(nas_check_on==0)) begin // { | |
270 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - int_sync Disabled"); | |
271 | int_sync_on = 0; | |
272 | end // } | |
273 | else begin // { | |
274 | `PR_ALWAYS ("arg", `ALWAYS, "int_sync Enabled"); | |
275 | end //} | |
276 | ||
277 | //-------------- | |
278 | // ERR SYNC | |
279 | if (($test$plusargs("err_sync_on"))&&(nas_check_on!=0)) begin // { | |
280 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - err_sync Enabled"); | |
281 | err_sync_on = 1; | |
282 | end // } | |
283 | ||
284 | if (($test$plusargs("noerr_sync"))|(nas_check_on==0)) begin // { | |
285 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - err_sync Disabled"); | |
286 | err_sync_on = 0; | |
287 | end // } | |
288 | else begin // { | |
289 | `PR_ALWAYS ("arg",`ALWAYS,"err_sync Enabled"); | |
290 | end //} | |
291 | ||
292 | //-------------- | |
293 | // DMA Mem Check | |
294 | if (($test$plusargs("dma_memchk_off"))|(nas_check_on==0)) begin // { | |
295 | dma_memchk_off = 1; | |
296 | `PR_ALWAYS ("arg",`ALWAYS,"dma_memchk Disabled"); | |
297 | end // } | |
298 | else begin // { | |
299 | dma_memchk_off = 0; | |
300 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - dma_memchk Enabled"); | |
301 | end //} | |
302 | ||
303 | //-------------- | |
304 | // SOC SYNC | |
305 | if ($test$plusargs("nosoc_sync")) begin // { | |
306 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - soc_sync Disabled"); | |
307 | soc_sync_on = 0; | |
308 | end // } | |
309 | else begin // { | |
310 | `PR_ALWAYS ("arg", `ALWAYS, "soc_sync Enabled"); | |
311 | end //} | |
312 | ||
313 | //-------------- | |
314 | // PKU Error Injection | |
315 | if ($test$plusargs("pku_err_inject")) begin // { | |
316 | `PR_ALWAYS ("arg",`ALWAYS,"pku_err_inject Enabled"); | |
317 | pku_err_inject = 1; | |
318 | end // } | |
319 | ||
320 | // LSU_MON | |
321 | if ($test$plusargs("lsu_mon_off")) begin // { | |
322 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - lsu_mon Disabled"); | |
323 | lsu_mon_on = 0; | |
324 | end // } | |
325 | else begin // { | |
326 | `PR_ALWAYS ("arg", `ALWAYS, "lsu_mon Enabled"); | |
327 | end //} | |
328 | ||
329 | // global_chkr | |
330 | if ($test$plusargs("gchkr_off")) begin // { | |
331 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - Global Chkr Disabled."); | |
332 | gchkr_on = 0; | |
333 | end // } | |
334 | else begin // { | |
335 | `ifndef SPC_BENCH //global chkr shd not be enabled in the SPC bench | |
336 | gchkr_on = 1; | |
337 | `PR_ALWAYS ("arg", `ALWAYS,"NOTICE - Global Chkr Enabled."); | |
338 | `endif | |
339 | end //} | |
340 | ||
341 | // RAS_CHKR | |
342 | if ($test$plusargs("err_chkrs_off")) begin // { | |
343 | `PR_ALWAYS ("arg",`ALWAYS,"NOTICE - Block level err chkrs Disabled"); | |
344 | err_chkrs_off = 1; | |
345 | end // } | |
346 | ||
347 | //-------------- | |
348 | // Debug & printing .. | |
349 | if ($test$plusargs("show_delta")) begin // { | |
350 | show_delta_on = 1; | |
351 | `TOP.quiet = 0; | |
352 | `PR_ALWAYS ("arg", `ALWAYS, "Show Delta Enabled"); | |
353 | end // } | |
354 | ||
355 | if ($test$plusargs("show_memop")) begin // { | |
356 | show_memop_on = 1; | |
357 | `PR_ALWAYS ("arg", `ALWAYS, "show_memop Enabled"); | |
358 | end // } | |
359 | ||
360 | if ($test$plusargs("show_tlb")) begin // { | |
361 | show_tlb_on = 1; | |
362 | `PR_ALWAYS ("arg", `ALWAYS, "show_tlb Enabled"); | |
363 | end // } | |
364 | ||
365 | //----- | |
366 | // Index Hash | |
367 | if ($test$plusargs("hash_on")) begin // { | |
368 | hash_on = 1; | |
369 | `PR_ALWAYS ("arg", `ALWAYS, "hash_on Enabled"); | |
370 | `ifdef FC_BENCH | |
371 | `PR_ALWAYS ("arg", `ALWAYS, "Force bit in NCU to enable hash."); | |
372 | `ifdef NCU_GATE | |
373 | force `CPU.ncu.ncu_scd_ctl__n63154 = 1'b1; | |
374 | `else | |
375 | force `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.l2idxhs_en_status = 1'b1; | |
376 | `endif | |
377 | `endif | |
378 | end // } | |
379 | ||
380 | if ($test$plusargs("hash_on_no_force")) begin // { | |
381 | hash_on = 1; | |
382 | `PR_ALWAYS ("arg", `ALWAYS, "hash_on Enabled"); | |
383 | end // } | |
384 | //----- | |
385 | ||
386 | if ($test$plusargs("perf_diag")) begin // { | |
387 | perf_diag = 1; | |
388 | `PR_ALWAYS ("arg", `ALWAYS, "perf_diag Enabled"); | |
389 | end // } | |
390 | ||
391 | if ($test$plusargs("win_check")) begin // { | |
392 | win_check_on = 1; | |
393 | `PR_ALWAYS ("arg", `ALWAYS, "win_check Enabled"); | |
394 | end // } | |
395 | ||
396 | if ($test$plusargs("AXIS_DEBUG_ON")) begin // { | |
397 | axis_debug_on = 1; | |
398 | `PR_ALWAYS ("arg", `ALWAYS, "AXIS_DEBUG_ON Enabled"); | |
399 | end // } | |
400 | ||
401 | ||
402 | //--------------- | |
403 | // reduced core set. partial core for vectors. "portable core" related. | |
404 | // must be done before finish_mask and th_check_enable!!! | |
405 | if ($test$plusargs("core_set_mask")) begin | |
406 | if ($value$plusargs("core_set_mask=%0h", core_set_mask)) begin | |
407 | if (core_set_mask < 8'hff) begin | |
408 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - Partial core mode is enabled. core_set_mask = %0h", core_set_mask); | |
409 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - Partial core mode. thread/th_check_enable/finish_mask/etc may be adjusted based on core_set_mask."); | |
410 | for (i=7;i>=0;i=i-1) begin | |
411 | core_set_mask_tids = core_set_mask_tids << 8; | |
412 | core_set_mask_tids[7:0] = {8{core_set_mask[i]}}; | |
413 | end | |
414 | mp_mask = mp_mask & core_set_mask_tids; | |
415 | end | |
416 | end | |
417 | end | |
418 | ||
419 | ||
420 | //-------------- | |
421 | // Thread Enable | |
422 | if (! $test$plusargs("no_thread_force")) begin // { | |
423 | if ($value$plusargs("thread=%s", tempstr)) begin // { | |
424 | if (tempstr == "0") begin | |
425 | `PR_WARN ("arg", `WARN, "WARNING: thread=0 has the same effect as none, all threads will be disabled!\n"); | |
426 | end | |
427 | th_check_enable = {get_thread_enables(tempstr)}; | |
428 | end // } | |
429 | end // } | |
430 | ||
431 | th_check_enable = th_check_enable & mp_mask; | |
432 | `PR_ALWAYS ("arg", `ALWAYS, "Initial Thread Check Control (may change if SW startup): %h (th_check_enable/+thread)",th_check_enable); | |
433 | ||
434 | //-------------- | |
435 | // FinishMask | |
436 | finish_mask = th_check_enable; | |
437 | //`PR_ALWAYS ("arg", `ALWAYS, "Thread Finish Mask (finish_mask) is now 0x%h (+thread/th_check_enable based).\n", finish_mask); | |
438 | // Override finish mask from plusarg | |
439 | if ($value$plusargs("finish_mask=%s", tempstr)) begin // { | |
440 | if (tempstr == "0") begin | |
441 | `PR_WARN ("arg", `WARN, "WARNING - finish_mask=0 has the same effect as none, bench will not wait for any threads to reach good/bad trap!\n"); | |
442 | end | |
443 | finish_mask = {get_thread_enables(tempstr)}; | |
444 | end // } | |
445 | ||
446 | finish_mask = finish_mask & mp_mask; | |
447 | `PR_ALWAYS("arg", `ALWAYS, "Thread Finish Mask, adjusted: %h (finish_mask/+finish_mask)",finish_mask); | |
448 | ||
449 | ||
450 | ||
451 | //-------------- | |
452 | // Timeouts | |
453 | `PR_ALWAYS ("arg", `ALWAYS, ""); | |
454 | `PR_ALWAYS ("arg", `ALWAYS,"!!! BE AWARE - timeout values are in # of Cycles, NOT # of ps/fs units"); | |
455 | ||
456 | // Runaway throttle | |
457 | if ($value$plusargs("max_cycle=%d", max_cycle)) begin // { | |
458 | end // } | |
459 | else begin // { | |
460 | max_cycle = 1000000; | |
461 | end // } | |
462 | `PR_ALWAYS ("arg", `ALWAYS, | |
463 | "Max Cycles %d Cycles (Timeout if simulation reaches this cycle count) ", | |
464 | max_cycle); | |
465 | ||
466 | if ($value$plusargs("TIMEOUT=%d", timeout)) begin // { | |
467 | end // } | |
468 | else begin // { | |
469 | timeout = 1000; | |
470 | end // } | |
471 | `PR_ALWAYS ("arg", `ALWAYS, | |
472 | "Global Timeout %d Cycles (Timeout if ALL threads are idle (i.e. no SSTEP)) ", | |
473 | timeout); | |
474 | ||
475 | if ($value$plusargs("th_timeout=%d", th_timeout)) begin // { | |
476 | end // } | |
477 | else begin // { | |
478 | th_timeout = timeout * 5; | |
479 | end // } | |
480 | `PR_ALWAYS ("arg", `ALWAYS, | |
481 | "Thread Timeout %d Cycles (Timeout if ANY thread is idle (i.e. no SSTEP))", | |
482 | th_timeout); | |
483 | ||
484 | if ($value$plusargs("skt_timeout=%d", skt_timeout)) begin // { | |
485 | end // } | |
486 | else begin // { | |
487 | skt_timeout = 5000; | |
488 | end // } | |
489 | `PR_ALWAYS ("arg", `ALWAYS, | |
490 | "Socket Timeout %d Cycles (Timeout if no socket msg from Riesling) ", | |
491 | skt_timeout); | |
492 | `PR_ALWAYS ("arg", `ALWAYS, ""); | |
493 | ||
494 | ||
495 | ||
496 | //-------------- | |
497 | // Goodtrap/Badtrap | |
498 | if ($test$plusargs("good_trap")) begin // { | |
499 | if ($value$plusargs("good_trap=%s", tmptrapstr)) begin | |
500 | good_trap_count = get_good_trap_addr(tmptrapstr); | |
501 | `WR_ALWAYS("arg", `ALWAYS, "Good Trap Address (%0d):", good_trap_count); | |
502 | `ifdef AXIS_TL | |
503 | `WR_ALWAYS("arg", `ALWAYS, " %h", good_trap_addr); | |
504 | `PR_ALWAYS("arg", `ALWAYS, ""); | |
505 | if (good_trap_count > 1) | |
506 | `PR_WARN("arg", `WARN, "axis targetless model can only support one good trap and one bad trap address"); | |
507 | `else | |
508 | for (i=0;i<good_trap_count;i=i+1) | |
509 | `WR_ALWAYS("arg", `ALWAYS, " %h", good_trap_addr[i]); | |
510 | `PR_ALWAYS("arg", `ALWAYS, ""); | |
511 | `endif | |
512 | end | |
513 | end // } | |
514 | else begin // { | |
515 | good_trap_count = 0; | |
516 | `PR_WARN("arg", `WARN, "WARNING - No good_trap address found!\n\tSimulation may not terminate!\n"); | |
517 | end // } | |
518 | ||
519 | if ($test$plusargs("bad_trap")) begin // { | |
520 | if ($value$plusargs("bad_trap=%s", tmptrapstr)) begin | |
521 | bad_trap_count = get_bad_trap_addr(tmptrapstr); | |
522 | `WR_ALWAYS("arg", `ALWAYS, "Bad Trap Address(%0d):", bad_trap_count); | |
523 | `ifdef AXIS_TL | |
524 | //`WR_ALWAYS("arg", `ALWAYS, " %h", bad_trap_addr); | |
525 | //`PR_ALWAYS("arg", `ALWAYS, ""); | |
526 | for (i=0;i<=bad_trap_count;i=i+1) | |
527 | case (i) | |
528 | 1: $display("bad trap addr 1 = %h",bad_trap_addr1); | |
529 | 2: $display("bad trap addr 2 = %h",bad_trap_addr2); | |
530 | 3: $display("bad trap addr 3 = %h",bad_trap_addr3); | |
531 | 4: $display("bad trap addr 4 = %h",bad_trap_addr4); | |
532 | endcase | |
533 | ||
534 | `PR_WARN("arg", `WARN, "axis targetless model can only support four bad trap and one bad trap address"); | |
535 | `else | |
536 | for (i=0;i<bad_trap_count;i=i+1) | |
537 | `WR_ALWAYS("arg", `ALWAYS, " %h", bad_trap_addr[i]); | |
538 | `PR_ALWAYS("arg", `ALWAYS, ""); | |
539 | `endif | |
540 | end | |
541 | end // } | |
542 | else begin // { | |
543 | bad_trap_count = 0; | |
544 | `PR_WARN("arg", `WARN, "WARNING - No bad_trap address found!\n\tSimulation may not terminate!\n"); | |
545 | end // } | |
546 | ||
547 | ||
548 | //-------------- | |
549 | // bank_set_mask for efuse partial bank mode | |
550 | if ($test$plusargs("bank_set_mask")) begin | |
551 | // will runtime force NCU wires pm, ba01, ba23, ... if not 4'h0 | |
552 | if ($value$plusargs("bank_set_mask=%h", bank_set_mask)) begin // { | |
553 | if (bank_set_mask == 0) begin | |
554 | `PR_WARN ("arg", `WARN, "WARNING - bank_set_mask=0 is being ignored! You need at least one pair!\n"); | |
555 | end | |
556 | if (bank_set_mask !== 0) begin | |
557 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - Partial bank mode is enabled w/ binary mask of %b (ba67|ba45|ba23|ba01)\n", bank_set_mask); | |
558 | end | |
559 | end | |
560 | end | |
561 | ||
562 | ||
563 | //-------------- | |
564 | // bank_set_mask_csr for csr partial bank mode | |
565 | if ($test$plusargs("bank_set_mask_csr")) begin | |
566 | // will runtime force NCU wires pm, ba01, ba23, ... if not 4'h0 | |
567 | if ($value$plusargs("bank_set_mask_csr=%h", bank_set_mask_csr)) begin // { | |
568 | if (bank_set_mask_csr == 0) begin | |
569 | `PR_WARN ("arg", `WARN, "WARNING - bank_set_mask_csr=0 is being ignored! You need at least one pair!\n"); | |
570 | end | |
571 | if (bank_set_mask_csr !== 0) begin | |
572 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - Partial bank mode is enabled w/ binary mask of %b (ba67|ba45|ba23|ba01)\n", bank_set_mask_csr); | |
573 | end | |
574 | end // } | |
575 | end | |
576 | ||
577 | end // initial } | |
578 | ||
579 | ||
580 | `ifndef AXIS_TL | |
581 | `ifndef PLAYBACK | |
582 | `ifdef CORE_BENCH | |
583 | initial begin | |
584 | if ($test$plusargs("clk_stop_exit")) begin | |
585 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - +clk_stop_exit seen. Simulation will exit after ANY clocks have stopped (FC/SPC2 only)!"); | |
586 | ||
587 | `ifdef FC_BENCH | |
588 | // wait for clocks to stop | |
589 | @(posedge `TOP.flush_reset_complete); | |
590 | @(posedge `CPU.tcu_ccu_clk_stop or | |
591 | posedge `CPU.tcu_ccu_io_clk_stop or | |
592 | posedge `CPU.tcu_spc0_clk_stop or | |
593 | posedge `CPU.tcu_spc1_clk_stop or | |
594 | posedge `CPU.tcu_spc2_clk_stop or | |
595 | posedge `CPU.tcu_spc3_clk_stop or | |
596 | posedge `CPU.tcu_spc4_clk_stop or | |
597 | posedge `CPU.tcu_spc5_clk_stop or | |
598 | posedge `CPU.tcu_spc6_clk_stop or | |
599 | posedge `CPU.tcu_spc7_clk_stop or | |
600 | posedge `CPU.tcu_l2d0_clk_stop or | |
601 | posedge `CPU.tcu_l2d1_clk_stop or | |
602 | posedge `CPU.tcu_l2d2_clk_stop or | |
603 | posedge `CPU.tcu_l2d3_clk_stop or | |
604 | posedge `CPU.tcu_l2d4_clk_stop or | |
605 | posedge `CPU.tcu_l2d5_clk_stop or | |
606 | posedge `CPU.tcu_l2d6_clk_stop or | |
607 | posedge `CPU.tcu_l2d7_clk_stop or | |
608 | posedge `CPU.tcu_l2t0_clk_stop or | |
609 | posedge `CPU.tcu_l2t1_clk_stop or | |
610 | posedge `CPU.tcu_l2t2_clk_stop or | |
611 | posedge `CPU.tcu_l2t3_clk_stop or | |
612 | posedge `CPU.tcu_l2t4_clk_stop or | |
613 | posedge `CPU.tcu_l2t5_clk_stop or | |
614 | posedge `CPU.tcu_l2t6_clk_stop or | |
615 | posedge `CPU.tcu_l2t7_clk_stop or | |
616 | posedge `CPU.tcu_l2b0_clk_stop or | |
617 | posedge `CPU.tcu_l2b1_clk_stop or | |
618 | posedge `CPU.tcu_l2b2_clk_stop or | |
619 | posedge `CPU.tcu_l2b3_clk_stop or | |
620 | posedge `CPU.tcu_l2b4_clk_stop or | |
621 | posedge `CPU.tcu_l2b5_clk_stop or | |
622 | posedge `CPU.tcu_l2b6_clk_stop or | |
623 | posedge `CPU.tcu_l2b7_clk_stop or | |
624 | posedge `CPU.tcu_mcu0_clk_stop or | |
625 | posedge `CPU.tcu_mcu0_dr_clk_stop or | |
626 | posedge `CPU.tcu_mcu0_io_clk_stop or | |
627 | posedge `CPU.tcu_mcu0_fbd_clk_stop or | |
628 | posedge `CPU.tcu_mcu1_clk_stop or | |
629 | posedge `CPU.tcu_mcu1_dr_clk_stop or | |
630 | posedge `CPU.tcu_mcu1_io_clk_stop or | |
631 | posedge `CPU.tcu_mcu1_fbd_clk_stop or | |
632 | posedge `CPU.tcu_mcu2_clk_stop or | |
633 | posedge `CPU.tcu_mcu2_dr_clk_stop or | |
634 | posedge `CPU.tcu_mcu2_io_clk_stop or | |
635 | posedge `CPU.tcu_mcu2_fbd_clk_stop or | |
636 | posedge `CPU.tcu_mcu3_clk_stop or | |
637 | posedge `CPU.tcu_mcu3_dr_clk_stop or | |
638 | posedge `CPU.tcu_mcu3_io_clk_stop or | |
639 | posedge `CPU.tcu_mcu3_fbd_clk_stop or | |
640 | posedge `CPU.tcu_ccx_clk_stop or | |
641 | posedge `CPU.tcu_sii_clk_stop or | |
642 | posedge `CPU.tcu_sii_io_clk_stop or | |
643 | posedge `CPU.tcu_sio_clk_stop or | |
644 | posedge `CPU.tcu_sio_io_clk_stop or | |
645 | posedge `CPU.tcu_ncu_clk_stop or | |
646 | posedge `CPU.tcu_ncu_io_clk_stop or | |
647 | posedge `CPU.tcu_efu_clk_stop or | |
648 | posedge `CPU.tcu_efu_io_clk_stop or | |
649 | posedge `CPU.tcu_rst_clk_stop or | |
650 | posedge `CPU.tcu_rst_io_clk_stop or | |
651 | posedge `CPU.tcu_dmu_io_clk_stop or | |
652 | posedge `CPU.tcu_rdp_io_clk_stop or | |
653 | posedge `CPU.tcu_mac_io_clk_stop or | |
654 | posedge `CPU.tcu_rtx_io_clk_stop or | |
655 | posedge `CPU.tcu_tds_io_clk_stop or | |
656 | posedge `CPU.tcu_peu_pc_clk_stop or | |
657 | posedge `CPU.tcu_peu_io_clk_stop); | |
658 | ||
659 | #1000; | |
660 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - +clk_stop_exit exiting because clocks have stopped!"); | |
661 | good_end; | |
662 | `endif | |
663 | ||
664 | `ifdef SPC_BENCH | |
665 | // wait for clocks to stop | |
666 | @(posedge `CPU.spc0_ncu_core_running_status); | |
667 | @(posedge `CPU.tcu_spc0_clk_stop); | |
668 | #1000; | |
669 | `PR_ALWAYS ("arg", `ALWAYS, "NOTICE - +clk_stop_exit exiting because clocks have stopped!"); | |
670 | good_end; | |
671 | `endif | |
672 | ||
673 | end | |
674 | end | |
675 | `endif | |
676 | `endif // PLAYBACK | |
677 | `endif | |
678 | ||
679 | ||
680 | initial begin | |
681 | // do not add anything else in this block!!! | |
682 | // | |
683 | // fast_boot for booting out of main memory | |
684 | if ($test$plusargs("fast_boot")) begin | |
685 | ||
686 | `PR_ALWAYS ("arg", `ALWAYS, "\nNOTICE - fast_boot seen!!! Will boot from 0x20!!!\n"); | |
687 | ||
688 | // will runtime force wire tb_top.cpu.ncu_wmr_vec_mask | |
689 | //force `TOP.cpu.ncu_wmr_vec_mask = 1; | |
690 | ||
691 | `ifndef FC_SCAN_BENCH | |
692 | `ifndef FC_BENCH | |
693 | `ifndef NCURTL | |
694 | `TOP.asi_wmr_vec_mask <= #1 1; // cmp_tasks fake NCU reg | |
695 | `endif | |
696 | `endif | |
697 | `endif | |
698 | ||
699 | `ifdef AXIS_TL | |
700 | force tb_top.cpu.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.wmr_vec_mask=1; | |
701 | `else | |
702 | `ifdef NCURTL | |
703 | // real NCU internal register | |
704 | // we are forcing a register write, NOT holding a force. Diag can write later. | |
705 | //assign wmr_vec_mask_n = asi_wmr_vec_mask_wr ? ncu_man_ucb_c2i_packet_data[0] : wmr_vec_mask; | |
706 | `ifdef NCU_GATE | |
707 | `define ASI_WMR_VEC_MASK_WR `NCU.ncu_scd_ctl__n36047 | |
708 | `define NCU_MAN_UCB_C2I_PACKET_DATA0 `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_ncu_man_ucb_c2i_packet_data_0_ | |
709 | `define WMR_VEC_MASK `NCU.ncu_scd_ctl__n63512 | |
710 | `define WAKE_THREAD `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_wake_thread | |
711 | `define NCU_L1CLK `NCU.ca1_l1clkhdr__iol2clk__col_3__vdd__tcu_scan_en__vss__grp_1_30__l1clk | |
712 | ||
713 | `else | |
714 | `define ASI_WMR_VEC_MASK_WR `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.asi_wmr_vec_mask_wr | |
715 | `define NCU_MAN_UCB_C2I_PACKET_DATA0 `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.ncu_man_ucb_c2i_packet_data[0] | |
716 | `define WMR_VEC_MASK `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.wmr_vec_mask | |
717 | `define WAKE_THREAD `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.wake_thread | |
718 | `define NCU_L1CLK `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.l1clk | |
719 | `endif // NCU_GATE | |
720 | ||
721 | forever begin | |
722 | force `ASI_WMR_VEC_MASK_WR = 1; | |
723 | force `NCU_MAN_UCB_C2I_PACKET_DATA0 = 1; | |
724 | force `WMR_VEC_MASK = 1; | |
725 | ||
726 | // get past X to zero | |
727 | if (`WAKE_THREAD !== 0) | |
728 | while (`WAKE_THREAD !== 0) | |
729 | @(negedge `NCU_L1CLK); | |
730 | ||
731 | `PR_ALWAYS ("arg", `ALWAYS, "\nNOTICE - fast_boot is forcing NCU asi_wmr_vec_mask register to set!!!\n"); | |
732 | ||
733 | // wait for first thread to get wake up, then release | |
734 | while (`WAKE_THREAD !== 1) | |
735 | @(negedge `NCU_L1CLK); | |
736 | ||
737 | `PR_ALWAYS ("arg", `ALWAYS, "\nNOTICE - fast_boot is releasing NCU asi_wmr_vec_mask register force (reg still set)!!!\n"); | |
738 | ||
739 | // safely past reset, write has stuck! | |
740 | release `ASI_WMR_VEC_MASK_WR; | |
741 | release `NCU_MAN_UCB_C2I_PACKET_DATA0; | |
742 | release `WMR_VEC_MASK; | |
743 | ||
744 | // Wait for the next power-on reset (if any) | |
745 | @(negedge `TOP.PWRON_RST_L); | |
746 | end // forever begin | |
747 | ||
748 | // do this to just force all the time | |
749 | //force `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_wmr_vec_mask[63:0] = 64'h1; | |
750 | ||
751 | // All done with these text macros, so undefine them | |
752 | `undef ASI_WMR_VEC_MASK_WR | |
753 | `undef NCU_MAN_UCB_C2I_PACKET_DATA0 | |
754 | `undef WMR_VEC_MASK | |
755 | `undef WAKE_THREAD | |
756 | `undef NCU_L1CLK | |
757 | `endif // `ifdef NCURTL | |
758 | `endif // !`ifdef AXIS_TL | |
759 | end | |
760 | end | |
761 | ||
762 | ||
763 | initial begin | |
764 | // do not add anything else in this block!!! | |
765 | // | |
766 | //-------------- | |
767 | // Power Throttle | |
768 | `ifndef PLAYBACK | |
769 | if ($value$plusargs("pwr_throttle=%s", tempstr)) begin // { | |
770 | if (tempstr == "rand" || tempstr == "random") begin // { | |
771 | `TOP.asi_power_throttle = $random(`PARGS.seed); | |
772 | `PR_ALWAYS ("arg", `ALWAYS,"pwr_throttle=static random, asi_power_throttle=%h (cores 0,1,4,5 = %0h/cores 2,3,6,7 = %0h",`TOP.asi_power_throttle,`TOP.asi_power_throttle[2:0],`TOP.asi_power_throttle[5:3]); | |
773 | end // } | |
774 | else if (tempstr == "cycle") begin // { | |
775 | if ($test$plusargs("pwr_throttle_freq")) | |
776 | tmp32 = $value$plusargs("pwr_throttle_freq=%d", asi_power_throttle_freq); | |
777 | if (asi_power_throttle_freq < 2) asi_power_throttle_freq = 3; | |
778 | `PR_ALWAYS ("arg", `ALWAYS,"pwr_throttle=cycle random, pwr_throttle_freq=%0d",asi_power_throttle_freq); | |
779 | `ifdef PALLADIUM | |
780 | // No pwr_throttle switch in FC1 | |
781 | `else | |
782 | while (1) begin | |
783 | `TOP.asi_power_throttle = $random(`PARGS.seed); | |
784 | repeat (asi_power_throttle_freq) @(negedge `CPU.cmp_gclk_c3_spc0); | |
785 | end | |
786 | `endif | |
787 | end // } | |
788 | else if (tempstr == "pulse") begin // { | |
789 | if ($test$plusargs("pwr_throttle_freq")) | |
790 | tmp32 = $value$plusargs("pwr_throttle_freq=%d", asi_power_throttle_freq); | |
791 | if (asi_power_throttle_freq < 2) asi_power_throttle_freq = 3; | |
792 | `PR_ALWAYS ("arg", `ALWAYS,"pwr_throttle=pulse random (return to zero), pwr_throttle_freq=%0d",asi_power_throttle_freq); | |
793 | `ifdef PALLADIUM | |
794 | // No pwr_throttle switch in FC1 | |
795 | `else | |
796 | while (1) begin | |
797 | if (`TOP.asi_power_throttle !== 0) `TOP.asi_power_throttle = 0; | |
798 | else `TOP.asi_power_throttle = $random(`PARGS.seed) + 1; | |
799 | repeat (asi_power_throttle_freq) @(negedge `CPU.cmp_gclk_c3_spc0); | |
800 | end | |
801 | `endif | |
802 | end // } | |
803 | else begin | |
804 | tmp32 = $value$plusargs("pwr_throttle=%d",`TOP.asi_power_throttle); | |
805 | `PR_ALWAYS ("arg", `ALWAYS,"pwr_throttle=%0d",`TOP.asi_power_throttle); | |
806 | end | |
807 | end // } | |
808 | else begin | |
809 | `TOP.asi_power_throttle = 0; | |
810 | end | |
811 | `endif // PLAYBACK | |
812 | end | |
813 | ||
814 | ||
815 | `ifndef FC_SCAN_BENCH | |
816 | `ifndef AXIS_TL | |
817 | `ifndef PLAYBACK | |
818 | // Need to set th_check_enable for all threads that POR .. | |
819 | // (and ONLY at their POR!) | |
820 | initial begin // { | |
821 | ||
822 | // wait... | |
823 | @(posedge `CPU.cmp_gclk_c3_spc0); | |
824 | @(negedge `CPU.cmp_gclk_c3_spc0); | |
825 | `ifdef FC_BENCH | |
826 | `ifndef FC_SCAN_BENCH | |
827 | @(posedge `TOP.flush_reset_complete); | |
828 | `endif | |
829 | `endif | |
830 | ||
831 | // detect saturation and then bail to optimize performance. | |
832 | // NOTE: if a warm reset causes us to go from 16 -> 8 threads running, | |
833 | // th_check_enable will still assume 16 threads are still running. | |
834 | while (`PARGS.th_check_enable[63:0] !== ({{8{`CPU.ncu_spc7_core_enable_status}}, | |
835 | {8{`CPU.ncu_spc6_core_enable_status}}, | |
836 | {8{`CPU.ncu_spc5_core_enable_status}}, | |
837 | {8{`CPU.ncu_spc4_core_enable_status}}, | |
838 | {8{`CPU.ncu_spc3_core_enable_status}}, | |
839 | {8{`CPU.ncu_spc2_core_enable_status}}, | |
840 | {8{`CPU.ncu_spc1_core_enable_status}}, | |
841 | {8{`CPU.ncu_spc0_core_enable_status}}})) begin // { | |
842 | ||
843 | // wait for a change of any core_running bit | |
844 | @(`CPU.ncu_spc0_core_running[7:0] or `CPU.ncu_spc1_core_running[7:0] or | |
845 | `CPU.ncu_spc2_core_running[7:0] or `CPU.ncu_spc3_core_running[7:0] or | |
846 | `CPU.ncu_spc4_core_running[7:0] or `CPU.ncu_spc5_core_running[7:0] or | |
847 | `CPU.ncu_spc6_core_running[7:0] or `CPU.ncu_spc7_core_running[7:0]); | |
848 | ||
849 | // X sanity, it's a good thing | |
850 | if (^(`CPU.ncu_spc0_core_running[7:0] ^ `CPU.ncu_spc1_core_running[7:0] ^ | |
851 | `CPU.ncu_spc2_core_running[7:0] ^ `CPU.ncu_spc3_core_running[7:0] ^ | |
852 | `CPU.ncu_spc4_core_running[7:0] ^ `CPU.ncu_spc4_core_running[7:0] ^ | |
853 | `CPU.ncu_spc6_core_running[7:0] ^ `CPU.ncu_spc5_core_running[7:0]) === 1'bx) begin // { | |
854 | // can't assume dispmon is not disabled | |
855 | $display("ERROR: Thread Check Control th_check_enable=%h core_running=%h X detected!!!", `PARGS.th_check_enable,{`CPU.ncu_spc7_core_running[7:0], | |
856 | `CPU.ncu_spc6_core_running[7:0], | |
857 | `CPU.ncu_spc5_core_running[7:0], | |
858 | `CPU.ncu_spc4_core_running[7:0], | |
859 | `CPU.ncu_spc3_core_running[7:0], | |
860 | `CPU.ncu_spc2_core_running[7:0], | |
861 | `CPU.ncu_spc1_core_running[7:0], | |
862 | `CPU.ncu_spc0_core_running[7:0]}); | |
863 | `PR_ERROR ("arg", `ERROR, "ERROR: Thread Check Control (th_check_enable=%h) core_running X detected!!!", `PARGS.th_check_enable); | |
864 | $finish; | |
865 | end // } | |
866 | ||
867 | // add in additional bits | |
868 | `PARGS.th_check_enable = `PARGS.th_check_enable | {`CPU.ncu_spc7_core_running[7:0], | |
869 | `CPU.ncu_spc6_core_running[7:0], | |
870 | `CPU.ncu_spc5_core_running[7:0], | |
871 | `CPU.ncu_spc4_core_running[7:0], | |
872 | `CPU.ncu_spc3_core_running[7:0], | |
873 | `CPU.ncu_spc2_core_running[7:0], | |
874 | `CPU.ncu_spc1_core_running[7:0], | |
875 | `CPU.ncu_spc0_core_running[7:0]}; | |
876 | `PR_NORMAL ("arg", `NORMAL, "Thread Check Control (th_check_enable) is now 0x%h (core_running changed).", `PARGS.th_check_enable); | |
877 | ||
878 | end // while } | |
879 | `PR_NORMAL ("arg", `NORMAL, "Thread Check Control (th_check_enable) is now 0x%h (saturated, bye).", `PARGS.th_check_enable); | |
880 | end // init } | |
881 | `endif // PLAYBACK | |
882 | `endif | |
883 | `endif | |
884 | ||
885 | //---------------------------------------------------------- | |
886 | // MA monitor | |
887 | initial begin | |
888 | if ($value$plusargs("mamon=%d", mamon)) begin | |
889 | `PR_ALWAYS ("arg", `ALWAYS, "Enabling SPU MA monitor.\n"); | |
890 | end | |
891 | if ($value$plusargs("dec_spu_grant=%d", dec_spu_grant)) begin | |
892 | `PR_ALWAYS ("arg", `ALWAYS, "Enabling random dec_spu_grant_d irritator.\n"); | |
893 | end | |
894 | end | |
895 | ||
896 | //---------------------------------------------------------- | |
897 | // Trap address extraction functions | |
898 | ||
899 | function [6:0] get_good_trap_addr ; | |
900 | input [8*(`TRAP_ADDR_CHARS+1)*`MAX_TRAP_ADDRS:0] instring; | |
901 | reg [`TRAP_ADDR_CHARS*8-1:0] addr_str; | |
902 | reg [`TRAP_ADDR_WIDTH-1:0] address; | |
903 | integer l; | |
904 | begin // { | |
905 | ||
906 | `ifdef PALLADIUM | |
907 | // The following contains some unsynthesizable RTL code. | |
908 | `else | |
909 | get_good_trap_addr = 0; | |
910 | begin : SCAN_INSTRING // { | |
911 | while (instring !== 0) begin // { | |
912 | addr_str = instring[8*`TRAP_ADDR_CHARS-1:0]; | |
913 | instring = instring >> 8*`TRAP_ADDR_CHARS; | |
914 | if (instring[7:0] == ":" || instring[7:0] == 0) begin // { | |
915 | l= $sscanf(addr_str, "%h", address); | |
916 | get_good_trap_addr = get_good_trap_addr+1; | |
917 | `ifdef AXIS_TL | |
918 | good_trap_addr=address; | |
919 | `else | |
920 | good_trap_addr[get_good_trap_addr-1]=address; | |
921 | `endif | |
922 | end // } | |
923 | if (instring[7:0] == ":") instring = instring >> 8; | |
924 | if (instring[7:0] == 0 ) disable SCAN_INSTRING; | |
925 | end // } | |
926 | end // } | |
927 | `endif // !`ifdef PALLADIUM | |
928 | ||
929 | end // } | |
930 | ||
931 | endfunction | |
932 | ||
933 | function [6:0] get_bad_trap_addr ; | |
934 | input [8*(`TRAP_ADDR_CHARS+1)*`MAX_TRAP_ADDRS:0] instring; | |
935 | reg [`TRAP_ADDR_CHARS*8-1:0] addr_str; | |
936 | reg [`TRAP_ADDR_WIDTH-1:0] address; | |
937 | integer l; | |
938 | begin // { | |
939 | ||
940 | `ifdef PALLADIUM | |
941 | // The following contains some unsynthesizable RTL code. | |
942 | `else | |
943 | get_bad_trap_addr = 0; | |
944 | begin : SCAN_INSTRING // { | |
945 | while (instring !== 0) begin // { | |
946 | addr_str = instring[8*`TRAP_ADDR_CHARS-1:0]; | |
947 | instring = instring >> 8*`TRAP_ADDR_CHARS; | |
948 | if (instring[7:0] == ":" || instring[7:0] == 0) begin // { | |
949 | l= $sscanf(addr_str, "%h", address); | |
950 | get_bad_trap_addr = get_bad_trap_addr+1; | |
951 | `ifdef AXIS_TL | |
952 | case (get_bad_trap_addr) | |
953 | 0: $display("No bad trap addresses?"); | |
954 | 1: bad_trap_addr1 = address; | |
955 | 2: bad_trap_addr2 = address; | |
956 | 3: bad_trap_addr3 = address; | |
957 | 4: bad_trap_addr4 = address; | |
958 | default: $display("greater than 4 bad trap addresses not allowed"); | |
959 | endcase | |
960 | `else | |
961 | bad_trap_addr[get_bad_trap_addr-1]=address; | |
962 | `endif | |
963 | end // } | |
964 | if (instring[7:0] == ":") instring = instring >> 8; | |
965 | if (instring[7:0] == 0 ) disable SCAN_INSTRING; | |
966 | end // } | |
967 | end // } | |
968 | ||
969 | `endif // !`ifdef PALLADIUM | |
970 | ||
971 | end // } | |
972 | ||
973 | endfunction | |
974 | ||
975 | ||
976 | ||
977 | ||
978 | //---------------------------------------------------------- | |
979 | function [63:0] get_thread_enables ; | |
980 | input [8*16:0] instring; | |
981 | reg [7:0] char; | |
982 | integer i, j; | |
983 | reg [3:0] nibble; | |
984 | ||
985 | begin | |
986 | get_thread_enables = 64'h0; | |
987 | // if argument is thread=all | |
988 | if (instring == "all") begin | |
989 | get_thread_enables = 64'hffffffff_ffffffff; | |
990 | end | |
991 | // if argument is thread=none | |
992 | else if (instring == "none") begin | |
993 | get_thread_enables = 64'h0; | |
994 | end | |
995 | // if argument is thread=rand | |
996 | else if (instring == "rand" || instring == "random") begin | |
997 | get_thread_enables = {$random(`PARGS.seed),$random(`PARGS.seed)}; | |
998 | end | |
999 | // rest should just be the actual value | |
1000 | else begin | |
1001 | for (i=0; i<16; i=i+1) begin | |
1002 | for (j=0; j<=7; j=j+1) begin | |
1003 | char[j] = instring[8*i+j]; | |
1004 | end | |
1005 | ||
1006 | case (char) | |
1007 | "0" : nibble = 4'b0000; | |
1008 | "1" : nibble = 4'b0001; | |
1009 | "2" : nibble = 4'b0010; | |
1010 | "3" : nibble = 4'b0011; | |
1011 | "4" : nibble = 4'b0100; | |
1012 | "5" : nibble = 4'b0101; | |
1013 | "6" : nibble = 4'b0110; | |
1014 | "7" : nibble = 4'b0111; | |
1015 | "8" : nibble = 4'b1000; | |
1016 | "9" : nibble = 4'b1001; | |
1017 | "a","A" : nibble = 4'b1010; | |
1018 | "b","B" : nibble = 4'b1011; | |
1019 | "c","C" : nibble = 4'b1100; | |
1020 | "d","D" : nibble = 4'b1101; | |
1021 | "e","E" : nibble = 4'b1110; | |
1022 | "f","F" : nibble = 4'b1111; | |
1023 | default : nibble = 4'b0000; | |
1024 | endcase | |
1025 | ||
1026 | get_thread_enables = get_thread_enables | (nibble << (i*4)); | |
1027 | end | |
1028 | end | |
1029 | end | |
1030 | endfunction | |
1031 | //---------------------------------------------------------- | |
1032 | //---------------------------------------------------------- | |
1033 | ||
1034 | `endif |