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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / global_monitor.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: global_monitor.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module global_monitor();
36
37
38`ifndef GATESIM
39
40
41//print out trap type explicitly inside the vcs.log file (XMR signal is taken from the trap logic unit, i.e. TLU)
42
43wire[8:0] trap_type = tb_top.cpu.spc0.tlu.trl0_trap_type[8:0];
44
45always @(trap_type) begin
46 if ((`TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0]) && (trap_type!=0)) begin
47 case (trap_type)
48 9'h1 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" power_on_reset \" ",trap_type); end
49 9'h2 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" watchdog_reset \" ",trap_type); end
50 9'h3 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" externally_initiated_reset \" ",trap_type); end
51 9'h4 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" SW_initiated_reset \" ",trap_type); end
52 9'h5 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" RED_state_exception \" ",trap_type); end
53 9'h7 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" store_error \" ",trap_type); end
54 9'h8 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" Instruction_Access_Exception_privilege_violation \" ",trap_type); end
55 9'h9 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" instruction_access_MMU_miss \" ",trap_type); end
56 9'hA : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" instruction_access_error \" ",trap_type); end
57 9'hB : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" Instruction_Access_Exception_unauth_access \" ",trap_type); end
58 9'hC : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" Instruction_Access_Exception_nfo_page \" ",trap_type); end
59 9'hD : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" instruction_address_range \" ",trap_type); end
60 9'hE : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" instruction_real_range \" ",trap_type); end
61 9'h10 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" illegal_instruction \" ",trap_type); end
62 9'h11 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" privileged_opcode \" ",trap_type); end
63 9'h12 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" unimplemented_LDD \" ",trap_type); end
64 9'h13 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" unimplemented_STD \" ",trap_type); end
65 9'h14 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" Data_Access_Exception_invalid_asi \" ",trap_type); end
66 9'h15 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" Data_Access_Exception_privilege_violation \" ",trap_type); end
67 9'h16 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" Data_Access_Exception_nc_page \" ",trap_type); end
68 9'h17 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" Data_Access_Exception_nfo_page \" ",trap_type); end
69 9'h20 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" fp_disabled \" ",trap_type); end
70 9'h21 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" fp_exception_ieee_754 \" ",trap_type); end
71 9'h22 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" fp_exception_other \" ",trap_type); end
72 9'h23 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" tag_overflow \" ",trap_type); end
73 9'h24,9'h25,9'h26,9'h27 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" clean_window \" ",trap_type); end
74 9'h28 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" division_by_zero \" ",trap_type); end
75 9'h29 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" internal_processor_error \" ",trap_type); end
76 9'h2A : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" instruction_invalid_TSB_entry \" ",trap_type); end
77 9'h2B : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" data_invalid_TSB_entry \" ",trap_type); end
78 9'h2D : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" mem_real_range \" ",trap_type); end
79 9'h2E : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" mem_address_range \" ",trap_type); end
80 9'h30 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" Data_Access_Exception_so_page \" ",trap_type); end
81 9'h31 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" data_access_MMU_miss \" ",trap_type); end
82 9'h32 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" data_access_error \" ",trap_type); end
83 9'h33 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" data_access_protection \" ",trap_type); end
84 9'h34 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" mem_address_not_aligned \" ",trap_type); end
85 9'h35 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" LDDF_mem_address_not_aligned \" ",trap_type); end
86 9'h36 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" STDF_mem_address_not_aligned \" ",trap_type); end
87 9'h37 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" privileged_action \" ",trap_type); end
88 9'h38 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" LDQF_mem_address_not_aligned \" ",trap_type); end
89 9'h39 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" STQF_mem_addess_not_aligned \" ",trap_type); end
90 9'h3B : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" unsupported_page_size \" ",trap_type); end
91 9'h3C : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" control_word_queue_interrupt \" ",trap_type); end
92 9'h3D : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" modular_arithmetic_interrupt \" ",trap_type); end
93 9'h3E : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" inst_real_translation_miss \" ",trap_type); end
94 9'h3F : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" data_real_translation_miss \" ",trap_type); end
95 9'h40 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" SW_recoverable_error \" ",trap_type); end
96 9'h41 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_1 \" ",trap_type); end
97 9'h42 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_2 \" ",trap_type); end
98 9'h43 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_3 \" ",trap_type); end
99 9'h44 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_4 \" ",trap_type); end
100 9'h45 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_5 \" ",trap_type); end
101 9'h46 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_6 \" ",trap_type); end
102 9'h47 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_7 \" ",trap_type); end
103 9'h48 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_8 \" ",trap_type); end
104 9'h49 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_9 \" ",trap_type); end
105 9'h4A : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_10 \" ",trap_type); end
106 9'h4B : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_11 \" ",trap_type); end
107 9'h4C : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_12 \" ",trap_type); end
108 9'h4D : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_13 \" ",trap_type); end
109 9'h4E : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_level_14 \" ",trap_type); end
110 9'h4F : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" pic_overflow (interrupt_level_15) \" ",trap_type); end
111 9'h5E : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" hstick_match \" ",trap_type); end
112 9'h5F : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" trap_level_zero \" ",trap_type); end
113 9'h60 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" interrupt_vector_trap \" ",trap_type); end
114 9'h61 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" PA_watchpoint \" ",trap_type); end
115 9'h62 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" VA_watchpoint \" ",trap_type); end
116 9'h63 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HW_corrected_error \" ",trap_type); end
117 9'h64 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" fast_instruction_access_MMU_miss \" ",trap_type); end
118 9'h68 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" fast_data_access_MMU_miss \" ",trap_type); end
119 9'h6C : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" fast_data_access_protection \" ",trap_type); end
120 9'h71 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" instruction_access_MMU_error \" ",trap_type); end
121 9'h72 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" data_access_MMU_error \" ",trap_type); end
122 9'h74 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" control_transfer_instruction \" ",trap_type); end
123 9'h75 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" instruction_VA_watchpoint \" ",trap_type); end
124 9'h76 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" instruction_breakpoint \" ",trap_type); end
125 9'h7C : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" cpu_mondo_trap \" ",trap_type); end
126 9'h7D : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" dev_mondo_trap \" ",trap_type); end
127 9'h7E : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" resumable_error \" ",trap_type); end
128 9'h7F : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" nonresumable_error (generated by SW only) \" ",trap_type); end
129 9'h80 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_0_normal \" ",trap_type); end
130 9'h84 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_1_normal \" ",trap_type); end
131 9'h88 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_2_normal \" ",trap_type); end
132 9'h8C : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_3_normal \" ",trap_type); end
133 9'h90 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_4_normal \" ",trap_type); end
134 9'h94 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_5_normal \" ",trap_type); end
135 9'h98 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_6_normal \" ",trap_type); end
136 9'h9C : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_7_normal \" ",trap_type); end
137 9'hA0 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_0_other \" ",trap_type); end
138 9'hA4 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_1_other \" ",trap_type); end
139 9'hA8 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_2_other \" ",trap_type); end
140 9'hAC : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_3_other \" ",trap_type); end
141 9'hB0 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_4_other \" ",trap_type); end
142 9'hB4 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_5_other \" ",trap_type); end
143 9'hB8 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_6_other \" ",trap_type); end
144 9'hBC : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window spill_7_other \" ",trap_type); end
145 9'hC0 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_0_normal \" ",trap_type); end
146 9'hC4 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_1_normal \" ",trap_type); end
147 9'hC8 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_2_normal \" ",trap_type); end
148 9'hCC : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_3_normal \" ",trap_type); end
149 9'hD0 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_4_normal \" ",trap_type); end
150 9'hD4 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_5_normal \" ",trap_type); end
151 9'hD8 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_6_normal \" ",trap_type); end
152 9'hDC : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_7_normal \" ",trap_type); end
153 9'hE0 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_0_other \" ",trap_type); end
154 9'hE4 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_1_other \" ",trap_type); end
155 9'hE8 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_2_other \" ",trap_type); end
156 9'hEC : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_3_other \" ",trap_type); end
157 9'hF0 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_4_other \" ",trap_type); end
158 9'hF4 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_5_other \" ",trap_type); end
159 9'hF8 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_6_other \" ",trap_type); end
160 9'hFC : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" window fill_7_other \" ",trap_type); end
161 //9'h100-9'h17F : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" trap_instruction \" ",trap_type); end
162 9'h100 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 GoodTrap \" ",trap_type); end
163 9'h101 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 BadTrap \" ",trap_type); end
164 9'h102 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 ChangePriv \" ",trap_type); end
165 9'h103 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 ChangeNonPriv \" ",trap_type); end
166 9'h104 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 ChangeToTL1 \" ",trap_type); end
167 9'h105 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 ChangeToTL0 \" ",trap_type); end
168 9'h106 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 ChangeToTL0 \" ",trap_type); end
169 9'h107 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 ChangeToTL0 \" ",trap_type); end
170 9'h108 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 TrapEn \" ",trap_type); end
171 9'h10A : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 TrapDis \" ",trap_type); end
172 9'h10C : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 TrapEn_Ntimes \" ",trap_type); end
173 9'h110 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 PThreadMutexLock \" ",trap_type); end
174 9'h111 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 ChangeToTL0 \" ",trap_type); end
175 9'h114 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 PThreadMutexUnLock \" ",trap_type); end
176 9'h116 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 Trap_Sync \" ",trap_type); end
177 9'h118 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 Trap_SysCall \" ",trap_type); end
178 9'h11A : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 Trap_SysRet \" ",trap_type); end
179 9'h120 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 HTrap_ChangePriv \" ",trap_type); end
180 9'h122 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 HTrap_ChangeNonPriv \" ",trap_type); end
181 9'h124 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 HTrapEn \" ",trap_type); end
182 9'h126 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 HTrapDis \" ",trap_type); end
183 9'h128 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 HTrapEn_Ntimes \" ",trap_type); end
184 9'h12A : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 ChangeCtx \" ",trap_type); end
185 9'h12C : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 Dummy \" ",trap_type); end
186 9'h12E : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" T0 RdThId \" ",trap_type); end
187 //9'h180-9'h1FF : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" htrap_instruction \" ",trap_type); end
188 9'h180 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HT0 ChangePriv \" ",trap_type); end
189 9'h182 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HT0 ChangeNonPriv \" ",trap_type); end
190 9'h184 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HT0 TrapEn \" ",trap_type); end
191 9'h186 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HT0 TrapDis \" ",trap_type); end
192 9'h188 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HT0 TrapEn_Ntimes \" ",trap_type); end
193 9'h18A : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HT0 ChangeCtx \" ",trap_type); end
194 9'h18E : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HT0 RdThId \" ",trap_type); end
195 9'h1A0 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HT0 GoodTrap \" ",trap_type); end
196 9'h1A1 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" HT0 BadTrap \" ",trap_type); end
197 default : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TRAP TAKEN : TT is 0x%h \" RESERVED! \" ",trap_type); end
198 endcase
199 end
200end
201
202
203
204//print out status from each of the core ESRs
205
206
207wire [2:0] isfsr_errtype = tb_top.cpu.spc0.tlu.asi.isfsr_data[2:0] ;
208wire [3:0] dsfsr_errtype = tb_top.cpu.spc0.tlu.asi.dsfsr_data[3:0] ;
209wire [47:0] dsfar_erraddr = tb_top.cpu.spc0.tlu.asi.dsfar_data[47:0] ;
210wire [4:0] desr_errtype = tb_top.cpu.spc0.tlu.asi.desr_data[60:56] ;
211wire [10:0] desr_erraddr = tb_top.cpu.spc0.tlu.asi.desr_data[10:0] ;
212wire desr_61 = tb_top.cpu.spc0.tlu.asi.desr_data[61];
213
214
215
216always @(isfsr_errtype) begin
217 if ((`TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0]) && (isfsr_errtype!=0) && (trap_type!=0)) begin
218 case (isfsr_errtype)
219 3'h1 : begin
220 if (trap_type == 9'h9) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- ISFSR [2:0] is 0x%h \" (ITTM) IT Tag Multiple hit \" ",trap_type,isfsr_errtype); end
221 else if (trap_type == 9'hA) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- ISFSR [2:0] is 0x%h \" (ICL2U) IC L2 Uncorrectable \" ",trap_type,isfsr_errtype); end
222 end
223 3'h2 : begin
224 if (trap_type == 9'h9) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- ISFSR [2:0] is 0x%h \" (ITTP) IT Tag Parity \" ",trap_type,isfsr_errtype); end
225 else if (trap_type == 9'hA) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- ISFSR [2:0] is 0x%h \" (ICL2ND) IC L2 NotData \" ",trap_type,isfsr_errtype); end
226 end
227 3'h3 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- ISFSR [2:0] is 0x%h \" (ITDP) IT Data Parity \" ",trap_type,isfsr_errtype); end
228 3'h4 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- ISFSR [2:0] is 0x%h \" (ITMU) IT MRA Uncorrectable \" ",trap_type,isfsr_errtype); end
229 3'h5 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- ISFSR [2:0] is 0x%h \" (ITL2U) IT L2 Uncorrectable \" ",trap_type,isfsr_errtype); end
230 3'h6 : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- ISFSR [2:0] is 0x%h \" (ITL2ND) IT L2 NotData \" ",trap_type,isfsr_errtype); end
231 default : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- ISFSR [2:0] is 0x%h \" UNDEFINED! \" ",trap_type,isfsr_errtype); end
232 endcase
233 end
234end
235
236
237
238always @(dsfsr_errtype) begin
239 if ((`TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0]) && (dsfsr_errtype!=0) && (trap_type!=0)) begin
240 case (dsfsr_errtype)
241 4'h1 : begin
242 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (IRFU) Integer register file uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
243 else if (trap_type == 9'h31) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (DTTM) DT tag multiple hit \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
244 else if (trap_type == 9'h32) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (DCL2U) data cache L2 uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
245 end
246 4'h2 : begin
247 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (IRFC) Integer register file correctable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
248 else if (trap_type == 9'h31) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (DTTP) DT tag parity \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
249 else if (trap_type == 9'h32) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (DCL2ND) data cache L2 NotData \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
250 end
251 4'h3 : begin
252 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (FRFU) FP register file uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
253 else if (trap_type == 9'h31) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (DTDP) DT data parity \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
254 end
255 4'h4 : begin
256 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (FRFC) FP register file correctable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
257 else if (trap_type == 9'h31) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (DTMU) DT MRA uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
258 else if (trap_type == 9'h32) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (SOCU) SOC uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
259 end
260 4'h5 : begin
261 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (SBDLC) Store buffer data load hit correctable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
262 else if (trap_type == 9'h31) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (DTL2U) DT L2 uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
263 end
264 4'h6 : begin
265 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (SBDLU) Store buffer data load hit uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
266 else if (trap_type == 9'h31) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (DTL2ND) DT L2 NotData \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
267 end
268 4'h7 : begin
269 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (MRAU) MRA uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
270 end
271 4'h8 : begin
272 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (TSAC) TSA correctable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
273 end
274 4'h9 : begin
275 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (TSAU) TSA uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
276 end
277 4'hA : begin
278 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (SCAC) SCA correctable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
279 end
280 4'hB : begin
281 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (SCAU) SCA uncorrectable \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
282 end
283 4'hC : begin
284 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (TCCP) Tick compare correctable precise \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
285 end
286 4'hD : begin
287 if (trap_type == 9'h29) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" (TCUP) Tick compare uncorrectable precise \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
288 end
289 default : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DSFSR [3:0] is 0x%h --- DSFAR [47:0] is 0x%h \" UNDEFINED! \" ",trap_type,dsfsr_errtype,dsfar_erraddr); end
290 endcase
291 end
292end
293
294
295always @(desr_errtype) begin
296 if ((`TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0]) && (desr_errtype!=0) && (trap_type!=0)) begin
297 case (desr_errtype)
298 5'h1 : begin
299 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (ITL2C) IT L2 correctable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
300 else if ( (trap_type == 9'h63) && (desr_erraddr == 11'h4) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (ICVP) Instruction cache valid bit parity \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
301 end
302 5'h2 : begin
303 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (ICL2C) IC L2 correctable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
304 else if ( (trap_type == 9'h63) && (desr_erraddr == 11'h4) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (ICTP) Instruction cache tag parity \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
305 end
306 5'h3 : begin
307 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (DTL2C) DT L2 correctable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
308 else if ( (trap_type == 9'h63) && (desr_erraddr == 11'h4) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (ICTM) Instruction cache tag multiple \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
309 end
310 5'h4 : begin
311 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (DCL2C) DC L2 correctable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
312 else if ( (trap_type == 9'h63) && (desr_erraddr == 11'h4) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (ICDP) Instruction cache data parity \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
313 end
314 5'h5 : begin
315 if ( (trap_type == 9'h63) && (desr_erraddr == 11'h5) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (DCVP) Data cache valid bit parity \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
316 end
317 5'h6 : begin
318 if ( (trap_type == 9'h63) && (desr_erraddr == 11'h5) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (DCTP) Data cache tag parity \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
319 else if ( (trap_type == 9'h40) && (desr_erraddr == 11'h6) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (SBDPU) Store buffer data PCX read uncorrectable ECC \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
320 end
321 5'h7 : begin
322 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h14) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (MAMU) MA memory uncorrectable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
323 else if ( (trap_type == 9'h63) && (desr_erraddr == 11'h5) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (DCTM) Data cache tag multiple \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
324 end
325 5'h8 : begin
326 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (MAL2C) MA L2 read correctable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
327 else if ( (trap_type == 9'h63) && (desr_erraddr == 11'h5) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (DCDP) Data cache data parity \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
328 end
329 5'h9 : begin
330 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (MAL2U) MA L2 read uncorrectable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
331 else if ( (trap_type == 9'h63) && (desr_erraddr == 11'h6) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (L2C) L2 cache correctable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
332 end
333 5'hA : begin
334 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (MAL2ND) MA L2 read NotData \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
335 else if ( (trap_type == 9'h63) && (desr_erraddr == 11'h6) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (SBDPC) Store buffer data PCX read correctable ECC \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
336 end
337 5'hB : begin
338 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (CWQL2C) CWQ L2 read correctable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
339 else if (trap_type == 9'h63) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (SOCC) SOC correctable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
340 end
341 5'hC : begin
342 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (CWQL2U) CWQ L2 read uncorrectable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
343 end
344 5'hD : begin
345 if ( (trap_type == 9'h40 ) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (CWQL2ND) CWQ L2 read NotData \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
346 end
347 5'hE : begin
348 if ( (trap_type == 9'h63) && (desr_erraddr == 11'h13) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (TCCD) Tick_compare correctable disrupting \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
349 end
350 5'hF : begin
351 if ( (trap_type == 9'h63) && (desr_erraddr == 11'h13) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (TCUD) Tick_compare uncorrectable disrupting \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
352 end
353 5'h10 : begin
354 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (L2U) L2 uncorrectable ECC error \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
355 end
356 5'h11 : begin
357 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (L2ND) L2 NotData error \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
358 end
359 5'h13 : begin
360 if (trap_type == 9'h40) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (SOCU) SOC uncorrectable \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
361 end
362 5'h14 : begin
363 if ( (trap_type == 9'h40) && (desr_erraddr == 11'h3) ) begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" (L2C) L2 correctable ECC error \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
364 end
365 default : begin `PR_ALWAYS("global_monitor", `ALWAYS, " *** TT is 0x%h --- DESR [61] is %b --- DESR [60:56] is 0x%h --- DESR [10:0] is 0x%h \" UNDEFINED! \" ",trap_type,desr_61,desr_errtype,desr_erraddr); end
366 endcase
367 end
368end
369
370
371//***************************************************************************************************
372//***************************************************************************************************
373wire drl2clk=`MCU0.drl2clk;
374
375// new fullchip ecc injector written since original injector :/verif/env/mcu/amb_dram_err_inject.v
376// works only on return packets from dram. this injector injects on both ingoing QWs as well as the return QWs
377
378wire mcu0_esr_dac = `MCU0.drif.rdpctl_err_sts_reg[23];
379wire mcu1_esr_dac = `MCU1.drif.rdpctl_err_sts_reg[23];
380wire mcu2_esr_dac = `MCU2.drif.rdpctl_err_sts_reg[23];
381wire mcu3_esr_dac = `MCU3.drif.rdpctl_err_sts_reg[23];
382
383wire mcu0_esr_dau = `MCU0.drif.rdpctl_err_sts_reg[22];
384wire mcu1_esr_dau = `MCU1.drif.rdpctl_err_sts_reg[22];
385wire mcu2_esr_dau = `MCU2.drif.rdpctl_err_sts_reg[22];
386wire mcu3_esr_dau = `MCU3.drif.rdpctl_err_sts_reg[22];
387
388wire mcu0_esr_dsc = `MCU0.drif.rdpctl_err_sts_reg[21];
389wire mcu1_esr_dsc = `MCU1.drif.rdpctl_err_sts_reg[21];
390wire mcu2_esr_dsc = `MCU2.drif.rdpctl_err_sts_reg[21];
391wire mcu3_esr_dsc = `MCU3.drif.rdpctl_err_sts_reg[21];
392
393wire mcu0_esr_dsu = `MCU0.drif.rdpctl_err_sts_reg[20];
394wire mcu1_esr_dsu = `MCU1.drif.rdpctl_err_sts_reg[20];
395wire mcu2_esr_dsu = `MCU2.drif.rdpctl_err_sts_reg[20];
396wire mcu3_esr_dsu = `MCU3.drif.rdpctl_err_sts_reg[20];
397
398 reg one_nibble_error=0;
399 reg multi_nibble_error=0;
400 reg random_nibble_error=0;
401reg on_ecc_bits_only=0; reg on_write_only=0;
402integer quadword=1;
403integer flip=1;
404
405initial begin
406 if ($test$plusargs("ONE_NIBBLE_ERROR")) begin
407 one_nibble_error = 1;
408 end
409 else if ($test$plusargs("MULTI_NIBBLE_ERROR")) begin
410 multi_nibble_error = 1;
411 end
412 else if ($test$plusargs("RANDOM_NIBBLE_ERROR")) begin
413 random_nibble_error = 1;
414 end
415if ($test$plusargs("ON_ECC_NEW")) on_ecc_bits_only=1;
416if ($test$plusargs("ON_WRITE_NEW")) on_write_only=1;
417if ($value$plusargs("QUADWORD_NEW=%d",quadword) && (one_nibble_error || multi_nibble_error ) )
418 begin
419 if ( (quadword<1) || (quadword>4) ) `PR_ERROR ("global_monitor", `ERROR, "can only specify 1,2,3 or 4!");
420 if (one_nibble_error==1)
421 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: will inject ECC CE on quadword %d",quadword);
422 else if (multi_nibble_error==1)
423 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: will inject ECC UE on quadword %d",quadword);
424 end
425else if ($test$plusargs("RANDOM_QUADWORD_NEW") && (one_nibble_error || multi_nibble_error ) )
426 begin
427 quadword=({$random}%4)+1;
428 if (one_nibble_error==1)
429 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: will randomly select 1st/2nd/3rd/4th quadword for injecting CE!");
430 else if (multi_nibble_error==1)
431 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: will randomly select 1st/2nd/3rd/4th quadword for injecting UE!");
432 end
433if ( $value$plusargs("FLIP_NEW=%d",flip) && (one_nibble_error || multi_nibble_error ) )
434 begin
435 if ( (flip<1) || (flip>4) ) `PR_ERROR ("global_monitor", `ERROR, "can only specify 1,2,3 or 4!");
436 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: will FLIP %d bits in nibble",flip);
437 end
438else if ( $test$plusargs("RANDOM_FLIP_NEW") && (one_nibble_error || multi_nibble_error ) )
439 begin
440 flip=({$random}%4)+1;
441 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: will randomly FLIP 1/2/3/4 bits in nibble!");
442 end
443
444end
445
446//end of bootcode
447reg passed_bootEnd_mask=0;
448 always @( `TOP.gOutOfBoot[63:0] ) begin
449 if (!passed_bootEnd_mask && (`TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0]) ) begin
450 repeat (1000) @ (posedge drl2clk); // wait until 1000 cycles after bootEnd, then start injecting
451 passed_bootEnd_mask=1;
452 end
453 end
454
455integer delay_ecc_new;
456initial
457 if (!$value$plusargs("DELAY_ECC_NEW=%d",delay_ecc_new)) delay_ecc_new=6;
458
459integer ce_count=0;
460integer ue_count=0;
461
462//READ
463wire [143:0]mcu0_rddata0 = `MCU0.fbdird0_data[143:0];
464wire [143:0]mcu0_rddata1 = `MCU0.fbdird1_data[143:0];
465reg [143:0] mcu0_rddata0_corrupted=144'b0 ;
466reg [143:0] mcu0_rddata1_corrupted=144'b0 ;
467
468reg [31:0] random;
469integer rddata_count=0;
470
471always @( posedge `MCU0.fbdic_rddata_vld ) begin
472if (passed_bootEnd_mask==1) begin
473if (one_nibble_error || multi_nibble_error || random_nibble_error) begin
474 rddata_count=rddata_count+1;
475 if ((rddata_count % delay_ecc_new==1) && !on_write_only && (!mcu0_esr_dac && !mcu0_esr_dau)) begin
476
477 if(random_nibble_error) begin
478 random={$random}%2;
479 if(random[0]) begin
480 one_nibble_error = 1'b1;
481 multi_nibble_error = 1'b0;
482 end
483 else begin
484 one_nibble_error = 1'b0;
485 multi_nibble_error = 1'b1;
486 end
487 end
488
489 if (one_nibble_error) ce_count=ce_count+1;
490 else if (multi_nibble_error) ue_count=ue_count+1;
491
492 if (quadword==1 && !(mcu0_rddata0[143:128] == 16'hffff) ) begin
493 mcu0_rddata0_corrupted = quadword_inject ( mcu0_rddata0, one_nibble_error, multi_nibble_error, on_ecc_bits_only, flip,ce_count,ue_count );
494 force `MCU0.fbdird0_data[143:0] = mcu0_rddata0_corrupted [143:0];
495 end
496 else if (quadword==2 && !(mcu0_rddata1[143:128] == 16'hffff) ) begin
497 mcu0_rddata1_corrupted = quadword_inject ( mcu0_rddata1, one_nibble_error, multi_nibble_error, on_ecc_bits_only, flip,ce_count,ue_count );
498 force `MCU0.fbdird1_data[143:0] = mcu0_rddata1_corrupted [143:0];
499 end
500
501 @(posedge drl2clk);
502 if (quadword==3 && !(mcu0_rddata0[143:128] == 16'hffff) ) begin
503 mcu0_rddata0_corrupted = quadword_inject ( mcu0_rddata0, one_nibble_error, multi_nibble_error, on_ecc_bits_only, flip,ce_count,ue_count );
504 force `MCU0.fbdird0_data[143:0] = mcu0_rddata0_corrupted [143:0];
505 end
506 else if (quadword==4 && !(mcu0_rddata1[143:128] == 16'hffff) ) begin
507 mcu0_rddata1_corrupted = quadword_inject ( mcu0_rddata1, one_nibble_error, multi_nibble_error, on_ecc_bits_only, flip,ce_count,ue_count );
508 force `MCU0.fbdird1_data[143:0] = mcu0_rddata1_corrupted [143:0];
509 end
510
511 repeat (10) @ (posedge drl2clk); //hold it for 10 clocks, then release it
512 release `MCU0.fbdird0_data[143:0];
513 release `MCU0.fbdird1_data[143:0];
514end
515end
516end
517end
518
519//WRITE
520wire [143:0] mcu0_wdata = `MCU0.fbdiwr.wrdp_data[143:0];
521reg [143:0] mcu0_wdata_corrupted=144'b0 ;
522
523integer wdata_count=0;
524
525always @( `MCU0.drif.drif_dram_cmd_b[2:0] ) begin
526if (passed_bootEnd_mask==1) begin
527if (one_nibble_error || multi_nibble_error || random_nibble_error) begin
528if ( `MCU0.drif.drif_dram_cmd_b[2:0]==3'h5) begin
529 wdata_count=wdata_count+1;
530 if ( (wdata_count % delay_ecc_new==1) && on_write_only && ( !mcu0_esr_dac && !mcu0_esr_dau && !mcu0_esr_dsc && !mcu0_esr_dsu ) ) begin
531
532 if(random_nibble_error) begin
533 random={$random}%2;
534 if(random[0]) begin
535 one_nibble_error = 1'b1;
536 multi_nibble_error = 1'b0;
537 end
538 else begin
539 one_nibble_error = 1'b0;
540 multi_nibble_error = 1'b1;
541 end
542 end
543
544 if (one_nibble_error) ce_count=ce_count+1;
545 else if (multi_nibble_error) ue_count=ue_count+1;
546
547 @(posedge drl2clk) ; // this 1 clock delay is necessary to get data
548 if (quadword==1 && !(mcu0_wdata[143:128] == 16'hffff)) begin
549 mcu0_wdata_corrupted = quadword_inject ( mcu0_wdata, one_nibble_error, multi_nibble_error, on_ecc_bits_only, flip,ce_count,ue_count );
550 #1 force `MCU0.fbdiwr.wrdp_data[143:0] = mcu0_wdata_corrupted[143:0];
551 end
552 @(posedge drl2clk) ;
553 if (quadword==2 && !(mcu0_wdata[143:128] == 16'hffff)) begin
554 mcu0_wdata_corrupted = quadword_inject ( mcu0_wdata, one_nibble_error, multi_nibble_error, on_ecc_bits_only, flip,ce_count,ue_count );
555 #1 force `MCU0.fbdiwr.wrdp_data[143:0] = mcu0_wdata_corrupted[143:0];
556 end
557 @(posedge drl2clk) ;
558 if (quadword==3 && !(mcu0_wdata[143:128] == 16'hffff)) begin
559 mcu0_wdata_corrupted = quadword_inject ( mcu0_wdata, one_nibble_error, multi_nibble_error, on_ecc_bits_only, flip,ce_count,ue_count );
560 #1 force `MCU0.fbdiwr.wrdp_data[143:0] = mcu0_wdata_corrupted[143:0];
561 end
562 @(posedge drl2clk) ;
563 if (quadword==4 && !(mcu0_wdata[143:128] == 16'hffff)) begin
564 mcu0_wdata_corrupted = quadword_inject ( mcu0_wdata, one_nibble_error, multi_nibble_error, on_ecc_bits_only, flip,ce_count,ue_count );
565 #1 force `MCU0.fbdiwr.wrdp_data[143:0] = mcu0_wdata_corrupted[143:0];
566 end
567
568 repeat (10) @ (posedge drl2clk); //hold it for 10 clocks, then release it
569 release `MCU0.fbdiwr.wrdp_data[143:0];
570end
571end
572end
573end
574end
575
576
577function [143:0] quadword_inject;
578input[143:0] data;
579input one_nibble_error;
580input multi_nibble_error;
581input on_ecc_bits_only;
582input [31:0] flip;
583input [31:0] ce_count;
584input [31:0] ue_count;
585reg [4:0] nibble_error_position1;
586reg [4:0] nibble_error_position2;
587reg [3:0] ecc_error_position1;
588reg [3:0] ecc_error_position2;
589reg [127:0]tmp_data;
590reg [15:0]tmp_ecc;
591reg [3:0] calc_flipbits_out;
592
593begin
594 if (one_nibble_error)
595 begin
596 if (!on_ecc_bits_only) begin //inject on data bits only
597 nibble_error_position1 = {$random}%32; // 32 data nibbles
598
599 calc_flipbits_out=calc_flipbits(flip);
600 tmp_data=(calc_flipbits_out << (4*nibble_error_position1));
601 quadword_inject = data ^ { {16{1'b0}}, tmp_data };
602 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: Injected CE DATA error no. %d (nibble is %d, %d bits/nibble flipped, nibble config is %4b) --> orig. data [143:0] was %x, modif. data [143:0] is %x",ce_count,nibble_error_position1,flip,calc_flipbits_out,data,quadword_inject);
603 end
604 else begin //inject on ecc bits only
605 ecc_error_position1 = {$random}%16; // 16 ECC bits
606
607 tmp_ecc=(1 << ecc_error_position1);
608 quadword_inject = data ^ { tmp_ecc, {128{1'b0}} };
609 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: Injected CE ECC error no. %d (ecc bit flipped is %d) --> orig. data [143:0] was %x, modif. data [143:0] is %x",ce_count,ecc_error_position1,data,quadword_inject);
610 end
611 end
612 else if(multi_nibble_error)
613 begin
614 if (!on_ecc_bits_only) begin //inject on data bits only
615 nibble_error_position1 = {$random}%32;
616 nibble_error_position2 = {$random}%32;
617 while ( (nibble_error_position2 == nibble_error_position1) || (nibble_error_position2 < nibble_error_position1) )
618 nibble_error_position2 = {$random}%32;
619
620 calc_flipbits_out=calc_flipbits(flip);
621 tmp_data=(calc_flipbits_out << (4*nibble_error_position1));
622 tmp_data=(tmp_data | (calc_flipbits_out << (4*nibble_error_position2)));
623 quadword_inject = data ^ { {16{1'b0}}, tmp_data };
624 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: Injected UE DATA error no. %d (nibbles are %d and %d, %d bits/nibble flipped, nibble config is %4b) --> orig. data [143:0] was %x, modif. data [143:0] is %x",ue_count,nibble_error_position1,nibble_error_position2,flip,calc_flipbits_out,data,quadword_inject);
625 end
626 else begin //inject on ecc bits only
627 ecc_error_position1 = {$random}%16;
628 ecc_error_position2 = {$random}%16;
629 while ( (ecc_error_position2 == ecc_error_position1) || (ecc_error_position2 < ecc_error_position1) ||
630 ( (ecc_error_position2 > ecc_error_position1) && (ecc_error_position2 - ecc_error_position1 <4) ) )
631 ecc_error_position2 = {$random}%16;
632
633 tmp_ecc=(1 << ecc_error_position1);
634 tmp_ecc=(tmp_ecc | (1 << ecc_error_position2));
635 quadword_inject = data ^ { tmp_ecc, {128{1'b0}} };
636 `PR_ALWAYS ("global_monitor", `ALWAYS, "INFO: Injected UE ECC error no. %d (ecc bits flipped are %d and %d,i.e. placed 4 bits apart) --> orig. data [143:0] was %x, modif. data [143:0] is %x",ue_count,ecc_error_position1,ecc_error_position2,data,quadword_inject);
637 end
638 end
639
640end
641endfunction
642
643function [3:0] calc_flipbits;
644input [31:0] flip;
645integer i;
646begin
647 case (flip)
648 1: begin
649 i=({$random}%4)+1;
650 case (i)
651 1: calc_flipbits=4'b0001;
652 2: calc_flipbits=4'b0010;
653 3: calc_flipbits=4'b0100;
654 4: calc_flipbits=4'b1000;
655 default: calc_flipbits=4'b0001;
656 endcase
657 end
658 2: begin
659 i=({$random}%6)+1;
660 case (i)
661 1: calc_flipbits=4'b0011;
662 2: calc_flipbits=4'b0101;
663 3: calc_flipbits=4'b1001;
664 4: calc_flipbits=4'b0110;
665 5: calc_flipbits=4'b1010;
666 6: calc_flipbits=4'b1100;
667 default: calc_flipbits=4'b0011;
668 endcase
669 end
670 3: begin
671 i=({$random}%4)+1;
672 case (i)
673 1: calc_flipbits=4'b0111;
674 2: calc_flipbits=4'b1011;
675 3: calc_flipbits=4'b1101;
676 4: calc_flipbits=4'b1110;
677 default: calc_flipbits=4'b0111;
678 endcase
679 end
680 4: calc_flipbits=4'b1111;
681 endcase
682end
683endfunction
684
685//***************************************************************************************************
686//***************************************************************************************************
687
688`endif //GATESIM
689
690endmodule
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