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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fc_common.config | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #if defined(AXIS_BUILD) || defined(AXIS_COSIM) | |
36 | -vcs_run_args=+dispmon_disable | |
37 | -vera_build_args="NO_0INMGR=1" | |
38 | -config_rtl=AXIS | |
39 | -sunv_args=-keepSectionSym=AXIS_SMEM | |
40 | -sunv_args=-keepSectionSym=EMUL_COSIM | |
41 | -sunv_args=-keepSectionSym=AXIS_EMUL_COSIM | |
42 | -vcs_build_args=+define+DISABLE_TID_CHKR | |
43 | -nouse_oolm | |
44 | -vcs_run_args=+fbdimm_nb_witdh_capability=1f | |
45 | -vcs_build_args=+define+ALL_DUMP_OFF | |
46 | -novcs_use_fsdb | |
47 | #ifndef AXIS_TL | |
48 | -vcs_build_args=-P $VERA_HOME/lib/vera_pli.tab | |
49 | -vcs_build_args=$VERA_HOME/lib/libSysSciTask.a | |
50 | #endif | |
51 | -vcs_build_args="-pl -lsocket -pl -lnsl -pl -lintl -pl -ldl " | |
52 | -vcs_build_args=+v2000 | |
53 | -vcs_build_args=+tran | |
54 | -vcs_build_args=+tran_force | |
55 | -vcs_build_args="-Z $DV_ROOT/verif/model/verilog/mem/dram/axis_sram.v" | |
56 | -axis_build_args=" -scope n2_fc -map_udp " | |
57 | -novcs_use_vcsd | |
58 | #ifndef AXIS_NO_IP | |
59 | -axis_build_args=" -vms_excl delay_n+delay_n_w_stalling+niu_smx_regfl+dmu_common_simple_fifo+fflp_flow_fifo+n2_iom_sp_2048b_cust+n2_iom_sp_1024b_cust" | |
60 | #endif | |
61 | #ifdef AXIS_USE_MC | |
62 | -vcs_build_args=" +mcexcl+dc_panel_array+cmp_sat +mcminsize+64 +rtlmemsize+20000 " | |
63 | #else | |
64 | -axis_build_args=" -no_mc -run_vms " | |
65 | #endif | |
66 | #ifndef AXIS_TL | |
67 | -axis_build_args=" -vms_excl wiz6c2b8n5d2t " | |
68 | #endif | |
69 | -vcs_build_args="-Z $DV_ROOT/verif/env/fc/axis_hacks.v" | |
70 | #endif | |
71 | #ifdef FASTER_AXIS | |
72 | -vcs_build_args=+define+FAST_AXIS | |
73 | #endif | |
74 | ||
75 | #ifdef AXIS_64BIT | |
76 | -vcs_build_args=+vlg64 | |
77 | #endif | |
78 | #ifdef CPU_TGL_COV | |
79 | -vcs_cm_args=tgl | |
80 | -vcs_cm_config=$DV_ROOT/verif/env/fc/fc_cpu_tgl.cm_config | |
81 | #endif | |
82 | #ifdef AXIS_TURNIN | |
83 | #ifdef AXIS_TL | |
84 | -axis_build_args=" -rm_axiswork " | |
85 | -vcs_build_args=+rtlUnsupportedError | |
86 | #endif | |
87 | #endif | |
88 | #ifdef AXIS_COSIM | |
89 | -vcs_build_args=" +rtlIgnPragma +rtlCommentPragma+niu_txc_drr_arbiter " | |
90 | -vcs_build_args="+define+AXIS_SMEM+EMUL_COSIM+AXIS_EMUL_COSIM " | |
91 | -axis_build_args="-hwtype xs -model_type axis_cs -comp_64" | |
92 | -axis_run_args=" -model_type axis_cs " | |
93 | #endif | |
94 | #ifdef AXIS_TL | |
95 | -novcs_use_fsdb | |
96 | -vcs_build_args=+define+FSDB_OFF | |
97 | -axis_run_args="-hwtype xs" | |
98 | -vcs_build_args="+define+AXIS_SMEM+EMUL_COSIM+AXIS_EMUL_COSIM " | |
99 | //-vcs_build_args="-Z $DV_ROOT/verif/env/fc/axis_hacks.v" | |
100 | -vcs_build_args=" $DV_ROOT/verif/env/fc/axis_modules.v" | |
101 | -vcs_build_args="-v $DV_ROOT/verif/env/fc/axis_siu_mon.v" | |
102 | -axis_run_args=-runpresim '"$DV_ROOT/verif/env/mcu/axis_convert -s "' | |
103 | -vcs_build_args=+define+FBDIMM_NUM_1+ | |
104 | -vcs_run_args=+1_FBDIMMS | |
105 | -vcs_run_args=+ddr2_way_err_enable=0 | |
106 | -vcs_run_args=+ddr2_way_warn_enable=1 | |
107 | -vcs_build_args=+define+X4+ | |
108 | -vcs_build_args=+define+AXIS_DDR2_MODEL | |
109 | -vcs_build_args=+define+AXIS_FBDIMM | |
110 | -midas_args=-DPART_0_BASE=0x0 | |
111 | -midas_args=-nocompress_image | |
112 | -vcs_build_args="+dut+tb_top" | |
113 | -vcs_build_args="+define+AXIS_TL +define+ALL_DUMP_OFF " | |
114 | -vcs_build_args="-v $DV_ROOT/verif/env/fc/axis_ccx_mon.v" | |
115 | #ifndef AXIS_NO_IP | |
116 | -vcs_build_args="-Z $DV_ROOT/verif/model/verilog/niu/niu_enet_models/n2_tcam_array.vap" | |
117 | #endif | |
118 | -vcs_build_args=" +rtlCommentPragma " | |
119 | -axis_build_args="-hwtype xs -model_type axis_tl -comp_64" | |
120 | -axis_run_args=" -model_type axis_tl" | |
121 | -vera_build_args=FC_NO_PEU_VERA=1 | |
122 | -vcs_build_args=+incdir+$DV_ROOT/design/esr/esr_l/esr/rtl/ | |
123 | -vcs_build_args="-v $DV_ROOT/verif/env/fc/axis_tlb_mon.v" | |
124 | -vcs_build_args="-v /import/datools/vendor/axis/v2004.4.3/sys/masterLib/trigProc.v" | |
125 | #ifndef AXIS_NO_IP | |
126 | -vcs_build_args=+dut+ept | |
127 | #endif | |
128 | -vcs_build_args=+define+AXIS_FBDIMM_HW | |
129 | -vcs_build_args=+define+USE_JTAG_DRIVER | |
130 | #endif | |
131 | ||
132 | #ifdef AXIS_NO_FSR | |
133 | -vcs_build_args=+define+AXIS_FBDIMM_NO_FSR | |
134 | -vcs_build_args="-Z $DV_ROOT/verif/env/mcu/axis_hack_fsr.v " | |
135 | #ifdef AXIS_TL | |
136 | -vcs_build_args=+dut+no_fsr_for_axis | |
137 | #endif | |
138 | #endif | |
139 | ||
140 | -pal_use_tgseed | |
141 | -config_rtl=MCU | |
142 | -config_rtl=RTL_SPARC0 | |
143 | -config_rtl=RTL_FLOP_RPTRS | |
144 | -config_rtl=RTL_DRAM02 | |
145 | -config_rtl=RTL_DRAM13 | |
146 | -config_rtl=NCURTL | |
147 | -config_rtl=FC_BENCH | |
148 | // Generic define for all core Benches (SPC2,CMPn,CCMn,FCn). Not set in SATs. | |
149 | -config_rtl=CORE_BENCH | |
150 | -config_rtl=ZIN_CORE_SUBSET | |
151 | -vera_build_args="VFLAGS=-DDRAM" | |
152 | -vera_build_args=PAL_OPTS="sys=DRAM" | |
153 | -vera_build_args=NEPTUNE_MODE=N2 | |
154 | -vera_build_args=VERA_SYS_DEFS="-DFC_BENCH -DNCURTL -DN2_FC" | |
155 | -vera_build_args=NEPTUNE_ENV=CDMSPP | |
156 | -vera_config_root=$DV_ROOT/verif | |
157 | -vera_diag_root=$DV_ROOT/verif/diag | |
158 | -drm_disk=[/export/home/bw=30] | |
159 | -drm_type=vcs | |
160 | -drm_freeram=2000 | |
161 | -drm_freeprocessor=1.0 | |
162 | -asm_diag_root=$DV_ROOT/verif/diag | |
163 | -env_base=$DV_ROOT/verif/env/fc | |
164 | -flist=$DV_ROOT/verif/env/common/verilog/misc/misc.flist | |
165 | #ifdef CONFIG_LOADNGO | |
166 | -flist=$DV_ROOT/verif/env/fc/loadngo/fc_loadngo.flist | |
167 | -vcs_build_args=-LDFLAGS -R -LDFLAGS $DV_ROOT/verif/env/fc/loadngo/pli | |
168 | -vcs_build_args=" -L$DV_ROOT/verif/env/fc/loadngo/pli -lloadngo" | |
169 | -vcs_build_args=+vc+abstract | |
170 | -vera_build_args="CONFIG_LOADNGO=1" | |
171 | #endif | |
172 | #ifdef AXIS_BUILD | |
173 | //#ifdef AXIS_TL | |
174 | -flist=$DV_ROOT/verif/env/common/verilog/axis_traps/axis_traps.flist | |
175 | //#else | |
176 | #endif | |
177 | ||
178 | #ifndef AXIS_TL | |
179 | #ifndef PLAYBACK | |
180 | -flist=$DV_ROOT/verif/env/common/verilog/nas_car/nas_car.flist | |
181 | -flist=$DV_ROOT/verif/env/common/verilog/tlb_sync/tlb_sync.flist | |
182 | -flist=$DV_ROOT/verif/env/common/verilog/int_sync/int_sync.flist | |
183 | -flist=$DV_ROOT/verif/env/common/verilog/ldst_sync/ldst_sync.flist | |
184 | -flist=$DV_ROOT/verif/env/common/verilog/err_sync/err_sync.flist | |
185 | #endif // PLAYBACK | |
186 | -flist=$DV_ROOT/verif/env/common/verilog/reg_slam/reg_slam.flist | |
187 | #ifndef GATESIM | |
188 | -flist=$DV_ROOT/verif/env/common/verilog/monitors/monitors_soc.flist | |
189 | -flist=$DV_ROOT/verif/env/common/verilog/err_random/err.flist | |
190 | #ifndef FC_NO_NIU_T2 | |
191 | #ifndef NIU_SYSTEMC_T2 | |
192 | -flist=$DV_ROOT/verif/env/common/verilog/soc_sync/soc_sync.flist.2 | |
193 | #else | |
194 | -flist=$DV_ROOT/verif/env/common/verilog/soc_sync/soc_sync.flist | |
195 | #endif | |
196 | #else | |
197 | -flist=$DV_ROOT/verif/env/common/verilog/soc_sync/soc_sync.flist | |
198 | #endif | |
199 | ||
200 | #endif | |
201 | #endif | |
202 | #ifndef FC_NO_NIU_T2 | |
203 | #ifndef IO_GATE | |
204 | -flist=$DV_ROOT/verif/env/niu/eser_rtl.flist | |
205 | #endif | |
206 | -flist=$DV_ROOT/verif/env/niu/eser_tb.flist | |
207 | -flist=$DV_ROOT/verif/env/fc/fc_niu.flist | |
208 | -flist=$DV_ROOT/verif/env/common/verilog/monitors/monitors.flist | |
209 | #endif | |
210 | #ifdef INPHI_AMB | |
211 | -flist=$DV_ROOT/verif/model/inphi/inphi_amb.flist | |
212 | -flist=$DV_ROOT/verif/model/sun/sun_misc.flist | |
213 | #elif MICRON_AMB | |
214 | -flist=$DV_ROOT/verif/model/micron/micron_amb.flist | |
215 | -flist=$DV_ROOT/verif/model/sun/sun_misc.flist | |
216 | #elif IDT_AMB | |
217 | -flist=$DV_ROOT/verif/model/idt/idt_amb.flist | |
218 | -flist=$DV_ROOT/verif/model/sun/sun_misc.flist | |
219 | // commented this out, replaced with equiv. definition | |
220 | // #define CRC_ERR_INJECTOR | |
221 | -vcs_build_args=+define+FC_CRC_INJECT | |
222 | -flist=$DV_ROOT/verif/env/mcu/fc_crc.flist | |
223 | #elif NEC_AMB | |
224 | -flist=$DV_ROOT/verif/model/nec/nec_amb.flist | |
225 | -flist=$DV_ROOT/verif/model/sun/sun_misc.flist | |
226 | -vcs_build_args=+define+ASSERTS_OFF | |
227 | -vcs_build_args=+nospecify | |
228 | -vcs_build_args=+access+rwc | |
229 | -vcs_build_args=+no_tchkmsg | |
230 | -vcs_build_args=+notimingcheck | |
231 | -vcs_build_args=+libext+.vp+ | |
232 | -vcs_build_args=+warn=noTMR | |
233 | ||
234 | #else | |
235 | -flist=$DV_ROOT/verif/model/sun/sun_amb.flist | |
236 | #endif | |
237 | ||
238 | //#ifdef CRC_ERR_INJECTOR | |
239 | //#ifndef PLAYBACK | |
240 | //-vcs_build_args=+define+FC_CRC_INJECT | |
241 | //-flist=$DV_ROOT/verif/env/mcu/fc_crc.flist | |
242 | //#endif // PLAYBACK | |
243 | //#endif | |
244 | ||
245 | #ifdef NB_BITLANE_DESKEW | |
246 | -vcs_build_args=+define+NB_BITLANE_DESKEW | |
247 | -flist=$DV_ROOT/verif/env/mcu/fc_crc.flist | |
248 | #endif | |
249 | ||
250 | #ifndef PLAYBACK | |
251 | -flist=$DV_ROOT/verif/env/fc/fc.flist | |
252 | #endif // PLAYBACK | |
253 | #ifdef PLAYBACK | |
254 | -flist=$DV_ROOT/verif/env/fc/fc_playback.flist | |
255 | -vcs_build_args=-P $DV_ROOT/verif/env/fc/vectorfile.tab | |
256 | -vcs_build_args=$DV_ROOT/verif/env/fc/libvectorfile.a | |
257 | #endif // PLAYBACK | |
258 | ||
259 | #ifdef FULL_GATE | |
260 | #ifndef PLAYBACK | |
261 | -flist=$DV_ROOT/verif/env/fc/ilu_peu_denali.flist | |
262 | #endif // PLAYBACK | |
263 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist | |
264 | -flist=$DV_ROOT/verif/env/fc/fc_rptr.flist | |
265 | #endif | |
266 | #ifdef PEU_DMU_GATESIM | |
267 | #ifndef PLAYBACK | |
268 | -flist=$DV_ROOT/verif/env/fc/ilu_peu_denali.flist | |
269 | #endif // PLAYBACK | |
270 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.peu+dmu_gate | |
271 | #endif | |
272 | #ifdef CCU_GATESIM | |
273 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ccu_gate | |
274 | #endif | |
275 | #ifdef SUNV_EXCLUDE_CPU | |
276 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.cpu_gate | |
277 | -sunv_args=-excludecell=\^cpu | |
278 | #endif | |
279 | #ifdef SUNV_EXCLUDE_CLK_GL_CUST | |
280 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.clk_gl_cust_gate | |
281 | -sunv_args=-excludecell=\^n2_clk_gl_cust\$ | |
282 | -sunv_args=-excludecell=\^n2_clk_gl_cmp_tree\$ | |
283 | -sunv_args=-excludecell=\^n2_clk_gl_dr_tree\$ | |
284 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_top\$ | |
285 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_ccu_m0 | |
286 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_rst_m0 | |
287 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_tcu_m0 | |
288 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_17s1 | |
289 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_8s2 | |
290 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_4s4 | |
291 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s1_1 | |
292 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s1_0 | |
293 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_0 | |
294 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_1 | |
295 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_2 | |
296 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s1_1 | |
297 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_0 | |
298 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_1 | |
299 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_2 | |
300 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_3 | |
301 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s1_0 | |
302 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s2_0 | |
303 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s2_1 | |
304 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s1_0 | |
305 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s2_0 | |
306 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s2_1 | |
307 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_0 | |
308 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_1 | |
309 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_3 | |
310 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_2 | |
311 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_0 | |
312 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_1 | |
313 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_3 | |
314 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_2 | |
315 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s1_0 | |
316 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s1_1 | |
317 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s1_1 | |
318 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_align | |
319 | -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_mcu_dr | |
320 | #endif | |
321 | #ifdef SUNV_EXCLUDE_IO | |
322 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.io_gate | |
323 | -sunv_args=-excludecell=\^fsr | |
324 | -sunv_args=-excludecell=\^esr | |
325 | -sunv_args=-excludecell=\^psr | |
326 | -sunv_args=-excludecell=\^mio | |
327 | -sunv_args=-excludecell=\^mio | |
328 | -sunv_args=-excludecell=\^n2_pcm_main_blk | |
329 | #endif | |
330 | #ifdef SUNV_EXCLUDE_MCU | |
331 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.mcu_gate | |
332 | -sunv_args=-excludecell=\^mcu | |
333 | #endif | |
334 | #ifdef SUNV_EXCLUDE_NIU | |
335 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.niu_gate | |
336 | -sunv_args=-excludecell=\^niu | |
337 | -sunv_args=-excludecell=\^mac | |
338 | -sunv_args=-excludecell=\^rtx | |
339 | -sunv_args=-excludecell=\^rdp | |
340 | -sunv_args=-excludecell=\^tds | |
341 | #endif | |
342 | #ifdef SUNV_EXCLUDE_TCU | |
343 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.tcu_gate | |
344 | -sunv_args=-excludecell=\^tcu | |
345 | #endif | |
346 | #ifdef SUNV_EXCLUDE_RST | |
347 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.rst_gate | |
348 | -sunv_args=-excludecell=\^rst | |
349 | #endif | |
350 | #ifdef SUNV_EXCLUDE_EFU | |
351 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.efu_gate | |
352 | -sunv_args=-excludecell=\^efu | |
353 | #endif | |
354 | #ifdef SUNV_EXCLUDE_SII_SIO | |
355 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.sii+sio_gate | |
356 | -sunv_args=-excludecell=\^sii\$ | |
357 | -sunv_args=-excludecell=\^sii_ilc_ctl\$ | |
358 | -sunv_args=-excludecell=\^sii_ild_dp\$ | |
359 | -sunv_args=-excludecell=\^sii_inc_ctl\$ | |
360 | -sunv_args=-excludecell=\^sii_ipcc_ctl\$ | |
361 | -sunv_args=-excludecell=\^sii_ipcc_dp\$ | |
362 | -sunv_args=-excludecell=\^sii_ipcs_ctl\$ | |
363 | -sunv_args=-excludecell=\^sii_mb0_ctl\$ | |
364 | -sunv_args=-excludecell=\^sii_mb1_ctl\$ | |
365 | -sunv_args=-excludecell=\^sii_stgsio_dp\$ | |
366 | -sunv_args=-excludecell=\^sio\$ | |
367 | -sunv_args=-excludecell=\^sio_mb0_ctl\$ | |
368 | -sunv_args=-excludecell=\^sio_mb1_ctl\$ | |
369 | -sunv_args=-excludecell=\^sio_mbist_ctl\$ | |
370 | -sunv_args=-excludecell=\^sio_olc_ctl\$ | |
371 | -sunv_args=-excludecell=\^sio_old_dp\$ | |
372 | -sunv_args=-excludecell=\^sio_old_rf_cust\$ | |
373 | -sunv_args=-excludecell=\^sio_opcc_ctl\$ | |
374 | -sunv_args=-excludecell=\^sio_opcs_ctl\$ | |
375 | -sunv_args=-excludecell=\^sio_opd_data_rf_cust\$ | |
376 | -sunv_args=-excludecell=\^sio_opd_hdr_rf_cust\$ | |
377 | -sunv_args=-excludecell=\^sio_opdc_dp\$ | |
378 | -sunv_args=-excludecell=\^sio_opds_dp\$ | |
379 | -sunv_args=-excludecell=\^sio_stg1_dp\$ | |
380 | -sunv_args=-excludecell=\^sio_stg2_dp\$ | |
381 | #endif | |
382 | #ifdef SUNV_EXCLUDE_SPC | |
383 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.spc_gate | |
384 | // exclude spc | |
385 | -sunv_args=-excludecell=\^spc\$ | |
386 | -sunv_args=-excludecell=\^spc_msf0_dp\$ | |
387 | -sunv_args=-excludecell=\^spc_msf1_dp\$ | |
388 | -sunv_args=-excludecell=\^spc_lb_ctl\$ | |
389 | -sunv_args=-excludecell=\^clkgen_spc_cmp\$ | |
390 | -sunv_args=-excludecell=\^dmo_dp\$ | |
391 | -sunv_args=-excludecell=\^gkt\$ | |
392 | -sunv_args=-excludecell=\^fgu\$ | |
393 | -sunv_args=-excludecell=\^ifu_ibu\$ | |
394 | -sunv_args=-excludecell=\^ifu_ftu\$ | |
395 | -sunv_args=-excludecell=\^ifu_cmu\$ | |
396 | -sunv_args=-excludecell=\^dec\$ | |
397 | -sunv_args=-excludecell=\^pku\$ | |
398 | -sunv_args=-excludecell=\^exu\$ | |
399 | -sunv_args=-excludecell=\^tlu\$ | |
400 | -sunv_args=-excludecell=\^lsu\$ | |
401 | -sunv_args=-excludecell=\^spu\$ | |
402 | -sunv_args=-excludecell=\^mmu\$ | |
403 | -sunv_args=-excludecell=\^pmu\$ | |
404 | -sunv_args=-excludecell=\^spc_mb0_ctl\$ | |
405 | -sunv_args=-excludecell=\^spc_mb1_ctl\$ | |
406 | -sunv_args=-excludecell=\^spc_mb2_ctl\$ | |
407 | #endif | |
408 | #ifdef SUNV_EXCLUDE_CCX | |
409 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ccx_gate | |
410 | // exclude ccx | |
411 | -sunv_args=-excludecell=\^ccx\$ | |
412 | -sunv_args=-excludecell=\^cpx\$ | |
413 | -sunv_args=-excludecell=\^pcx\$ | |
414 | #endif | |
415 | #ifdef SUNV_EXCLUDE_L2 | |
416 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.l2_gate | |
417 | // exclude l2t | |
418 | -sunv_args=-excludecell=\^l2t\$ | |
419 | -sunv_args=-excludecell=\^l2t_arb_ctl\$ | |
420 | -sunv_args=-excludecell=\^l2t_arbadr_dp\$ | |
421 | -sunv_args=-excludecell=\^l2t_arbdat_dp\$ | |
422 | -sunv_args=-excludecell=\^l2t_arbdec_dp\$ | |
423 | -sunv_args=-excludecell=\^l2t_csr_ctl\$ | |
424 | -sunv_args=-excludecell=\^l2t_csreg_ctl\$ | |
425 | -sunv_args=-excludecell=\^l2t_decc_dp\$ | |
426 | -sunv_args=-excludecell=\^l2t_deccck_ctl\$ | |
427 | -sunv_args=-excludecell=\^l2t_dir_ctl\$ | |
428 | -sunv_args=-excludecell=\^l2t_dirbuf_ctl\$ | |
429 | -sunv_args=-excludecell=\^l2t_dirin_dp\$ | |
430 | -sunv_args=-excludecell=\^l2t_dirlbf_dp\$ | |
431 | -sunv_args=-excludecell=\^l2t_dirout_dp\$ | |
432 | -sunv_args=-excludecell=\^l2t_dirrep_ctl\$ | |
433 | -sunv_args=-excludecell=\^l2t_dirtop_ctl\$ | |
434 | -sunv_args=-excludecell=\^l2t_dirvec_ctl\$ | |
435 | -sunv_args=-excludecell=\^l2t_dirvec_dp\$ | |
436 | -sunv_args=-excludecell=\^l2t_dmo_dp\$ | |
437 | -sunv_args=-excludecell=\^l2t_dmorpt_dp\$ | |
438 | -sunv_args=-excludecell=\^l2t_ecc24b_dp\$ | |
439 | -sunv_args=-excludecell=\^l2t_ecc30b_dp\$ | |
440 | -sunv_args=-excludecell=\^l2t_ecc39_dp\$ | |
441 | -sunv_args=-excludecell=\^l2t_ecc39a_dp\$ | |
442 | -sunv_args=-excludecell=\^l2t_evctag_dp\$ | |
443 | -sunv_args=-excludecell=\^l2t_ffrpt_dp\$ | |
444 | -sunv_args=-excludecell=\^l2t_filbuf_ctl\$ | |
445 | -sunv_args=-excludecell=\^l2t_iqu_ctl\$ | |
446 | -sunv_args=-excludecell=\^l2t_ique_dp\$ | |
447 | -sunv_args=-excludecell=\^l2t_l2brep_dp\$ | |
448 | -sunv_args=-excludecell=\^l2t_l2drpt_dp\$ | |
449 | -sunv_args=-excludecell=\^l2t_mb0_ctl\$ | |
450 | -sunv_args=-excludecell=\^l2t_mb2_ctl\$ | |
451 | -sunv_args=-excludecell=\^l2t_mbist_ctl\$ | |
452 | -sunv_args=-excludecell=\^l2t_misbuf_ctl\$ | |
453 | -sunv_args=-excludecell=\^l2t_mrep16x8_dp\$ | |
454 | -sunv_args=-excludecell=\^l2t_mrep2x64_dp\$ | |
455 | -sunv_args=-excludecell=\^l2t_mrep32x3_dp\$ | |
456 | -sunv_args=-excludecell=\^l2t_mrep4x6_dp\$ | |
457 | -sunv_args=-excludecell=\^l2t_mrep8x16_dp\$ | |
458 | -sunv_args=-excludecell=\^l2t_oqu_ctl\$ | |
459 | -sunv_args=-excludecell=\^l2t_oque_dp\$ | |
460 | -sunv_args=-excludecell=\^l2t_pgen32b_dp\$ | |
461 | -sunv_args=-excludecell=\^l2t_rdmarpt_dp\$ | |
462 | -sunv_args=-excludecell=\^l2t_rdmat_ctl\$ | |
463 | -sunv_args=-excludecell=\^l2t_rep_dp\$ | |
464 | -sunv_args=-excludecell=\^l2t_ret_dp\$ | |
465 | -sunv_args=-excludecell=\^l2t_shdwscn_dp\$ | |
466 | -sunv_args=-excludecell=\^l2t_snp_ctl\$ | |
467 | -sunv_args=-excludecell=\^l2t_snpd_dp\$ | |
468 | -sunv_args=-excludecell=\^l2t_tag_ctl\$ | |
469 | -sunv_args=-excludecell=\^l2t_tagd_dp\$ | |
470 | -sunv_args=-excludecell=\^l2t_tagdp_ctl\$ | |
471 | -sunv_args=-excludecell=\^l2t_taghdr_ctl\$ | |
472 | -sunv_args=-excludecell=\^l2t_tagl_dp\$ | |
473 | -sunv_args=-excludecell=\^l2t_usaloc_dp\$ | |
474 | -sunv_args=-excludecell=\^l2t_vlddir_dp\$ | |
475 | -sunv_args=-excludecell=\^l2t_vuad_ctl\$ | |
476 | -sunv_args=-excludecell=\^l2t_vuad_dp\$ | |
477 | -sunv_args=-excludecell=\^l2t_vuadcl_dp\$ | |
478 | -sunv_args=-excludecell=\^l2t_vuaddp_ctl\$ | |
479 | -sunv_args=-excludecell=\^l2t_vuadio_dp\$ | |
480 | -sunv_args=-excludecell=\^l2t_vuadpm_dp\$ | |
481 | -sunv_args=-excludecell=\^l2t_wbuf_ctl\$ | |
482 | -sunv_args=-excludecell=\^l2t_wbufrpt_dp\$ | |
483 | // exclude l2b | |
484 | -sunv_args=-excludecell=\^l2b | |
485 | #endif | |
486 | #ifdef SUNV_EXCLUDE_DB | |
487 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.db_gate | |
488 | // exclude db0 | |
489 | -sunv_args=-excludecell=\^db0\$ | |
490 | -sunv_args=-excludecell=\^db0_red_dp\$ | |
491 | -sunv_args=-excludecell=\^db0_reduct_ctl\$ | |
492 | -sunv_args=-excludecell=\^db0_rtc_dp\$ | |
493 | // exclude db1 | |
494 | -sunv_args=-excludecell=\^db1\$ | |
495 | -sunv_args=-excludecell=\^db1_csr_ctl\$ | |
496 | -sunv_args=-excludecell=\^db1_dbgprt_dp\$ | |
497 | -sunv_args=-excludecell=\^db1_ucbbusin4_ctl\$ | |
498 | -sunv_args=-excludecell=\^db1_ucbbusout4_ctl\$ | |
499 | -sunv_args=-excludecell=\^db1_ucbflow_ctl\$ | |
500 | #endif | |
501 | #ifdef SUNV_EXCLUDE_NCU | |
502 | -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ncu_gate | |
503 | -sunv_args=-excludecell=\^ncu\$ | |
504 | -sunv_args=-excludecell=\^ncu_c2ibuf32_ctl\$ | |
505 | -sunv_args=-excludecell=\^ncu_c2ibuf4_ctl\$ | |
506 | -sunv_args=-excludecell=\^ncu_c2ibufpio_ctl\$ | |
507 | -sunv_args=-excludecell=\^ncu_c2ifc_ctl\$ | |
508 | -sunv_args=-excludecell=\^ncu_c2ifcd_ctl\$ | |
509 | -sunv_args=-excludecell=\^ncu_c2ifd_ctl\$ | |
510 | -sunv_args=-excludecell=\^ncu_c2isc_ctl\$ | |
511 | -sunv_args=-excludecell=\^ncu_c2iscd_ctl\$ | |
512 | -sunv_args=-excludecell=\^ncu_c2isd_ctl\$ | |
513 | -sunv_args=-excludecell=\^ncu_ctrl_ctl\$ | |
514 | -sunv_args=-excludecell=\^ncu_eccchk11_ctl\$ | |
515 | -sunv_args=-excludecell=\^ncu_eccchk16_ctl\$ | |
516 | -sunv_args=-excludecell=\^ncu_eccchk6_ctl\$ | |
517 | -sunv_args=-excludecell=\^ncu_eccgen11_ctl\$ | |
518 | -sunv_args=-excludecell=\^ncu_eccgen6_ctl\$ | |
519 | -sunv_args=-excludecell=\^ncu_fcd_ctl\$ | |
520 | -sunv_args=-excludecell=\^ncu_i2cbuf32_ctl\$ | |
521 | -sunv_args=-excludecell=\^ncu_i2cbuf32_ni_ctl\$ | |
522 | -sunv_args=-excludecell=\^ncu_i2cbuf4_ctl\$ | |
523 | -sunv_args=-excludecell=\^ncu_i2cbuf4_ni_ctl\$ | |
524 | -sunv_args=-excludecell=\^ncu_i2cbufsii_ctl\$ | |
525 | -sunv_args=-excludecell=\^ncu_i2cbuftcu_ctl\$ | |
526 | -sunv_args=-excludecell=\^ncu_i2cfc_ctl\$ | |
527 | -sunv_args=-excludecell=\^ncu_i2cfcd_ctl\$ | |
528 | -sunv_args=-excludecell=\^ncu_i2cfd_ctl\$ | |
529 | -sunv_args=-excludecell=\^ncu_i2csc_ctl\$ | |
530 | -sunv_args=-excludecell=\^ncu_i2cscd_ctl\$ | |
531 | -sunv_args=-excludecell=\^ncu_i2csd_ctl\$ | |
532 | -sunv_args=-excludecell=\^ncu_mb0_ctl\$ | |
533 | -sunv_args=-excludecell=\^ncu_mb1_ctl\$ | |
534 | -sunv_args=-excludecell=\^ncu_scd_ctl\$ | |
535 | -sunv_args=-excludecell=\^ncu_ssiflow_ctl\$ | |
536 | -sunv_args=-excludecell=\^ncu_ssisif_ctl\$ | |
537 | -sunv_args=-excludecell=\^ncu_ssisrg64_ctl\$ | |
538 | -sunv_args=-excludecell=\^ncu_ssisrg8_ctl\$ | |
539 | -sunv_args=-excludecell=\^ncu_ssitop_ctl\$ | |
540 | -sunv_args=-excludecell=\^ncu_ssiui4_ctl\$ | |
541 | -sunv_args=-excludecell=\^ncu_ssiuif_ctl\$ | |
542 | -sunv_args=-excludecell=\^ncu_ssiuo4_ctl\$ | |
543 | -sunv_args=-excludecell=\^ncu_ucbbusin8_ctl\$ | |
544 | // | |
545 | #endif | |
546 | ||
547 | #ifndef CCU_GATE | |
548 | -flist=$DV_ROOT/verif/env/tcu/ccu_rtl.flist | |
549 | #endif | |
550 | #ifndef NIU_GATE | |
551 | #ifndef AXIS_NO_IP | |
552 | #ifndef FC_NO_NIU_T2 | |
553 | #ifdef NIU_SYSTEMC_T2 | |
554 | #include "fc_niu_systemc.config" | |
555 | -flist=$DV_ROOT/verif/env/niu/niu_systemc.flist | |
556 | #else | |
557 | -flist=$DV_ROOT/verif/env/niu/niu.flist | |
558 | #endif | |
559 | #endif | |
560 | #endif | |
561 | #endif | |
562 | #ifndef AXIS_NO_IP | |
563 | #ifndef DMU_GATE | |
564 | -flist=$DV_ROOT/verif/env/dmu/dmu.rtlflist | |
565 | #endif | |
566 | -flist=$DV_ROOT/verif/env/dmu/dmu.libsflist | |
567 | #endif | |
568 | #ifdef FC_NO_PEU_VERA | |
569 | #ifdef AXIS_NO_IP | |
570 | -flist=$DV_ROOT/verif/env/fc/axis_no_ip.flist | |
571 | -vcs_build_args=+define+NO_VCS_CASCADE_IP_CODE | |
572 | #else | |
573 | -config_rtl=FC_NO_PEUSAT_CODE | |
574 | #ifndef FC_NO_PEU_T2 | |
575 | -flist=$DV_ROOT/verif/model/verilog/pcie/ept/ept.flist | |
576 | #endif | |
577 | #ifdef USE_BOBO | |
578 | -vera_build_args=BUILD_USE_BOBO=1 | |
579 | -config_rtl=BUILD_USE_BOBO | |
580 | -midas_args=-DUSE_BOBO=1 | |
581 | -flist=$DV_ROOT/verif/model/verilog/pcie/ept/bobo.flist | |
582 | #endif // use_bobo | |
583 | #ifndef FC_NO_PEU_T2 | |
584 | -flist=$DV_ROOT/verif/env/ilu_peu/ilu_peu_rtl_encrypted.axis.flist | |
585 | #endif | |
586 | #endif //axis_no_ip | |
587 | #else // fc_no_peu_vera | |
588 | #ifndef PEU_GATE | |
589 | #ifndef FC_NO_PEU_T2 | |
590 | -flist=$DV_ROOT/verif/env/fc/ilu_peu_denali.flist | |
591 | #ifdef PEU_SYSTEMC_T2 | |
592 | #include "fc_pcie_systemc.config" | |
593 | -flist=$DV_ROOT/verif/env/ilu_peu/ilu_peu_systemc.flist | |
594 | #else | |
595 | -flist=$DV_ROOT/verif/env/ilu_peu/ilu_peu_rtl_encrypted.flist | |
596 | #endif //PEU_SYSTEMC_T2 | |
597 | #endif | |
598 | #endif | |
599 | #endif //fc_no_peu_vera | |
600 | #ifndef AXIS_NO_IP | |
601 | #ifndef DMU_GATE | |
602 | -flist=$DV_ROOT/verif/env/ilu_peu/ilu_peu_common.rtlflist | |
603 | #endif | |
604 | #endif | |
605 | #ifndef IO_GATE | |
606 | -flist=$DV_ROOT/verif/env/mcu/fbd_serdes_axis.flist | |
607 | #endif | |
608 | -flist=$DV_ROOT/verif/env/fc/fc_inc.flist | |
609 | ||
610 | -fsdbfile=fc_top.fsdb | |
611 | -image_diag_root=$DV_ROOT/verif | |
612 | -midas_args=-DPART_0_BASE=0x200000000 | |
613 | -midas_args=-DFC | |
614 | -midas_args=-tsbtagfmt=tagtarget | |
615 | -midas_args=-cpp_args=-traditional-cpp | |
616 | -sas_run_args=-DTHREAD_STATUS_ADDR=0x9a00000000 | |
617 | -sas_run_args=-DMEM_DISABLE | |
618 | -sas_run_args=-DINTR_TEST | |
619 | -sas_run_args=-DFORCE_PC | |
620 | -sas_run_args=-DTSO_CHECKER | |
621 | SUNVFORCEOPTS | |
622 | -sunv_args=-preload=SUNVLIBS_SUNV | |
623 | -sunv_args=-perlinclude=SUNVPERLINC | |
624 | -sunv_args=-define=SIM | |
625 | -sunv_args=-define=LIB | |
626 | //-sunv_args=-define=INITLATZERO | |
627 | -sunv_args=-define=VCS | |
628 | -sunv_args=-version | |
629 | -sunv_args=-topcell=cpu | |
630 | -sunv_args=-warn=2000 | |
631 | -sunv_args=-ignorepartial | |
632 | -sunv_args=-unusednet='unused$:unused\[[0-9]+\]$' | |
633 | -sunv_args=-excludepreload | |
634 | -sunv_args=-out=cpu.v | |
635 | -sunv_args=-path=SUNV_RTL_PATH | |
636 | -sunv_args=-path=SUNVMACROS | |
637 | -sunv_args=-showCompiledOutCode=off | |
638 | -sunv_use_nonprim | |
639 | -sunv_nonprim_list=$DV_ROOT/verif/env/fc/nonprimitive.list | |
640 | -sunv_args=-excludecell=\^dmu\$ | |
641 | -sunv_args=-excludecell=\^peu\$ | |
642 | -sunv_args=-excludecell=\^psr\$ | |
643 | -sunv_args=-excludecell=\^esr\$ | |
644 | -sunv_args=-excludecell=\^rdp\$ | |
645 | -sunv_args=-excludecell=\^rtx\$ | |
646 | -sunv_args=-excludecell=\^tds\$ | |
647 | -sunv_args=-excludecell=\^mac\$ | |
648 | -sunv_args=-excludecell=\^ccu\$ | |
649 | #ifndef ONLY_FOR_TO_1_0 | |
650 | -sunv_args=-excludecell=\^n2_rng_cust\$ | |
651 | #endif | |
652 | -sunv_args=-excludecell=\^fsr_left\$ | |
653 | -sunv_args=-excludecell=\^fsr_right\$ | |
654 | -sunv_args=-excludecell=\^fsr_bottom\$ | |
655 | ||
656 | #ifdef INPHI_AMB | |
657 | -sunv_args=-define=FBD_LAT_DELAY_2 | |
658 | #endif | |
659 | #ifdef MICRON_AMB | |
660 | -sunv_args=-define=FBD_LAT_DELAY_1 | |
661 | -vcs_run_args=+MICRON_AMB_USED | |
662 | #endif | |
663 | #ifdef IDT_AMB | |
664 | -sunv_args=-define=FBD_LAT_DELAY_1 | |
665 | -vcs_build_args=+define+IDT_FBDIMM | |
666 | -vcs_run_args=+BYPASS_AMB_DRAM_INIT | |
667 | -vcs_run_args=+IDT_AMB_USED | |
668 | #endif | |
669 | #ifdef NEC_AMB | |
670 | -sunv_args=-define=FBD_LAT_DELAY_1 | |
671 | #endif | |
672 | ||
673 | -vlint_top=tb_top | |
674 | -vlint_args=+define+TOP=tb_top | |
675 | -vlint_args=SUNVLIBS_OTHER | |
676 | -vlint_args=-turn_unspecified_off | |
677 | -vlint_args=-binary | |
678 | -vlint_args=-vlint | |
679 | -vlint_args=-depth 999 | |
680 | -vlint_args=-vr $DV_ROOT/verif/env/config/vlint.rc | |
681 | -illust_args=-b -c $DV_ROOT/verif/env/config/filter_vlint.rc | |
682 | -illust_run | |
683 | -wait_cycle_to_kill=15 | |
684 | -zeroIn_build_args=+define+TOP=tb_top | |
685 | -zeroIn_build_args=-d cpu | |
686 | #if defined(AXIS_BUILD) || defined(AXIS_COSIM) | |
687 | -zeroIn_build_args=-sim axis | |
688 | #else | |
689 | -zeroIn_build_args=-sim vcs | |
690 | #endif | |
691 | #ifdef FC_COVERAGE | |
692 | -vera_cov_obj=FC_COVERAGE | |
693 | -vcs_build_args=+define+FC_COVERAGE | |
694 | #define ZEROINCOV | |
695 | -config_rtl=SPCINF_COVERAGE | |
696 | #endif | |
697 | #ifndef ZINFASTBUILD | |
698 | #ifndef ZEROINCOV | |
699 | -zeroIn_build_args="-fastsim turbo" | |
700 | #endif | |
701 | #ifndef NOFASTMOD | |
702 | -zeroIn_build_args=-fastmod | |
703 | #endif | |
704 | #endif | |
705 | -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/0in_checkers.v | |
706 | #ifdef ZEROINCOV | |
707 | -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/0in_coverages.v | |
708 | #endif | |
709 | -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/fc/fc_zeroIn_cfg.v | |
710 | -zeroIn_build_args=SUNVLIBS_OTHER | |
711 | -zeroIn_build_args=-incr | |
712 | -zeroIn_build_args=+define+CPU=tb_top.cpu | |
713 | -zeroIn_build_args=+define+FC_NO_NIU_T2 | |
714 | -zeroIn_build_args=+define+FC_NO_PEU_T2 | |
715 | #ifndef FC_NO_NIU_T2 | |
716 | -zeroIn_build_args=+define+ESR=tb_top.cpu.esr | |
717 | -zeroIn_build_args=+define+RTX=tb_top.cpu.rtx | |
718 | -zeroIn_build_args=+define+TDS=tb_top.cpu.tds | |
719 | -zeroIn_build_args=+define+RDP=tb_top.cpu.rdp | |
720 | -zeroIn_build_args=+define+MAC=tb_top.cpu.mac | |
721 | -zeroIn_build_args=+define+NIU=tb_top.cpu.niu | |
722 | #endif | |
723 | -zeroIn_build_args=+define+ILU=tb_top.cpu.dmu.ilu | |
724 | -zeroIn_build_args=-exit_on_directive_errors | |
725 | -zeroIn_build_args=+define+FSR_NOATPG | |
726 | -zeroIn_build_args=+error+command-19 | |
727 | -zeroIn_build_args=+error+command-46 | |
728 | -zeroIn_build_args=+error+command-6 | |
729 | -zeroIn_build_args=+error+command-7 | |
730 | //skip processing bench modules | |
731 | #ifndef FC_NO_PEU_T2 | |
732 | -zeroIn_build_args=+skip_modules+fc_dmupeu_csr_probe | |
733 | #endif | |
734 | -zeroIn_build_args=+skip_modules+fc_l2_csr_probe | |
735 | -zeroIn_build_args=+skip_modules+fc_mcu_csr_probe | |
736 | -zeroIn_build_args=+skip_modules+fc_ncu_csr_probe | |
737 | #ifndef FC_NO_NIU_T2 | |
738 | -zeroIn_build_args=+skip_modules+fc_niu_csr_probe | |
739 | #endif | |
740 | -vcs_build_args=+define+DISABLE_TID_CHKR | |
741 | -vcs_build_args=+define+FSR_NOATPG | |
742 | //-vcs_run_args=+noldst_sync | |
743 | -vcs_build_args=SUNVLIBS_OTHER | |
744 | -vcs_build_args=+define+BWSIM_SAME_GCLK_RCLK+ | |
745 | -vcs_build_args=+define+MODEL_DRAM+ | |
746 | #ifdef DRAMX8 | |
747 | -vcs_build_args=+define+X8 | |
748 | -zeroIn_build_args=+define+X8 | |
749 | -vcs_run_args=+X8 | |
750 | #else | |
751 | -vcs_build_args=+define+X4 | |
752 | -zeroIn_build_args=+define+X4 | |
753 | #endif | |
754 | -vcs_build_args=+define+DRAM_SAT+ | |
755 | -vcs_build_args=+define+TOP=tb_top | |
756 | -vcs_build_args=+define+LIB | |
757 | -vcs_build_args=+define+SIM | |
758 | -vcs_build_args=+define+IOS | |
759 | -vcs_build_args=+define+N2 | |
760 | #ifndef FC_NO_NIU_T2 | |
761 | -vcs_build_args=+define+N2_NIU | |
762 | #endif | |
763 | #ifdef FC_NO_NIU_T2 | |
764 | -diaglist_cpp_args=-DFC_NO_NIU_T2 | |
765 | #endif | |
766 | #ifdef FC_NO_PEU_T2 | |
767 | -diaglist_cpp_args=-DFC_NO_PEU_T2 | |
768 | #endif | |
769 | #ifdef NIU_SYSTEMC_T2 | |
770 | -vcs_build_args=+define+NIU_SYSTEMC_T2 | |
771 | -diaglist_cpp_args=-DNIU_SYSTEMC_T2 | |
772 | #endif | |
773 | -vcs_build_args=+define+FLUSH_RESET | |
774 | -vcs_build_args=+define+SCAN_MODE | |
775 | #ifdef USE_TAP_DRIVER | |
776 | -vera_build_args="USE_JTAG_DRIVER=1" | |
777 | -vcs_build_args=+define+USE_JTAG_DRIVER | |
778 | #else | |
779 | #ifndef USE_FULL_FLOP | |
780 | -vcs_build_args=+define+FAST_FLUSH | |
781 | #endif // USE_FULL_FLOP | |
782 | #endif // USE_TAP_DRIVER | |
783 | ||
784 | #ifdef USE_FULL_FLOP | |
785 | -zeroIn_build_args=+define+MUXOHTEST //enable mux-ex check | |
786 | -vcs_build_args=+define+MUXOHTEST //enable mux-ex check | |
787 | #endif // USE_FULL_FLOP | |
788 | ||
789 | // Used for DTM Mode | |
790 | #ifdef TO_1_0_VECTORS | |
791 | -vera_build_args="TO_1_0_VECTORS=1" | |
792 | -config_rtl=TO_1_0_VECTORS | |
793 | // Axis doesn't read config.v soon enough, so we also need: | |
794 | -vcs_build_args=+define+TO_1_0_VECTORS | |
795 | #endif | |
796 | ||
797 | // Option to disable MEM initialization in array cell | |
798 | #ifdef NO_INIT_MEM | |
799 | -sunv_args=-define=NOINITMEM | |
800 | -config_rtl=NOINITMEM | |
801 | #endif | |
802 | ||
803 | -vcs_build_args=+define+DISABLE_tMRD_VIOLATION_AT_PD_ENTRY | |
804 | -vcs_build_args=+define+NO_Ill_cmd_during_init_MRS_with_DLL_disable_expected_CHECK | |
805 | ||
806 | #ifndef AXIS_TL | |
807 | // -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/libdummy.a | |
808 | -vcs_build_args="-P $DV_ROOT/verif/model/infineon/bwmem_pli.tab" | |
809 | #ifndef LINUX | |
810 | -vcs_build_args=$DV_ROOT/verif/model/infineon/libbwmem_pli.a | |
811 | #else | |
812 | -vcs_build_args=$DV_ROOT/verif/model/infineon/linux/libbwmem_pli.a | |
813 | #endif | |
814 | -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/bwutility/bwutility_pli.tab" | |
815 | #ifndef LINUX | |
816 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/libbwutility_pli.a | |
817 | #else | |
818 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/linux/libbwutility_pli.a | |
819 | #endif | |
820 | //added for l2 warm | |
821 | -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/cache/bwioj.tab" | |
822 | #ifndef LINUX | |
823 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/cache/libiob.a | |
824 | #else | |
825 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/cache/linux/libiob.a | |
826 | #endif | |
827 | -vcs_build_args=+define+NO_Ill_cmd_before_init_CHECK | |
828 | -vcs_build_args=+define+NO_err_cke | |
829 | -vcs_build_args=+define+NO_err_cke_diasserted_when_not_pwr_down_CHECK | |
830 | -vcs_build_args=+define+NO_err_dqs_and_dqsbar_not_in_sync_CHECK | |
831 | -vcs_build_args=+define+NO_err_clk_and_clkbar_not_in_sync_CHECK | |
832 | #endif | |
833 | #if defined(AXIS_TL) || defined (VCS_FAST_MCU) | |
834 | -flist=$DV_ROOT/verif/env/fc/axis_dimm.flist | |
835 | #else | |
836 | #ifdef DRAMX8 | |
837 | -flist=$DV_ROOT/verif/model/verilog/mem/dram/infineon_x8_ddr2.flist | |
838 | #else | |
839 | -flist=$DV_ROOT/verif/model/verilog/mem/dram/infineon_ddr2.flist | |
840 | #endif | |
841 | #endif | |
842 | ||
843 | -flist=$DV_ROOT/design/sys/iop/ccx/ccx_rtl.flist | |
844 | -flist=$DV_ROOT/design/sys/iop/db0/db0_rtl.flist | |
845 | -flist=$DV_ROOT/design/sys/iop/db1/db1_rtl.flist | |
846 | -flist=$DV_ROOT/design/sys/iop/efu/efu_rtl.flist | |
847 | -flist=$DV_ROOT/design/sys/iop/l2b/l2b_rtl.flist | |
848 | -flist=$DV_ROOT/design/sys/iop/l2t/l2t_rtl.flist | |
849 | -flist=$DV_ROOT/design/sys/iop/mcu/mcu_rtl.flist | |
850 | -flist=$DV_ROOT/design/sys/iop/ncu/ncu_rtl.flist | |
851 | -flist=$DV_ROOT/design/sys/iop/rst/rst_rtl.flist | |
852 | -flist=$DV_ROOT/design/sys/iop/sii/sii_rtl.flist | |
853 | -flist=$DV_ROOT/design/sys/iop/sio/sio_rtl.flist | |
854 | -flist=$DV_ROOT/design/sys/iop/spc/spc_rtl.flist | |
855 | -flist=$DV_ROOT/design/sys/iop/tcu/tcu_rtl.flist | |
856 | -flist=$DV_ROOT/verif/env/fc/fc.flist.des_v_rtl | |
857 | ||
858 | #if defined(AXIS_BUILD) || defined(AXIS_COSIM) | |
859 | #ifndef AXIS_TL | |
860 | -vcs_build_args=vera/mempli.a | |
861 | -vcs_build_args=vera/mal.o | |
862 | -vcs_build_args=vera/pgRandom.o | |
863 | -vcs_build_args=" -pl -R/import/freetools/local/gcc/3.3.2/lib " | |
864 | -vcs_build_args=" /import/freetools/local/gcc/3.3.2/lib/libstdc++.so" | |
865 | -vcs_build_args=" /import/freetools/local/gcc/3.3.2/lib/libgcc_s.so " | |
866 | //these four packet gen files are order sensitive!! sims reverses the order from | |
867 | //to what gets passed to the linker, and libnet.a must be at the end of the link | |
868 | -vcs_build_args=vera/libnet.a | |
869 | -vcs_build_args=vera/pgVera.a | |
870 | -vcs_build_args=vera/pgVeraWrap.o | |
871 | -vcs_build_args=vera/genCpacket.o | |
872 | -vcs_build_args=" $DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.o " | |
873 | #endif | |
874 | ||
875 | #else | |
876 | //note: the actual config cpp args e.g. FC_NO_PEU_T2, FC_NO_NIU_T2 | |
877 | //are declared inside fc.config, as for the non config cpp args, they are declared here | |
878 | #if defined(T2) | |
879 | -nosunv_run | |
880 | -nozeroIn_build | |
881 | -nozeroInSearch_build | |
882 | #endif | |
883 | #ifdef PEU_SYSTEMC_T2 | |
884 | -sysc_build | |
885 | -vera_build_args="PEU_SYSTEMC_T2=1" | |
886 | -vcs_build_args="+define+PEU_SYSTEMC_MODEL" | |
887 | -vcs_build_args="-sysc=220" | |
888 | -vcs_build_args="-cpp $CC_BIN/g++" | |
889 | -vcs_build_args="-ld $CC_BIN/g++" | |
890 | -vcs_build_args="-cc $CC_BIN/gcc" | |
891 | #endif | |
892 | ||
893 | //added these config cpp macros for OpenSparc T2 | |
894 | #ifdef FC_NO_NIU_T2 | |
895 | -vera_build_args="FC_NO_NIU_T2=1" | |
896 | -vcs_build_args=+define+FC_NO_NIU_T2 | |
897 | #endif | |
898 | #ifdef NIU_SYSTEMC_T2 | |
899 | -vera_build_args="NIU_SYSTEMC_T2=1" | |
900 | #endif | |
901 | #ifdef FC_NO_PEU_T2 | |
902 | -vera_build_args="FC_NO_PEU_T2=1" | |
903 | -vcs_build_args=+define+FC_NO_PEU_T2 | |
904 | #endif | |
905 | #ifdef FC_NO_PEU_VERA | |
906 | -vera_build_args="FC_NO_PEU_VERA=1" | |
907 | #endif | |
908 | // following added for no PEU mode (but with NIU) | |
909 | #ifndef FC_NO_NIU_T2 | |
910 | -vcs_build_args=+define+ESR=tb_top.cpu.esr | |
911 | -vcs_build_args=+define+RTX=tb_top.cpu.rtx | |
912 | -vcs_build_args=+define+TDS=tb_top.cpu.tds | |
913 | -vcs_build_args=+define+RDP=tb_top.cpu.rdp | |
914 | -vcs_build_args=+define+MAC=tb_top.cpu.mac | |
915 | #endif | |
916 | ||
917 | ||
918 | // -vcs_build_args=+applylearn+$DV_ROOT/verif/env/fc/pli_learn_all.tab | |
919 | -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/global_chkr/global_chkr.tab" | |
920 | #ifndef LINUX | |
921 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/global_chkr/libglobal_chkr.a | |
922 | #else | |
923 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/global_chkr/linux/libglobal_chkr.a | |
924 | #endif | |
925 | #ifndef GATESIM | |
926 | -vcs_build_args=+rad | |
927 | #endif | |
928 | -vcs_build_args="-Mupdate +warn=all +lint=none" | |
929 | -vcs_build_args="+notimingcheck +nospecify" | |
930 | VCS_BUILD_WITH_GPP | |
931 | -vcs_build_args="-cc gcc -cpp g++ -ld g++ -lstdc++" | |
932 | -vcs_build="-Xstrict=0x01 " | |
933 | -vcs_build_args=+v2k | |
934 | #ifndef FC_NO_NIU_T2 | |
935 | #ifndef PLAYBACK | |
936 | -vcs_build_args=" +vc vera/mal.o" | |
937 | -vcs_build_args=" +vc vera/pgVeraWrap.o" | |
938 | -vcs_build_args=" +vc vera/genCpacket.o" | |
939 | -vcs_build_args=" +vc vera/libnet.a" | |
940 | -vcs_build_args=" +vc vera/pgVera.a" | |
941 | -vcs_build_args=" +vc vera/pgRandom.o" | |
942 | #endif // PLAYBACK | |
943 | //-vcs_build_args="$DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.o" | |
944 | #ifndef LINUX | |
945 | -vcs_build_args="$DV_ROOT/verif/env/common/pli/niu_pli/libniu_pli.a" | |
946 | #else | |
947 | -vcs_build_args="$DV_ROOT/verif/env/common/pli/niu_pli/linux/libniu_pli.a" | |
948 | #endif | |
949 | -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.tab" | |
950 | #endif | |
951 | -vcs_use_vera | |
952 | #endif | |
953 | #ifndef AXIS_TL | |
954 | -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/socket/socket_pli.tab" | |
955 | #ifndef LINUX | |
956 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/socket/libsocket_pli.a | |
957 | #else | |
958 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/socket/linux/libsocket_pli.a | |
959 | #endif | |
960 | #endif | |
961 | -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/monitor/monitor_pli.tab" | |
962 | #ifdef AXIS_64BIT | |
963 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli_64.a | |
964 | #else | |
965 | #ifndef LINUX | |
966 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli.a | |
967 | #else | |
968 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/linux/libmonitor_pli.a | |
969 | #endif | |
970 | #endif | |
971 | #ifndef FC_NO_PEU_VERA | |
972 | #ifndef PLAYBACK | |
973 | -vcs_build_args=-P $DV_ROOT/verif/env/fnx/clib/report/report.tab | |
974 | -vcs_build_args=vera/report.a | |
975 | // -vcs_build_args=-P vera/denali_pcie.tab | |
976 | -vcs_build_args=-P $DENALI/verilog/pli.tab | |
977 | -vcs_build_args=$DENALI/verilog/denverlib.o | |
978 | #endif // PLAYBACK | |
979 | #endif | |
980 | -vcs_run_args=+SLAM_INIT_CMP | |
981 | -vcs_run_args=+DRAM | |
982 | -vcs_run_args=+no_slam_init | |
983 | -vcs_run_args=+slam_value=0 | |
984 | -vcs_run_args=+vera_exit_on_error | |
985 | -vcs_run_args=+mac0 | |
986 | -vcs_run_args=+mac1 | |
987 | -vcs_run_args=+mac2 | |
988 | -vcs_run_args=+mac3 | |
989 | -vcs_run_args=+rxc | |
990 | -vcs_run_args=+vera_disable_final_report | |
991 | -vcs_run_args=+vera_semaphore_size=64000 | |
992 | -vcs_run_args=+vera_mailbox_size=64000 | |
993 | -vcs_run_args=+0in_debug+no_auto_message_wrap | |
994 | #ifndef FC_NO_PEU_VERA | |
995 | -vcs_run_args=+vera_directc=$VERA_LIBDIR/denali_pcie.dl:$VERA_HOME/lib/libdenaliddv.so | |
996 | #endif | |
997 | -vcs_run_args=+0in_checker_finish_delay+3000 | |
998 | -vcs_run_args=+skt_timeout=50000 | |
999 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_register.data ." | |
1000 | -post_process_cmd="regreport -1 | tee status.log" | |
1001 | -midas_args=-DL2_REG_PROG | |
1002 | // -vera_vcon_file=cmp_top.vcon | |
1003 | -vera_vcon_file=fc_top.vcon | |
1004 | ||
1005 | // Note that some test vector options are handled in fc.config | |
1006 | ||
1007 | #ifdef DTM15_SLAM_DP1 | |
1008 | -vcs_run_args=+serdes_dtm1=1 | |
1009 | -vcs_run_args=+serdes_dtm2=0 | |
1010 | -vcs_run_args=+dbg_port_config=001 | |
1011 | #endif //DTM15_SLAM_DP1 | |
1012 | ||
1013 | #ifdef DTM15_SLAM_DP2 | |
1014 | -vcs_run_args=+serdes_dtm1=0 | |
1015 | -vcs_run_args=+serdes_dtm2=1 | |
1016 | -vcs_run_args=+dbg_port_config=001 | |
1017 | #endif //DTM15_SLAM_DP2 | |
1018 | ||
1019 | #ifdef DTM15_SLAM | |
1020 | -vcs_build_args=+define+SLAM_VECTORS | |
1021 | -vcs_build_args=+define+DTM_ENABLED | |
1022 | -vcs_build_args=+define+FBDIMM_BUG_107438 | |
1023 | -vcs_build_args=+define+TI_wizaccel | |
1024 | ||
1025 | -diaglist_cpp_args=-DSLAM_VECTORS=SLAM_VECTORS | |
1026 | -tg_seed=1 | |
1027 | -vcs_run_args=+info | |
1028 | -vcs_run_args=+show_delta | |
1029 | -vcs_run_args=+show_memop | |
1030 | -vcs_run_args=+0in_no_statistics | |
1031 | -nofast_boot | |
1032 | -max_cycle=9999999 | |
1033 | -rtl_timeout=1000000 | |
1034 | -vcs_run_args=+mcu_errmon_disable | |
1035 | -vcs_run_args=+mcu_fmon_disable | |
1036 | -vcs_run_args=+noDebugChecks | |
1037 | -vcs_run_args=+CMPDR_RATIO_15 | |
1038 | -midas_args=-DDTM_ENABLED | |
1039 | -vcs_run_args=+DTM_ENABLED | |
1040 | -vcs_run_args=+PCIE_REF_CLK_104 | |
1041 | -vcs_run_args=+PEU_TEST | |
1042 | -vcs_run_args=+PEU_DTM_PCIE_SKEW_LANE0_UI=20 | |
1043 | // The following doesn't work because $DV_ROOT is not expanded by sims 1.270 | |
1044 | // -use_denalirc=$DV_ROOT/verif/env/ilu_peu/.denalirc_bypass_training | |
1045 | -vcs_run_args=+set_channel_read_latency=0x1717 | |
1046 | -midas_args=-DSLAM_VECTORS | |
1047 | -vcs_run_args=+SLAM_VECTORS | |
1048 | -midas_args=-DSSI_CLK_4 | |
1049 | -vcs_run_args=+SSI_CLK_4 | |
1050 | -vcs_run_args=+ssi_mon | |
1051 | -midas_args=-DSSI_STATUS | |
1052 | -vcs_run_args=+SSI_STATUS | |
1053 | -vcs_run_args=+TCK_PERIOD=9600 | |
1054 | -midas_args=-DBOOTPROM_INIT | |
1055 | -midas_args=-DSYNC_SLAM_NO_SLAM | |
1056 | ||
1057 | #endif // DTM15_SLAM | |
1058 | ||
1059 | #ifdef DTM15_SLAM_DUMP | |
1060 | -vcs_run_args=+DUMP_LIMIT | |
1061 | -vcs_run_args=+DUMP_PINS | |
1062 | -vcs_run_args=+DUMP_DEBUG_PORT | |
1063 | -debussy | |
1064 | -fsdb2vcd | |
1065 | #endif // DTM15_SLAM_DUMP | |
1066 | ||
1067 | #ifdef DTM15_NONSLAM_DP1 | |
1068 | -midas_args=-DSERDES_DTM1=1 | |
1069 | -midas_args=-DSERDES_DTM2=0 | |
1070 | #endif // DTM15_NONSLAM_DP1 | |
1071 | ||
1072 | #ifdef DTM15_NONSLAM_DP2 | |
1073 | -midas_args=-DSERDES_DTM1=0 | |
1074 | -midas_args=-DSERDES_DTM2=1 | |
1075 | #endif // DTM15_NONSLAM_DP2 | |
1076 | ||
1077 | ||
1078 | #ifdef DTM15_NONSLAM | |
1079 | -vcs_build_args=+define+NON_SLAM_VECTORS | |
1080 | -vcs_build_args=+define+DTM_ENABLED | |
1081 | -vcs_build_args=+define+FBDIMM_BUG_107438 | |
1082 | -vcs_build_args=+define+TI_wizaccel | |
1083 | -vcs_build_args=+define+FULL_RESET | |
1084 | -vcs_build_args=+define+FAST_FLUSH | |
1085 | ||
1086 | -diaglist_cpp_args=-DNON_SLAM_VECTORS=NON_SLAM_VECTORS | |
1087 | -tg_seed=1 | |
1088 | -vcs_run_args=+info | |
1089 | -vcs_run_args=+show_delta | |
1090 | -vcs_run_args=+show_memop | |
1091 | -vcs_run_args=+ssi_mon | |
1092 | -vcs_run_args=+0in_no_statistics | |
1093 | -nofast_boot | |
1094 | -max_cycle=9999999 | |
1095 | -rtl_timeout=2000000000 | |
1096 | -vcs_run_args=+th_timeout=2000000000 | |
1097 | ||
1098 | -vcs_run_args=+mcu_errmon_disable | |
1099 | -vcs_run_args=+mcu_fmon_disable | |
1100 | -vcs_run_args=+noDebugChecks | |
1101 | -midas_args=-DCMPDR_RATIO_15 | |
1102 | -vcs_run_args=+DTM_ENABLED | |
1103 | -midas_args=-DDTM_ENABLED | |
1104 | -vcs_run_args=+PCIE_REF_CLK_104 | |
1105 | -vcs_run_args=+PEU_TEST | |
1106 | -vcs_run_args=+PEU_DTM_PCIE_SKEW_LANE0_UI=20 | |
1107 | -midas_args=-DMCU_CHANNEL_DATA=0x0000000000170017 | |
1108 | -vcs_run_args=+NON_SLAM_VECTORS | |
1109 | -midas_args=-DNON_SLAM_VECTORS | |
1110 | -vcs_run_args=+ssi_mon | |
1111 | -vcs_run_args=+SSI_STATUS | |
1112 | -midas_args=-DSSI_STATUS | |
1113 | -vcs_run_args=+TCK_PERIOD=9600 | |
1114 | -midas_args=-DCCU_REG_PROG | |
1115 | -midas_args=-DL2_REG_PROG | |
1116 | -vcs_run_args=+NO_MCU_CSR_SLAM | |
1117 | -midas_args=-DBOOTPROM_INIT | |
1118 | -midas_args=-DWARM_RESET_INIT | |
1119 | -vcs_run_args=+NO_CCU_CSR_SLAM | |
1120 | -midas_args=-DNO_SLAM_INIT_MCUCTL | |
1121 | ||
1122 | -vcs_run_args=+noUserEvents | |
1123 | -vcs_run_args=+lsu_mon_off | |
1124 | -vcs_run_args=+l2esr_mon_off | |
1125 | -vcs_run_args=+mcuesr_mon_disable | |
1126 | -vcs_run_args=+nb_crc_mon_disable | |
1127 | -vcs_run_args=+mcusat_cov_mon_disable | |
1128 | -vcs_run_args=+disable_refresh_checker | |
1129 | -vcs_run_args=+gchkr_off | |
1130 | ||
1131 | #endif // DTM15_NONSLAM | |
1132 | ||
1133 | #ifdef DTM15_NONSLAM_DUMP | |
1134 | -vcs_run_args=+DUMP_LIMIT | |
1135 | -vcs_run_args=+DUMP_PINS | |
1136 | -vcs_run_args=+DUMP_DEBUG_PORT | |
1137 | -debussy | |
1138 | -fsdb2vcd | |
1139 | #endif // DTM15_NONSLAM_DUMP | |
1140 |