projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: niu_tasks.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | task assert_mdint; | |
| 36 | input[2:0] id; | |
| 37 | begin | |
| 38 | if(id==0) begin | |
| 39 | $display("assert_mdint id=0 time=%0d\n", $time); | |
| 40 | force tb_top.cpu.XAUI_MDINT0_L = 1'b0; | |
| 41 | end | |
| 42 | if(id==1) begin | |
| 43 | $display("assert_mdint id=1 time=%0d\n", $time); | |
| 44 | force tb_top.cpu.XAUI_MDINT1_L = 1'b0; | |
| 45 | end | |
| 46 | end | |
| 47 | endtask | |
| 48 | ||
| 49 | task deassert_mdint; | |
| 50 | input[2:0] id; | |
| 51 | begin | |
| 52 | if(id==0) begin | |
| 53 | $display("deassert_mdint id=0 time=%0d\n", $time); | |
| 54 | release tb_top.cpu.XAUI_MDINT0_L; | |
| 55 | end | |
| 56 | if(id==1) begin | |
| 57 | $display("deassert_mdint id=1 time=%0d\n", $time); | |
| 58 | release tb_top.cpu.XAUI_MDINT1_L; | |
| 59 | end | |
| 60 | end | |
| 61 | endtask | |
| 62 | ||
| 63 | task check_mdint_status; | |
| 64 | input[2:0] id; | |
| 65 | inout status; | |
| 66 | begin | |
| 67 | if(id==0) begin | |
| 68 | $display("check_mdint_status=%0b id=0 time=%0d\n", tb_top.cpu.XAUI_MDINT0_L, $time); | |
| 69 | status=tb_top.cpu.XAUI_MDINT0_L; | |
| 70 | end | |
| 71 | if(id==1) begin | |
| 72 | $display("check_mdint_status=%0b id=1 time=%0d\n", tb_top.cpu.XAUI_MDINT1_L, $time); | |
| 73 | status=tb_top.cpu.XAUI_MDINT1_L; | |
| 74 | end | |
| 75 | end | |
| 76 | endtask | |
| 77 | ||
| 78 | ||
| 79 | task force_rxc_cksum_be_partial; | |
| 80 | ||
| 81 | begin | |
| 82 | `ifdef NIU_SYSTEMC_T2 | |
| 83 | `else | |
| 84 | `ifdef NIU_GATE | |
| 85 | $display("ERROR: FORCE_rxc_cksum_be_partial not supported in NIU_GATES...yet\n"); | |
| 86 | `else | |
| 87 | $display("FORCE_rxc_cksum_be_partial\n"); | |
| 88 | force `RTX.rxc.ipp_top_0.ipp0.sum_unit_0.ipp_full_cksum = 1'h0; | |
| 89 | force `RTX.rxc.ipp_top_0.ipp1.sum_unit_0.ipp_full_cksum = 1'h0; | |
| 90 | `endif | |
| 91 | `endif // NIU_SYSTEMC_T2 | |
| 92 | end | |
| 93 | endtask | |
| 94 | ||
| 95 | task force_tcam_entry; | |
| 96 | input [7:0] index; | |
| 97 | input [199:0] tcam_key; | |
| 98 | begin | |
| 99 | ||
| 100 | `ifdef NIU_SYSTEMC_T2 | |
| 101 | `else | |
| 102 | ||
| 103 | `ifdef MAC_SAT | |
| 104 | begin | |
| 105 | end | |
| 106 | `else // if not MAC_SAT | |
| 107 | begin | |
| 108 | // $display("n2_niu_tb_top.v: force_tcam_entry(): FORCE_TCAM index = %h, data = %h", index, tcam_key); | |
| 109 | `ifdef NIU_GATE | |
| 110 | tb_top.cpu.rtx.rxc_niu_tcam_0_niu_scam0_cam_128x200_0.niu_tcam_ary0.mem_data[index] = tcam_key; | |
| 111 | `else | |
| 112 | tb_top.cpu.rtx.rxc.niu_tcam_0.niu_scam0.cam_128x200_0.niu_tcam_ary0.mem_data[index] = tcam_key; | |
| 113 | `endif | |
| 114 | end | |
| 115 | `endif // end for mac_sat/not | |
| 116 | ||
| 117 | `endif // NIU_SYSTEMC_T2 | |
| 118 | end | |
| 119 | endtask | |
| 120 | ||
| 121 | ||
| 122 | task backdoor_init_tcam; | |
| 123 | integer ii; | |
| 124 | begin | |
| 125 | ||
| 126 | `ifdef NIU_SYSTEMC_T2 | |
| 127 | `else | |
| 128 | ||
| 129 | `ifdef MAC_SAT | |
| 130 | begin | |
| 131 | end | |
| 132 | `else | |
| 133 | begin | |
| 134 | // $display("n2_niu_tb_top.v: FORCE_TCAM keys to 0s and masks to 1s"); | |
| 135 | `ifdef NIU_GATE | |
| 136 | for(ii=0;ii<128;ii=ii+1) begin | |
| 137 | tb_top.cpu.rtx.rxc_niu_tcam_0_niu_scam0_cam_128x200_0.niu_tcam_ary0.mem_data[ii] = {200{1'b0}}; | |
| 138 | tb_top.cpu.rtx.rxc_niu_tcam_0_niu_scam0_cam_128x200_0.niu_tcam_ary0.mem_mask[ii] = {200{1'b1}}; | |
| 139 | end | |
| 140 | `else | |
| 141 | for(ii=0;ii<128;ii=ii+1) begin | |
| 142 | tb_top.cpu.rtx.rxc.niu_tcam_0.niu_scam0.cam_128x200_0.niu_tcam_ary0.mem_data[ii] = {200{1'b0}}; | |
| 143 | tb_top.cpu.rtx.rxc.niu_tcam_0.niu_scam0.cam_128x200_0.niu_tcam_ary0.mem_mask[ii] = {200{1'b1}}; | |
| 144 | end | |
| 145 | `endif | |
| 146 | end | |
| 147 | `endif | |
| 148 | ||
| 149 | `endif // NIU_SYSTEMC_T2 | |
| 150 | end | |
| 151 | endtask | |
| 152 | ||
| 153 | // Added this task to slam Vlan table -MAQ | |
| 154 | ||
| 155 | task force_vlan_tbl_entry; | |
| 156 | input [15:0] mem_addr; | |
| 157 | input [17:0] mem_wr_data; | |
| 158 | ||
| 159 | begin | |
| 160 | ||
| 161 | `ifdef NIU_SYSTEMC_T2 | |
| 162 | $display("force_vlan_tbl_entry is not supported in niu systemc model!"); | |
| 163 | `else | |
| 164 | ||
| 165 | `ifdef NIU_GATE | |
| 166 | case(mem_addr[11:7]) | |
| 167 | ||
| 168 | ||
| 169 | 5'b0 : begin | |
| 170 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 171 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 172 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 173 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 174 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 175 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 176 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 177 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 178 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 179 | end | |
| 180 | 5'b1 : begin | |
| 181 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 182 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 183 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 184 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 185 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 186 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 187 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 188 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 189 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 190 | end | |
| 191 | 5'b10 : begin | |
| 192 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 193 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 194 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 195 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 196 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 197 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 198 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 199 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 200 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 201 | end | |
| 202 | 5'b11 : begin | |
| 203 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 204 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 205 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 206 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 207 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 208 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 209 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 210 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 211 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 212 | end | |
| 213 | 5'b100 : begin | |
| 214 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 215 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 216 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 217 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 218 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 219 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 220 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 221 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 222 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 223 | end | |
| 224 | 5'b101 : begin | |
| 225 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 226 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 227 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 228 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 229 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 230 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 231 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 232 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 233 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 234 | end | |
| 235 | 5'b110 : begin | |
| 236 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 237 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 238 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 239 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 240 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 241 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 242 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 243 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 244 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 245 | end | |
| 246 | 5'b111 : begin | |
| 247 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 248 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 249 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 250 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 251 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 252 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 253 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 254 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 255 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 256 | end | |
| 257 | 5'b1000 : begin | |
| 258 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 259 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 260 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 261 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 262 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 263 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 264 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 265 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 266 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 267 | end | |
| 268 | 5'b1001 : begin | |
| 269 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 270 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 271 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 272 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 273 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 274 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 275 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 276 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 277 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 278 | end | |
| 279 | 5'b1010 : begin | |
| 280 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 281 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 282 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 283 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 284 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 285 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 286 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 287 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 288 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 289 | end | |
| 290 | 5'b1011 : begin | |
| 291 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 292 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 293 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 294 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 295 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 296 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 297 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 298 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 299 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 300 | end | |
| 301 | 5'b1100 : begin | |
| 302 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 303 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 304 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 305 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 306 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 307 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 308 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 309 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 310 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 311 | end | |
| 312 | 5'b1101 : begin | |
| 313 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 314 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 315 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 316 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 317 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 318 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 319 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 320 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 321 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 322 | end | |
| 323 | 5'b1110 : begin | |
| 324 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 325 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 326 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 327 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 328 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 329 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 330 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 331 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 332 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 333 | end | |
| 334 | 5'b1111 : begin | |
| 335 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 336 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 337 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 338 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 339 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 340 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 341 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 342 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 343 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 344 | end | |
| 345 | 5'b10000 : begin | |
| 346 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 347 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 348 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 349 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 350 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 351 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 352 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 353 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 354 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 355 | end | |
| 356 | 5'b10001 : begin | |
| 357 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 358 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 359 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 360 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 361 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 362 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 363 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 364 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 365 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 366 | end | |
| 367 | 5'b10010 : begin | |
| 368 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 369 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 370 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 371 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 372 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 373 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 374 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 375 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 376 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 377 | end | |
| 378 | 5'b10011 : begin | |
| 379 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 380 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 381 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 382 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 383 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 384 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 385 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 386 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 387 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 388 | end | |
| 389 | 5'b10100 : begin | |
| 390 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 391 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 392 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 393 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 394 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 395 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 396 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 397 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 398 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 399 | end | |
| 400 | 5'b10101 : begin | |
| 401 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 402 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 403 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 404 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 405 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 406 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 407 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 408 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 409 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 410 | end | |
| 411 | 5'b10110 : begin | |
| 412 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 413 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 414 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 415 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 416 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 417 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 418 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 419 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 420 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 421 | end | |
| 422 | 5'b10111 : begin | |
| 423 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 424 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 425 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 426 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 427 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 428 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 429 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 430 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 431 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 432 | end | |
| 433 | 5'b11000 : begin | |
| 434 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 435 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 436 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 437 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 438 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 439 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 440 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 441 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 442 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 443 | end | |
| 444 | 5'b11001 : begin | |
| 445 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 446 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 447 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 448 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 449 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 450 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 451 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 452 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 453 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 454 | end | |
| 455 | 5'b11010 : begin | |
| 456 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 457 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 458 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 459 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 460 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 461 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 462 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 463 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 464 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 465 | end | |
| 466 | 5'b11011 : begin | |
| 467 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 468 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 469 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 470 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 471 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 472 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 473 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 474 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 475 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 476 | end | |
| 477 | 5'b11100 : begin | |
| 478 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 479 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 480 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 481 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 482 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 483 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 484 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 485 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 486 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 487 | end | |
| 488 | 5'b11101 : begin | |
| 489 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 490 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 491 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 492 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 493 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 494 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 495 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 496 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 497 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 498 | end | |
| 499 | 5'b11110 : begin | |
| 500 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 501 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 502 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 503 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 504 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 505 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 506 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 507 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 508 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 509 | end | |
| 510 | 5'b11111 : begin | |
| 511 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 512 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 513 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 514 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 515 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 516 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 517 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 518 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 519 | tb_top.cpu.rtx.rxc_niu_ram_4096x9_0_ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 520 | end | |
| 521 | endcase | |
| 522 | ||
| 523 | `else | |
| 524 | case(mem_addr[11:7]) | |
| 525 | ||
| 526 | ||
| 527 | 5'b0 : begin | |
| 528 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 529 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 530 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 531 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 532 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 533 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 534 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 535 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 536 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 537 | end | |
| 538 | 5'b1 : begin | |
| 539 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 540 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 541 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 542 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 543 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 544 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 545 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 546 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 547 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 548 | end | |
| 549 | 5'b10 : begin | |
| 550 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 551 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 552 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 553 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 554 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 555 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 556 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 557 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 558 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 559 | end | |
| 560 | 5'b11 : begin | |
| 561 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 562 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 563 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 564 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 565 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 566 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 567 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 568 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 569 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 570 | end | |
| 571 | 5'b100 : begin | |
| 572 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 573 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 574 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 575 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 576 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 577 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 578 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 579 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 580 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 581 | end | |
| 582 | 5'b101 : begin | |
| 583 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 584 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 585 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 586 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 587 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 588 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 589 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 590 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 591 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 592 | end | |
| 593 | 5'b110 : begin | |
| 594 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 595 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 596 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 597 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 598 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 599 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 600 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 601 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 602 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 603 | end | |
| 604 | 5'b111 : begin | |
| 605 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b16.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 606 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b14.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 607 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b12.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 608 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b10.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 609 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b8.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 610 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b6.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 611 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b4.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 612 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b2.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 613 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b0.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 614 | end | |
| 615 | 5'b1000 : begin | |
| 616 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 617 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 618 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 619 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 620 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 621 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 622 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 623 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 624 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 625 | end | |
| 626 | 5'b1001 : begin | |
| 627 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 628 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 629 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 630 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 631 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 632 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 633 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 634 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 635 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 636 | end | |
| 637 | 5'b1010 : begin | |
| 638 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 639 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 640 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 641 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 642 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 643 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 644 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 645 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 646 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 647 | end | |
| 648 | 5'b1011 : begin | |
| 649 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 650 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 651 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 652 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 653 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 654 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 655 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 656 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 657 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 658 | end | |
| 659 | 5'b1100 : begin | |
| 660 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 661 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 662 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 663 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 664 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 665 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 666 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 667 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 668 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 669 | end | |
| 670 | 5'b1101 : begin | |
| 671 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 672 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 673 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 674 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 675 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 676 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 677 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 678 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 679 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 680 | end | |
| 681 | 5'b1110 : begin | |
| 682 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 683 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 684 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 685 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 686 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 687 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 688 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 689 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 690 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 691 | end | |
| 692 | 5'b1111 : begin | |
| 693 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b17.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 694 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b15.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 695 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b13.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 696 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b11.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 697 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b9.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 698 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b7.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 699 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b5.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 700 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b3.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 701 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_up.array_2k.b1.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 702 | end | |
| 703 | 5'b10000 : begin | |
| 704 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 705 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 706 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 707 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 708 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 709 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 710 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 711 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 712 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 713 | end | |
| 714 | 5'b10001 : begin | |
| 715 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 716 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 717 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 718 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 719 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 720 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 721 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 722 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 723 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 724 | end | |
| 725 | 5'b10010 : begin | |
| 726 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 727 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 728 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 729 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 730 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 731 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 732 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 733 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 734 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 735 | end | |
| 736 | 5'b10011 : begin | |
| 737 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 738 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 739 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 740 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 741 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 742 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 743 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 744 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 745 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 746 | end | |
| 747 | 5'b10100 : begin | |
| 748 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 749 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 750 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 751 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 752 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 753 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 754 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 755 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 756 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 757 | end | |
| 758 | 5'b10101 : begin | |
| 759 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 760 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 761 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 762 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 763 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 764 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 765 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 766 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 767 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 768 | end | |
| 769 | 5'b10110 : begin | |
| 770 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 771 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 772 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 773 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 774 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 775 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 776 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 777 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 778 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 779 | end | |
| 780 | 5'b10111 : begin | |
| 781 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b16.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 782 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b14.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 783 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b12.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 784 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b10.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 785 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b8.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 786 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b6.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 787 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b4.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 788 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b2.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 789 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b0.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 790 | end | |
| 791 | 5'b11000 : begin | |
| 792 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 793 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 794 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 795 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 796 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 797 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 798 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 799 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 800 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b0.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 801 | end | |
| 802 | 5'b11001 : begin | |
| 803 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 804 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 805 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 806 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 807 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 808 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 809 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 810 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 811 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b1.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 812 | end | |
| 813 | 5'b11010 : begin | |
| 814 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 815 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 816 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 817 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 818 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 819 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 820 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 821 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 822 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b2.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 823 | end | |
| 824 | 5'b11011 : begin | |
| 825 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 826 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 827 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 828 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 829 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 830 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 831 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 832 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 833 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b3.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 834 | end | |
| 835 | 5'b11100 : begin | |
| 836 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 837 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 838 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 839 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 840 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 841 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 842 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 843 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 844 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b4.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 845 | end | |
| 846 | 5'b11101 : begin | |
| 847 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 848 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 849 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 850 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 851 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 852 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 853 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 854 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 855 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b5.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 856 | end | |
| 857 | 5'b11110 : begin | |
| 858 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 859 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 860 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 861 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 862 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 863 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 864 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 865 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 866 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b6.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 867 | end | |
| 868 | 5'b11111 : begin | |
| 869 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b17.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[8]; | |
| 870 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b15.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[7]; | |
| 871 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b13.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[6]; | |
| 872 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b11.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[5]; | |
| 873 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b9.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[4]; | |
| 874 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b7.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[3]; | |
| 875 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b5.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[2]; | |
| 876 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b3.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[1]; | |
| 877 | tb_top.cpu.rtx.rxc.niu_ram_4096x9_0.ram_4096x9_0.niu_sp_4096x9s_bank.array_dn.array_2k.b1.mem.b7.mem[mem_addr[6:0]]=mem_wr_data[0]; | |
| 878 | end | |
| 879 | endcase | |
| 880 | ||
| 881 | `endif // GATESIM...else | |
| 882 | ||
| 883 | `endif // NIU_SYSTEMC_T2 | |
| 884 | ||
| 885 | end | |
| 886 | ||
| 887 | endtask | |
| 888 |