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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ios_l2_stub.if.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #inc "ios_l2_stub_inc.pal" | |
36 | ||
37 | #ifndef INC_IOS_IF_VRH | |
38 | #define INC_IOS_IF_VRH | |
39 | ||
40 | #include "top_defines.vrh" | |
41 | ||
42 | .for($b=0; $b<$BANKS; $b++) { | |
43 | interface l2_${b}_req { | |
44 | input clk CLOCK verilog_node "`SII.l2clk"; | |
45 | input req_vld INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_l2t${b}_req_vld"; | |
46 | input [31:0] req INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_l2t${b}_req"; | |
47 | input [6:0] ecc INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_l2b${b}_ecc"; | |
48 | } | |
49 | ||
50 | .} | |
51 | ||
52 | .for($b=0; $b<8; $b++) { | |
53 | interface fc_l2b${b}_sio{ | |
54 | #ifndef GATESIM | |
55 | input clk CLOCK verilog_node "`CPU.l2b${b}.gclk"; | |
56 | //input clk CLOCK verilog_node "`CPU.l2b${b}.rdmard.l2clk"; // doesn't toggle when the bank is disabled | |
57 | input l2t_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2b${b}.rdmard.l2t_l2b_ctag_en_c7_reg"; | |
58 | input [31:0] l2t_ctag INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2b${b}.rdmard.l2t_l2b_ctag_c7"; | |
59 | input l2t_data_vld INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2b${b}.rdmard.l2t_l2b_we_c8"; | |
60 | input [623:0] l2t_data INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2b${b}.rdmard.l2d_l2b_decc_out_c8"; | |
61 | #else | |
62 | input clk CLOCK verilog_node "`SIO.l2clk"; | |
63 | input l2_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${b}_sio_ctag_vld"; | |
64 | input [31:0] l2_data INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${b}_sio_data"; | |
65 | #endif | |
66 | } | |
67 | .} | |
68 | ||
69 | .for($b=0; $b<8; $b++) { | |
70 | interface fc_l2b${b}_sio_fcerr{ | |
71 | input clk CLOCK verilog_node "`SIO.l2clk"; | |
72 | input l2_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${b}_sio_ctag_vld"; | |
73 | input [31:0] l2_data INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${b}_sio_data"; | |
74 | } | |
75 | .} | |
76 | ||
77 | interface ncu_pb { | |
78 | input pm INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_pm"; | |
79 | input ba01 INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_ba01"; | |
80 | input ba23 INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_ba23"; | |
81 | input ba45 INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_ba45"; | |
82 | input ba67 INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_ba67"; | |
83 | } | |
84 | ||
85 | #endif | |
86 |