Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / fc / vera / stubs / include / ios_l2_stub_ports_binds.vrhpal

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ios_l2_stub_ports_binds.vrhpal
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#inc "ios_l2_stub_inc.pal"

#ifndef INC_IOS_PORTS_BINDS_VRH
#define INC_IOS_PORTS_BINDS_VRH

#include "top_defines.vrh"

// for L2 STUB interface
port l2_stub_port {
        clk;
        req_vld;
        req;
        ecc;
}

.for($b=0; $b<$BANKS; $b++) {
bind l2_stub_port l2_stub_bind${b} {
        clk             l2_${b}_req.clk;
        req_vld         l2_${b}_req.req_vld;
        req             l2_${b}_req.req;
        ecc             l2_${b}_req.ecc;
}

.}

// for L2 STUB interface
port fc_l2_sio_port {
	clk;
#ifndef GATESIM
	ctag_vld;
	data_vld;
	data;
	ctag;
#else
	ctag_vld;
	data;
#endif
}

.for($b=0; $b<8; $b++) {
bind fc_l2_sio_port fc_l2_sio_bind${b} {
#ifndef GATESIM
	clk		fc_l2b${b}_sio.clk;
	ctag_vld	fc_l2b${b}_sio.l2t_ctag_vld;
	data_vld	fc_l2b${b}_sio.l2t_data_vld;
	data		fc_l2b${b}_sio.l2t_data;
	ctag		fc_l2b${b}_sio.l2t_ctag;
#else
	clk		fc_l2b${b}_sio.clk;
	ctag_vld	fc_l2b${b}_sio.l2_ctag_vld;
	data		fc_l2b${b}_sio.l2_data;
#endif
}

.}

// for L2 STUB interface used in FC RAS Diags
port fc_l2_sio_port_fcerr {
        clk;
        ctag_vld;
        data;
}

.for($b=0; $b<8; $b++) {
bind fc_l2_sio_port_fcerr fc_l2_sio_fc_err_bind${b} {
        clk             fc_l2b${b}_sio_fcerr.clk;
        ctag_vld        fc_l2b${b}_sio_fcerr.l2_ctag_vld;
        data            fc_l2b${b}_sio_fcerr.l2_data;
}
.}


#endif