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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fnx / vlib / FNXPCIEXactor / src / FNXPCIEXactorUtilities.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: FNXPCIEXactorUtilities.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36
37// FNX Basic Utilities Library
38#include "FNXBasicUtilities.vrh"
39
40// DenaliPCIE libary
41#include "DenaliPCIE.vri"
42
43// FNXPCIEXactor library
44#include "FNXPCIEXactorDefines.vri"
45
46// report library
47#include "cReport.vrh"
48#include "FNXPCIEXactorReportMacros.vri"
49
50class FNXPCIEXactorUtilities {
51
52 // Base Class and Method Names For QR Macros
53 local string ClassName = "FNXPCIEXactorUtilities";
54 local string MethodName = null;
55
56 // private members
57 local ReportClass MyReport;
58 local string XactorName;
59
60 // public members
61 FNXRandomUtil RandUtil;
62
63 // constructor
64 task new( ReportClass _Report, string _XactorName );
65
66 // public methods
67 function integer FindXValues( bit [FNX_PCIE_XTR_EXPECT_PKT_MAX-1:0] Pkt );
68 function bit PacketEquals( bit [FNX_PCIE_XTR_EXPECT_PKT_MAX-1:0] PktA,
69 bit [FNX_PCIE_XTR_EXPECT_PKT_MAX-1:0] PktB );
70 function bit TypeIsMsg( bit [FNX_PCIE_XTR_CMN_TYPE_WIDTH-1:0] type );
71 function bit TypeIsMsgD( bit [FNX_PCIE_XTR_CMN_TYPE_WIDTH-1:0] type );
72 function bit FmtTypeIsMsg( bit [FNX_PCIE_XTR_CMN_FMT_TYPE_WIDTH-1:0] fmtType);
73 function bit FmtTypeIsMsgD( bit [FNX_PCIE_XTR_CMN_FMT_TYPE_WIDTH-1:0] fmtType );
74
75 // denali utility methods (bits -> enums)
76 function denaliPcieTlpMsgTypeT MsgCodeToType( bit [FNX_PCIE_XTR_MSG_MESSAGE_CODE_WIDTH-1:0] msg_code );
77 function denaliPcieTlpVDMsgRoutingTypeT MsgRoutingToType( bit [FNX_PCIE_XTR_MSG_ROUTING_WIDTH-1:0] msg_routing );
78 function denaliPcieDllpTypeT DllpTypeToType( bit [FNX_PCIE_XTR_DLLP_TYPE_WIDTH-1:0] DllpType );
79
80 // denali utility methods (integers -> strings)
81 function string denaliRegNumToStr( integer regNum );
82
83 // pcie code -> string conversion methods
84 function string PktTypeToStr( bit [FNX_PCIE_XTR_PKT_TYPE_WIDTH-1:0] pktType );
85 function string DenPktTypeToStr( denaliPciePktTypeT pktType );
86 function string FmtToStr( bit [FNX_PCIE_XTR_CMN_FORMAT_WIDTH-1:0] fmt );
87 function string TypeToStr( bit[FNX_PCIE_XTR_CMN_TYPE_WIDTH-1:0] type );
88 function string FmtTypeToStr( bit[FNX_PCIE_XTR_CMN_FMT_TYPE_WIDTH-1:0] fmtType );
89 function string MsgCodeToStr( bit [FNX_PCIE_XTR_MSG_MESSAGE_CODE_WIDTH-1:0] MsgCode );
90 function string MsgRoutingToStr( bit [FNX_PCIE_XTR_MSG_ROUTING_WIDTH-1:0] MsgRouting );
91 function string CmplStatusToStr( bit[FNX_PCIE_XTR_CMPL_CMPL_STATUS_WIDTH-1:0] CmplStatus );
92 function string DllpTypeToStr( bit [FNX_PCIE_XTR_DLLP_TYPE_WIDTH-1:0] DllpType );
93
94 // misc string conversion methods
95 function string PyldToStr( bit [7:0] pyld[*], string prefixStr, string name );
96 function string ByteStreamToStr( bit[8:0] byteStrm[*], string prefixStr, string name );
97 function string DenaliPktToStr( denaliPciePacket denPkt, integer portNum );
98
99 // denali utility methods (enums -> integer encodings)
100 function integer denaliFCTypeToInt( denaliPcieFcTypeT denFcType );
101
102 // denali utility methods (integer encodings -> enums)
103 function denaliPcieFcTypeT FCEncToDenaliType( integer fcEnc );
104}
105
106
107// constructor
108task FNXPCIEXactorUtilities::new( ReportClass _Report, string _XactorName ) {
109 MyReport = _Report;
110 XactorName = _XactorName;
111 RandUtil = new(MyReport);
112}
113
114// This function returns 1 if X's or Z's are found within the given bit array.
115function integer FNXPCIEXactorUtilities::FindXValues( bit [FNX_PCIE_XTR_EXPECT_PKT_MAX-1:0] Pkt)
116{
117 FindXValues = (^Pkt) === 1'bx;
118}
119
120// This function returns 1 if PktA and PktB are the same. It allows "wildcards"
121function bit FNXPCIEXactorUtilities::PacketEquals( bit [FNX_PCIE_XTR_EXPECT_PKT_MAX-1:0] PktA,
122 bit [FNX_PCIE_XTR_EXPECT_PKT_MAX-1:0] PktB )
123{
124 if (PktA =?= PktB)
125 PacketEquals = 1'b1;
126 else
127 PacketEquals = 1'b0;
128}
129
130function denaliPcieTlpMsgTypeT FNXPCIEXactorUtilities::MsgCodeToType( bit [FNX_PCIE_XTR_MSG_MESSAGE_CODE_WIDTH-1:0] msg_code )
131{
132 case (msg_code) {
133 FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_A : MsgCodeToType = DENALI_PCIE_TL_MSG_INTX_ASSERT_A;
134 FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_B : MsgCodeToType = DENALI_PCIE_TL_MSG_INTX_ASSERT_B;
135 FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_C : MsgCodeToType = DENALI_PCIE_TL_MSG_INTX_ASSERT_C;
136 FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_D : MsgCodeToType = DENALI_PCIE_TL_MSG_INTX_ASSERT_D;
137 FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_A : MsgCodeToType = DENALI_PCIE_TL_MSG_INTX_DEASSERT_A;
138 FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_B : MsgCodeToType = DENALI_PCIE_TL_MSG_INTX_DEASSERT_B;
139 FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_C : MsgCodeToType = DENALI_PCIE_TL_MSG_INTX_DEASSERT_C;
140 FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_D : MsgCodeToType = DENALI_PCIE_TL_MSG_INTX_DEASSERT_D;
141 FNX_PCIE_XTR_MSG_CODE_PM_ACTIVE_STATE_NAK : MsgCodeToType = DENALI_PCIE_TL_MSG_PM_Active_State_Nak;
142 FNX_PCIE_XTR_MSG_CODE_PM_PME : MsgCodeToType = DENALI_PCIE_TL_MSG_PM_PME;
143 FNX_PCIE_XTR_MSG_CODE_PME_TURN_OFF : MsgCodeToType = DENALI_PCIE_TL_MSG_PME_Turn_Off;
144 FNX_PCIE_XTR_MSG_CODE_PME_TO_ACK : MsgCodeToType = DENALI_PCIE_TL_MSG_PME_TO_Ack;
145 FNX_PCIE_XTR_MSG_CODE_ERR_COR : MsgCodeToType = DENALI_PCIE_TL_MSG_ERR_COR;
146 FNX_PCIE_XTR_MSG_CODE_ERR_NONFATAL : MsgCodeToType = DENALI_PCIE_TL_MSG_ERR_NONFATAL;
147 FNX_PCIE_XTR_MSG_CODE_ERR_FATAL : MsgCodeToType = DENALI_PCIE_TL_MSG_ERR_FATAL;
148 FNX_PCIE_XTR_MSG_CODE_LOCK_UNLOCK : MsgCodeToType = DENALI_PCIE_TL_MSG_LOCK_Unlock;
149 FNX_PCIE_XTR_MSG_CODE_SLOT_POWER_LIMIT : MsgCodeToType = DENALI_PCIE_TL_MSG_SLOT_Power_Limit;
150 FNX_PCIE_XTR_MSG_CODE_VD_TYPE0 : MsgCodeToType = DENALI_PCIE_TL_MSG_VD_Type0;
151 FNX_PCIE_XTR_MSG_CODE_VD_TYPE1 : MsgCodeToType = DENALI_PCIE_TL_MSG_VD_Type1;
152 FNX_PCIE_XTR_MSG_CODE_HP_POWER_ON : MsgCodeToType = DENALI_PCIE_TL_MSG_HP_Power_On;
153 FNX_PCIE_XTR_MSG_CODE_HP_POWER_OFF : MsgCodeToType = DENALI_PCIE_TL_MSG_HP_Power_Off;
154 FNX_PCIE_XTR_MSG_CODE_HP_POWER_BLINK : MsgCodeToType = DENALI_PCIE_TL_MSG_HP_Power_Blink;
155 FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_PRESSED : MsgCodeToType = DENALI_PCIE_TL_MSG_HP_Attention_Pressed;
156 FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_ON : MsgCodeToType = DENALI_PCIE_TL_MSG_HP_Attention_On;
157 FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_OFF : MsgCodeToType = DENALI_PCIE_TL_MSG_HP_Attention_Off;
158 FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_BLINK : MsgCodeToType = DENALI_PCIE_TL_MSG_HP_Attention_Blink;
159 default : MsgCodeToType = DENALI_PCIE_TL_MSG_UNKNOWN;
160 }
161}
162
163function denaliPcieTlpVDMsgRoutingTypeT FNXPCIEXactorUtilities::MsgRoutingToType( bit [FNX_PCIE_XTR_MSG_ROUTING_WIDTH-1:0] msg_routing )
164{
165 case (msg_routing) {
166 FNX_PCIE_XTR_MSG_ROUTING_ROUTED_TO_ROOT_CMPLX : MsgRoutingToType = DENALI_PCIE_TL_VDMSG_ROUT_to_RC;
167 FNX_PCIE_XTR_MSG_ROUTING_ROUTED_BY_ID : MsgRoutingToType = DENALI_PCIE_TL_VDMSG_ROUT_by_ID;
168 FNX_PCIE_XTR_MSG_ROUTING_BCAST_FROM_ROOT_CMPLX : MsgRoutingToType = DENALI_PCIE_TL_VDMSG_ROUT_RC_broadcast;
169 FNX_PCIE_XTR_MSG_ROUTING_LOCAL : MsgRoutingToType = DENALI_PCIE_TL_VDMSG_ROUT_local_terminate;
170 FNX_PCIE_XTR_MSG_ROUTING_ROUTED_BY_ADDR,
171 FNX_PCIE_XTR_MSG_ROUTING_GNR_TO_ROOT_CMPLX : MsgRoutingToType = DENALI_PCIE_TL_VDMSG_ROUT_Unknown;
172 default : MsgRoutingToType = DENALI_PCIE_TL_VDMSG_ROUT_Unknown;
173 }
174}
175
176function denaliPcieDllpTypeT FNXPCIEXactorUtilities::DllpTypeToType( bit [FNX_PCIE_XTR_DLLP_TYPE_WIDTH-1:0] DllpType )
177{
178 case (DllpType) {
179 FNX_PCIE_XTR_DLLP_TYPE_ACK : DllpTypeToType = DENALI_PCIE_DL_ACK;
180 FNX_PCIE_XTR_DLLP_TYPE_NAK : DllpTypeToType = DENALI_PCIE_DL_NAK;
181 FNX_PCIE_XTR_DLLP_TYPE_PM_ENTER_L1 : DllpTypeToType = DENALI_PCIE_DL_PM_ENTER_L1;
182 FNX_PCIE_XTR_DLLP_TYPE_PM_ENTER_L23 : DllpTypeToType = DENALI_PCIE_DL_PM_ENTER_L23;
183 FNX_PCIE_XTR_DLLP_TYPE_PM_ACTIVE_ST_REQ_L1 : DllpTypeToType = DENALI_PCIE_DL_PM_ACTIVE_STATE_REQUEST_L1;
184 FNX_PCIE_XTR_DLLP_TYPE_PM_REQUEST_ACK : DllpTypeToType = DENALI_PCIE_DL_PM_REQUEST_ACK;
185 FNX_PCIE_XTR_DLLP_TYPE_VENDOR : DllpTypeToType = DENALI_PCIE_DL_VENDOR;
186 default : {
187 case (DllpType[FNX_PCIE_XTR_DLLP_FC_TYPE_TYPE_INT_SLC]) {
188 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC1_P : DllpTypeToType = DENALI_PCIE_DL_INIT_FC1_P;
189 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC1_NP : DllpTypeToType = DENALI_PCIE_DL_INIT_FC1_NP;
190 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC1_CPL : DllpTypeToType = DENALI_PCIE_DL_INIT_FC1_CPL;
191 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC2_P : DllpTypeToType = DENALI_PCIE_DL_INIT_FC2_P;
192 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC2_NP : DllpTypeToType = DENALI_PCIE_DL_INIT_FC2_NP;
193 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC2_CPL : DllpTypeToType = DENALI_PCIE_DL_INIT_FC2_CPL;
194 FNX_PCIE_XTR_FC_DLLP_TYPE_UPDATE_FC_P : DllpTypeToType = DENALI_PCIE_DL_UPDATE_FC_P;
195 FNX_PCIE_XTR_FC_DLLP_TYPE_UPDATE_FC_NP : DllpTypeToType = DENALI_PCIE_DL_UPDATE_FC_NP;
196 FNX_PCIE_XTR_FC_DLLP_TYPE_UPDATE_FC_CPL : DllpTypeToType = DENALI_PCIE_DL_UPDATE_FC_CPL;
197 default : DllpTypeToType = DENALI_PCIE_DL_UNKNOWN;
198 }
199 }
200 }
201}
202
203function string FNXPCIEXactorUtilities::PktTypeToStr( bit [FNX_PCIE_XTR_PKT_TYPE_WIDTH-1:0] pktType )
204{
205 case (pktType) {
206 FNX_PCIE_XTR_PKT_TYPE_TLP : PktTypeToStr = "TLP";
207 FNX_PCIE_XTR_PKT_TYPE_RAW_TLP : PktTypeToStr = "RAW_TLP";
208 FNX_PCIE_XTR_PKT_TYPE_DLP : PktTypeToStr = "DLP";
209 FNX_PCIE_XTR_PKT_TYPE_RAW_DLP : PktTypeToStr = "RAW_DLP";
210 FNX_PCIE_XTR_PKT_TYPE_DLLP : PktTypeToStr = "DLLP";
211 FNX_PCIE_XTR_PKT_TYPE_PLP : PktTypeToStr = "PLP";
212 FNX_PCIE_XTR_PKT_TYPE_PLLP : PktTypeToStr = "PLLP";
213 FNX_PCIE_XTR_PKT_TYPE_ORDERED_SET : PktTypeToStr = "ORDERED_SET";
214 FNX_PCIE_XTR_PKT_TYPE_RAW_DATA : PktTypeToStr = "RAW_DATA";
215 FNX_PCIE_XTR_PKT_TYPE_TRAINING_SET : PktTypeToStr = "TRAINING_SET";
216 default : PktTypeToStr = "UNKNOWN";
217 }
218}
219
220function string FNXPCIEXactorUtilities::DenPktTypeToStr( denaliPciePktTypeT pktType )
221{
222 case (pktType) {
223 DENALI_PCIE__Tlp : DenPktTypeToStr = "TLP";
224 DENALI_PCIE__RawTlp : DenPktTypeToStr = "RAW_TLP";
225 DENALI_PCIE__Dlp : DenPktTypeToStr = "DLP";
226 DENALI_PCIE__RawDlp : DenPktTypeToStr = "RAW_DLP";
227 DENALI_PCIE__RawDllp : DenPktTypeToStr = "RAW_DLLP";
228 DENALI_PCIE__Dllp : DenPktTypeToStr = "DLLP";
229 DENALI_PCIE__Plp : DenPktTypeToStr = "PLP";
230 DENALI_PCIE__Pllp : DenPktTypeToStr = "PLLP";
231 DENALI_PCIE__OrderedSet : DenPktTypeToStr = "ORDERED_SET";
232 DENALI_PCIE__RawData : DenPktTypeToStr = "RAW_DATA";
233 default : DenPktTypeToStr = "UNKNOWN";
234 }
235}
236
237function string FNXPCIEXactorUtilities::FmtToStr( bit [FNX_PCIE_XTR_CMN_FORMAT_WIDTH-1:0] fmt )
238{
239 string tmp;
240
241 sprintf(tmp, "(%0d'b%b)", FNX_PCIE_XTR_CMN_FORMAT_WIDTH, fmt);
242
243 case (fmt) {
244 2'b00 : FmtToStr = { "DWs=3,Pyld=N", tmp };
245 2'b01 : FmtToStr = { "DWs=4,Pyld=N", tmp };
246 2'b10 : FmtToStr = { "DWs=3,Pyld=Y", tmp };
247 2'b11 : FmtToStr = { "DWs=4,Pyld=Y", tmp };
248 default : FmtToStr = { "UNKNOWN", tmp };
249 }
250}
251
252function string FNXPCIEXactorUtilities::TypeToStr( bit[FNX_PCIE_XTR_CMN_TYPE_WIDTH-1:0] type )
253{
254 string tmp;
255
256 sprintf(tmp, "(%0d'b%b)", FNX_PCIE_XTR_CMN_TYPE_WIDTH, type);
257
258 TypeToStr = null;
259 if (TypeIsMsg(type) || TypeIsMsgD(type))
260 TypeToStr = { "Msg/MsgD", tmp };
261
262 if (TypeToStr === null) {
263 case (type) {
264 FNX_PCIE_XTR_TYPE_MRD : TypeToStr = { "MRd", tmp };
265 FNX_PCIE_XTR_TYPE_MRDLK : TypeToStr = { "MRdLk", tmp };
266 FNX_PCIE_XTR_TYPE_MWR : TypeToStr = { "MWr", tmp };
267 FNX_PCIE_XTR_TYPE_IORD : TypeToStr = { "IORd", tmp };
268 FNX_PCIE_XTR_TYPE_IOWR : TypeToStr = { "IOWr", tmp };
269 FNX_PCIE_XTR_TYPE_CFGRD0,
270 FNX_PCIE_XTR_TYPE_CFGWR0 : TypeToStr = { "CfgRd0/CfgWr0", tmp };
271 FNX_PCIE_XTR_TYPE_CFGRD1,
272 FNX_PCIE_XTR_TYPE_CFGWR1 : TypeToStr = { "CfgRd1/CfgWr1", tmp };
273 FNX_PCIE_XTR_TYPE_CPL,
274 FNX_PCIE_XTR_TYPE_CPLD : TypeToStr = { "CplD/CplD", tmp };
275 FNX_PCIE_XTR_TYPE_CPLLK,
276 FNX_PCIE_XTR_TYPE_CPLDLK : TypeToStr = { "CplLk/CplDLk", tmp };
277 default : TypeToStr = { "UNKNOWN", tmp };
278 }
279 }
280}
281
282function string FNXPCIEXactorUtilities::FmtTypeToStr( bit[FNX_PCIE_XTR_CMN_FMT_TYPE_WIDTH-1:0] fmtType )
283{
284 string tmp;
285
286 sprintf(tmp, "(%0d'b%b)", FNX_PCIE_XTR_CMN_FMT_TYPE_WIDTH, fmtType);
287
288 FmtTypeToStr = null;
289 if (FmtTypeIsMsg(fmtType))
290 FmtTypeToStr = { "Msg", tmp };
291 if (FmtTypeIsMsgD(fmtType))
292 FmtTypeToStr = { "MsgD", tmp };
293
294 if (FmtTypeToStr === null) {
295 case (fmtType) {
296 FNX_PCIE_XTR_FMT_TYPE_MRD_32 : FmtTypeToStr = { "MRd32", tmp };
297 FNX_PCIE_XTR_FMT_TYPE_MRD_64 : FmtTypeToStr = { "MRd64", tmp };
298 FNX_PCIE_XTR_FMT_TYPE_MRDLK_32 : FmtTypeToStr = { "MRdLk32", tmp };
299 FNX_PCIE_XTR_FMT_TYPE_MRDLK_64 : FmtTypeToStr = { "MRdLk64", tmp };
300 FNX_PCIE_XTR_FMT_TYPE_MWR_32 : FmtTypeToStr = { "MWr32", tmp };
301 FNX_PCIE_XTR_FMT_TYPE_MWR_64 : FmtTypeToStr = { "MWr64", tmp };
302 FNX_PCIE_XTR_FMT_TYPE_IORD : FmtTypeToStr = { "IORd", tmp };
303 FNX_PCIE_XTR_FMT_TYPE_IOWR : FmtTypeToStr = { "IOWr", tmp };
304 FNX_PCIE_XTR_FMT_TYPE_CFGRD0 : FmtTypeToStr = { "CfgRd0", tmp };
305 FNX_PCIE_XTR_FMT_TYPE_CFGWR0 : FmtTypeToStr = { "CfgWr0", tmp };
306 FNX_PCIE_XTR_FMT_TYPE_CFGRD1 : FmtTypeToStr = { "CfgRd1", tmp };
307 FNX_PCIE_XTR_FMT_TYPE_CFGWR1 : FmtTypeToStr = { "CfgWr1", tmp };
308 FNX_PCIE_XTR_FMT_TYPE_CPL : FmtTypeToStr = { "Cpl", tmp };
309 FNX_PCIE_XTR_FMT_TYPE_CPLD : FmtTypeToStr = { "CplD", tmp };
310 FNX_PCIE_XTR_FMT_TYPE_CPLLK : FmtTypeToStr = { "CplLk", tmp };
311 FNX_PCIE_XTR_FMT_TYPE_CPLDLK : FmtTypeToStr = { "CplDLk", tmp };
312 default : FmtTypeToStr = { "UNKNOWN", tmp };
313 }
314 }
315}
316
317function string FNXPCIEXactorUtilities::MsgCodeToStr( bit [FNX_PCIE_XTR_MSG_MESSAGE_CODE_WIDTH-1:0] MsgCode )
318{
319 string tmp;
320
321 sprintf(tmp, "(%0d'h%h)", FNX_PCIE_XTR_MSG_MESSAGE_CODE_WIDTH, MsgCode );
322
323 case (MsgCode) {
324 FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_A : MsgCodeToStr = { "INTX_ASSERT_A", tmp };
325 FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_B : MsgCodeToStr = { "INTX_ASSERT_B", tmp };
326 FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_C : MsgCodeToStr = { "INTX_ASSERT_C", tmp };
327 FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_D : MsgCodeToStr = { "INTX_ASSERT_D", tmp };
328 FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_A : MsgCodeToStr = { "INTX_DEASSERT_A", tmp };
329 FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_B : MsgCodeToStr = { "INTX_DEASSERT_B", tmp };
330 FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_C : MsgCodeToStr = { "INTX_DEASSERT_C", tmp };
331 FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_D : MsgCodeToStr = { "INTX_DEASSERT_D", tmp };
332 FNX_PCIE_XTR_MSG_CODE_PM_ACTIVE_STATE_NAK : MsgCodeToStr = { "PM_ACTIVE_STATE_NAK", tmp };
333 FNX_PCIE_XTR_MSG_CODE_PM_PME : MsgCodeToStr = { "PM_PME", tmp };
334 FNX_PCIE_XTR_MSG_CODE_PME_TURN_OFF : MsgCodeToStr = { "PME_TURN_OFF", tmp };
335 FNX_PCIE_XTR_MSG_CODE_PME_TO_ACK : MsgCodeToStr = { "PME_TO_ACK", tmp };
336 FNX_PCIE_XTR_MSG_CODE_ERR_COR : MsgCodeToStr = { "ERR_COR", tmp };
337 FNX_PCIE_XTR_MSG_CODE_ERR_NONFATAL : MsgCodeToStr = { "ERR_NONFATAL", tmp };
338 FNX_PCIE_XTR_MSG_CODE_ERR_FATAL : MsgCodeToStr = { "ERR_FATAL", tmp };
339 FNX_PCIE_XTR_MSG_CODE_LOCK_UNLOCK : MsgCodeToStr = { "UNLOCK", tmp };
340 FNX_PCIE_XTR_MSG_CODE_SLOT_POWER_LIMIT : MsgCodeToStr = { "SET_SLOT_POWER_LIMIT", tmp };
341 FNX_PCIE_XTR_MSG_CODE_VD_TYPE0 : MsgCodeToStr = { "VENDOR_DEFINED_TYPE_0", tmp };
342 FNX_PCIE_XTR_MSG_CODE_VD_TYPE1 : MsgCodeToStr = { "VENDOR_DEFINED_TYPE_1", tmp };
343 FNX_PCIE_XTR_MSG_CODE_HP_POWER_ON : MsgCodeToStr = { "POWER_INDICATOR_ON", tmp };
344 FNX_PCIE_XTR_MSG_CODE_HP_POWER_OFF : MsgCodeToStr = { "POWER_INDICATOR_OFF", tmp };
345 FNX_PCIE_XTR_MSG_CODE_HP_POWER_BLINK : MsgCodeToStr = { "POWER_INDICATOR_BLINK", tmp };
346 FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_PRESSED : MsgCodeToStr = { "ATTENTION_BUTTON_PRESSED", tmp };
347 FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_ON : MsgCodeToStr = { "ATTENTION_INDICATOR_ON", tmp };
348 FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_OFF : MsgCodeToStr = { "ATTENTION_INDICATOR_OFF", tmp };
349 FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_BLINK : MsgCodeToStr = { "ATTENTION_INDICATOR_BLINK", tmp };
350 default : MsgCodeToStr = { "UNKNOWN", tmp };
351 }
352}
353
354function string FNXPCIEXactorUtilities::MsgRoutingToStr( bit [FNX_PCIE_XTR_MSG_ROUTING_WIDTH-1:0] MsgRouting )
355{
356 string tmp;
357
358 sprintf(tmp, "(%0d'h%h)", FNX_PCIE_XTR_MSG_ROUTING_WIDTH, MsgRouting );
359
360 case (MsgRouting) {
361 FNX_PCIE_XTR_MSG_ROUTING_ROUTED_TO_ROOT_CMPLX : MsgRoutingToStr = { "ROUTED_TO_RC", tmp };
362 FNX_PCIE_XTR_MSG_ROUTING_ROUTED_BY_ADDR : MsgRoutingToStr = { "ROUTED_BY_ADDR", tmp };
363 FNX_PCIE_XTR_MSG_ROUTING_ROUTED_BY_ID : MsgRoutingToStr = { "ROUTED_BY_ID", tmp };
364 FNX_PCIE_XTR_MSG_ROUTING_BCAST_FROM_ROOT_CMPLX : MsgRoutingToStr = { "BC_FROM_RC", tmp };
365 FNX_PCIE_XTR_MSG_ROUTING_LOCAL : MsgRoutingToStr = { "LOCAL", tmp };
366 FNX_PCIE_XTR_MSG_ROUTING_GNR_TO_ROOT_CMPLX : MsgRoutingToStr = { "GATHERED_AND_ROUTED_TO_RC", tmp };
367 default : MsgRoutingToStr = { "UNKNOWN", tmp };
368 }
369}
370
371function string FNXPCIEXactorUtilities::CmplStatusToStr( bit[FNX_PCIE_XTR_CMPL_CMPL_STATUS_WIDTH-1:0] CmplStatus )
372{
373 string tmp;
374
375 sprintf(tmp, "(%0d'b%b)", FNX_PCIE_XTR_CMPL_CMPL_STATUS_WIDTH, CmplStatus);
376
377 case (CmplStatus) {
378 FNX_PCIE_XTR_CMPL_STATUS_SC : CmplStatusToStr = { "SC", tmp };
379 FNX_PCIE_XTR_CMPL_STATUS_UR : CmplStatusToStr = { "UR", tmp };
380 FNX_PCIE_XTR_CMPL_STATUS_CRS : CmplStatusToStr = { "CRS", tmp };
381 FNX_PCIE_XTR_CMPL_STATUS_CA : CmplStatusToStr = { "CA", tmp };
382 default : CmplStatusToStr = { "UNKNOWN", tmp };
383 }
384}
385
386function string FNXPCIEXactorUtilities::DllpTypeToStr( bit [FNX_PCIE_XTR_DLLP_TYPE_WIDTH-1:0] DllpType )
387{
388 string tmp;
389
390 sprintf(tmp, "(%0d'h%h)", FNX_PCIE_XTR_DLLP_TYPE_WIDTH, DllpType);
391
392 case (DllpType) {
393 FNX_PCIE_XTR_DLLP_TYPE_ACK : DllpTypeToStr = { "ACK", tmp };
394 FNX_PCIE_XTR_DLLP_TYPE_NAK : DllpTypeToStr = { "NAK", tmp };
395 FNX_PCIE_XTR_DLLP_TYPE_PM_ENTER_L1 : DllpTypeToStr = { "PM_ENTER_L1", tmp };
396 FNX_PCIE_XTR_DLLP_TYPE_PM_ENTER_L23 : DllpTypeToStr = { "PM_ENTER_L23", tmp };
397 FNX_PCIE_XTR_DLLP_TYPE_PM_ACTIVE_ST_REQ_L1 : DllpTypeToStr = { "PM_ACTIVE_ST_REQ_L1", tmp };
398 FNX_PCIE_XTR_DLLP_TYPE_PM_REQUEST_ACK : DllpTypeToStr = { "REQUEST_ACK", tmp };
399 FNX_PCIE_XTR_DLLP_TYPE_VENDOR : DllpTypeToStr = { "VENDOR", tmp };
400 default : {
401 case (DllpType[FNX_PCIE_XTR_DLLP_FC_TYPE_TYPE_INT_SLC]) {
402 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC1_P : DllpTypeToStr = { "INIT_FC1_P", tmp };
403 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC1_NP : DllpTypeToStr = { "INIT_FC1_NP", tmp };
404 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC1_CPL : DllpTypeToStr = { "INIT_FC1_CPL", tmp };
405 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC2_P : DllpTypeToStr = { "INIT_FC2_P", tmp };
406 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC2_NP : DllpTypeToStr = { "INIT_FC2_NP", tmp };
407 FNX_PCIE_XTR_FC_DLLP_TYPE_INIT_FC2_CPL : DllpTypeToStr = { "INIT_FC2_CPL", tmp };
408 FNX_PCIE_XTR_FC_DLLP_TYPE_UPDATE_FC_P : DllpTypeToStr = { "UPDATE_FC_P", tmp };
409 FNX_PCIE_XTR_FC_DLLP_TYPE_UPDATE_FC_NP : DllpTypeToStr = { "UPDATE_FC_NP", tmp };
410 FNX_PCIE_XTR_FC_DLLP_TYPE_UPDATE_FC_CPL : DllpTypeToStr = { "UPDATE_FC_CPL", tmp };
411 default : DllpTypeToStr = { "UNKNOWN", tmp };
412 }
413 }
414 }
415}
416
417function bit FNXPCIEXactorUtilities::TypeIsMsg( bit [FNX_PCIE_XTR_CMN_TYPE_WIDTH-1:0] type )
418{
419 if (type[FNX_PCIE_XTR_TYPE_MSG_FIXED_SLC] === FNX_PCIE_XTR_TYPE_MSG_FIXED)
420 TypeIsMsg = 1;
421 else
422 TypeIsMsg = 0;
423}
424
425function bit FNXPCIEXactorUtilities::TypeIsMsgD( bit [FNX_PCIE_XTR_CMN_TYPE_WIDTH-1:0] type )
426{
427 if (type[FNX_PCIE_XTR_TYPE_MSGD_FIXED_SLC] === FNX_PCIE_XTR_TYPE_MSGD_FIXED)
428 TypeIsMsgD = 1;
429 else
430 TypeIsMsgD = 0;
431}
432
433function bit FNXPCIEXactorUtilities::FmtTypeIsMsg( bit [FNX_PCIE_XTR_CMN_FMT_TYPE_WIDTH-1:0] fmtType )
434{
435 if (fmtType[FNX_PCIE_XTR_FMT_TYPE_MSG_FIXED_SLC] === FNX_PCIE_XTR_FMT_TYPE_MSG_FIXED)
436 FmtTypeIsMsg = 1;
437 else
438 FmtTypeIsMsg = 0;
439}
440
441function bit FNXPCIEXactorUtilities::FmtTypeIsMsgD( bit [FNX_PCIE_XTR_CMN_FMT_TYPE_WIDTH-1:0] fmtType )
442{
443 if (fmtType[FNX_PCIE_XTR_FMT_TYPE_MSGD_FIXED_SLC] === FNX_PCIE_XTR_FMT_TYPE_MSGD_FIXED)
444 FmtTypeIsMsgD = 1;
445 else
446 FmtTypeIsMsgD = 0;
447}
448
449
450function string FNXPCIEXactorUtilities::ByteStreamToStr( bit[8:0] byteStrm[*], string prefixStr, string name )
451{
452 integer i, j, k;
453 bit [31:0] byteStrm_dws[*], byteStrm_dw;
454 integer numLines, numDWs, extraBytes;
455 bit [7:0] pos1, pos2;
456 bit [8:0] tmpByte;
457
458 sprintf( ByteStreamToStr, "%s --- %s DWs ---\n", prefixStr, name );
459
460 // Place Byte Stream Into DWs Array
461 k = 0;
462 byteStrm_dws = new[ (byteStrm.size()/4) ];
463 for (i=0; i < byteStrm_dws.size(); i++) {
464 for (j=3; j >= 0; j--) {
465 tmpByte = byteStrm[k++];
466 byteStrm_dw[j*8+7:j*8] = tmpByte[7:0];
467 }
468 byteStrm_dws[i] = byteStrm_dw;
469 }
470
471 // Number of DWs on Last Byte Stream String Line
472 numDWs = byteStrm_dws.size() % 4;
473
474 // Number of Four DW Lines in String
475 numLines = byteStrm_dws.size() / 4;
476
477 // Number of Bytes in Partial DWs
478 extraBytes = byteStrm.size() % 4;
479
480 // Place Four DW Byte Stream Lines in String
481 k = 0;
482 for (i=0; i < numLines; i++) {
483 pos1 = i*4;
484 pos2 = (i*4)+3;
485 ByteStreamToStr = { ByteStreamToStr,
486 psprintf( "%s %h->%h %h %h %h %h\n",
487 prefixStr, pos1, pos2, byteStrm_dws[i*4], byteStrm_dws[(i*4)+1],
488 byteStrm_dws[(i*4)+2], byteStrm_dws[(i*4)+3] ) };
489 }
490
491 // Place Last Byte Stream Line in String
492 if (numDWs !== 0) {
493 pos1 = numLines*4;
494 pos2 = numLines*4 + numDWs - 1;
495 if (extraBytes > 0)
496 pos2++;
497 ByteStreamToStr = { ByteStreamToStr,
498 psprintf( "%s %h->%h ",
499 prefixStr, pos1, pos2 ) };
500 for (i=numLines*4; i < byteStrm_dws.size(); i++)
501 ByteStreamToStr = { ByteStreamToStr, psprintf("%h ", byteStrm_dws[i]) };
502 }
503
504 // Place Partial DW in String
505 if (extraBytes !== 0) {
506 if (numDWs == 0) {
507 pos1 = pos2+1;
508 pos2 = pos1+extraBytes/4;
509 ByteStreamToStr = { ByteStreamToStr,
510 psprintf( "%s %h->%h ",
511 prefixStr, pos1, pos2 ) };
512 }
513 k = byteStrm.size() - extraBytes;
514 for (i=0; i < extraBytes; i++) {
515 tmpByte = byteStrm[k++];
516 ByteStreamToStr = { ByteStreamToStr,
517 psprintf( "%h", tmpByte[7:0] ) };
518 }
519 }
520}
521
522function string FNXPCIEXactorUtilities::DenaliPktToStr( denaliPciePacket denPkt,
523 integer portNum )
524{
525 string tmp, prefixStr, userDataStr;
526 FNXPCIEXactorBasePacket fnxPkt;
527 FNXPCIEXactorBaseUserData userData;
528 denaliPciePktTypeT pktType;
529 denaliPcieTlpIdInfo reqId, cplId, cfgId;
530 denaliPcieErrorTypeT errType;
531 string errTypeStr;
532 bit [8:0] rawData[*];
533 bit [7:0] pyld[*];
534
535 // All Possible Denali Packet Classes
536 denaliPcieRawDlpPacket rawDlpPkt;
537 denaliPcieDlpPacket dlpPkt;
538 denaliPcieTlpPacket tlpPkt;
539 denaliPcieTlpMsgPacket tlpMsgPkt;
540 denaliPcieTlpCplPacket tlpCplPkt;
541 denaliPcieTlpReqPacket tlpReqPkt;
542 denaliPcieTlpMemPacket tlpMemPkt;
543 denaliPcieTlpIoPacket tlpIOPkt;
544 denaliPcieTlpCfgPacket tlpCfgPkt;
545 denaliPcieOrderedSet orderedSet;
546 denaliPcieTrainingSet trainingSet;
547 denaliPcieRawPacket rawPkt;
548 denaliPcieDllpPacket dllpPkt;
549 denaliPciePlPacket plPkt;
550 denaliPciePllpPacket pllpPkt;
551 denaliPciePlpPacket plpPkt;
552
553 if ( denPkt === null ) {
554 DenaliPktToStr = "NULL";
555 return;
556 }
557
558 userDataStr = "";
559 // If Denali Packet Contains an Embedded FNX Packet Return FNX Packet Contents
560 if ( denPkt.getUserData() != null ) {
561
562 // Retrieve FNX PCIE Packet From Denali Packet's User Data
563 cast_assign( userData, denPkt.getUserData() );
564 fnxPkt = userData.pkt;
565
566 if (fnxPkt != null) {
567
568 // [review jbanta 10/13/03] Only Print Supported FNX PCIE Packet Types For Now
569 if ( (fnxPkt.PktType == FNX_PCIE_XTR_PKT_TYPE_TLP) || (fnxPkt.PktType == FNX_PCIE_XTR_PKT_TYPE_DLLP) ) {
570
571 // Retrieve String From FNX PCIE Packet and Return
572 userDataStr = { " User Data's FNX Packet Contents:\n", fnxPkt.PktToStr() };
573 }
574 }
575 }
576
577 pktType = denPkt.getPktType();
578 sprintf( prefixStr, "DEN_PCIE_%s_%0d", DenPktTypeToStr(pktType), portNum );
579
580 // Extract Error Encoding From Denali Packet and Place Into String
581 if (cast_assign( errType, denPkt.getErr(), CHECK ))
582 sprintf( errTypeStr, "%s(%0d)", errType, denPkt.getErr() );
583 else
584 sprintf( errTypeStr, "%s(%0d)", "UNKNOWN_ENCODING", denPkt.getErr() );
585
586 // Add Fields Common To All Denali Packet Classes to String
587 sprintf( tmp, "%s errInject=%s pktDataLen='h%0h err=%s\n",
588 prefixStr, denPkt.getErrInject(), denPkt.getPktDataLen(), errTypeStr );
589 DenaliPktToStr = { DenaliPktToStr, tmp };
590
591 // Add DLLP/PLLP Specific Fields to String
592 if ( (pktType === DENALI_PCIE__Dllp) || (pktType === DENALI_PCIE__Pllp) ) {
593
594 // Extract DLLP Packet From Denali DLLP/PLLP Packet
595 if (pktType === DENALI_PCIE__Dllp)
596 cast_assign( dllpPkt, denPkt );
597 if (pktType === DENALI_PCIE__Pllp) {
598 cast_assign( pllpPkt, denPkt );
599 dllpPkt = pllpPkt.getDllp();
600 }
601 sprintf( tmp, "%s Type=%s SeqNum='h%h VC='h%h\n",
602 prefixStr, dllpPkt.getDllpType(), dllpPkt.getSeqNum(), dllpPkt.getVc() );
603 DenaliPktToStr = { DenaliPktToStr, tmp };
604 sprintf( tmp, "%s HdrFC='h%h DataFC='h%h LCRC16='h%h Vendor='h%h",
605 prefixStr, dllpPkt.getHdrFc(), dllpPkt.getDataFc(), dllpPkt.getLcrc(), dllpPkt.getVendorValue() );
606 DenaliPktToStr = { DenaliPktToStr, tmp };
607 return;
608 }
609
610 // Add PLP/DLP/TLP Specific Fields to String
611 if ( (pktType === DENALI_PCIE__Tlp) ||
612 (pktType === DENALI_PCIE__Plp) ||
613 (pktType === DENALI_PCIE__Dlp) ) {
614
615 // Extract TLP Packet From Denali TLP/PLP/DLP Packet
616 if (pktType === DENALI_PCIE__Plp) {
617 cast_assign( plpPkt, denPkt );
618 dlpPkt = plpPkt.getDlp();
619 tlpPkt = dlpPkt.getTlp();
620 }
621 if (pktType === DENALI_PCIE__Dlp) {
622 cast_assign( dlpPkt, denPkt );
623 tlpPkt = dlpPkt.getTlp();
624 }
625 if (pktType === DENALI_PCIE__Tlp)
626 cast_assign( tlpPkt, denPkt );
627
628 // Add Common TLP Fields To String
629 sprintf( tmp, "%s Type=%s TC=%0d'h%h TD=%0d'b%b\n",
630 prefixStr, tlpPkt.getTlpType(), FNX_PCIE_XTR_CMN_TC_WIDTH, tlpPkt.getTrafficClass(),
631 FNX_PCIE_XTR_CMN_TD_WIDTH, tlpPkt.getHasDigest() );
632 DenaliPktToStr = { DenaliPktToStr, tmp };
633 sprintf( tmp, "%s EP=%0d'b%b Attr=%0d'b%b Length=%0d'h%h\n",
634 prefixStr, FNX_PCIE_XTR_CMN_EP_WIDTH, tlpPkt.getIsPoisoned(),
635 FNX_PCIE_XTR_CMN_ATTR_WIDTH, tlpPkt.getAttr(),
636 FNX_PCIE_XTR_CMN_LENGTH_WIDTH, tlpPkt.getLength() );
637 DenaliPktToStr = { DenaliPktToStr, tmp };
638
639 // Add TLP Request Packet Fields To String
640 if (cast_assign( tlpReqPkt, tlpPkt, CHECK)) {
641 reqId = tlpReqPkt.getRequesterId();
642 sprintf( tmp, "%s ReqID: BusNum=%0d'h%h DeviceNum=%0d'h%h FuncNum=%0d'h%h\n",
643 prefixStr, FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH, reqId.getBusNumber(),
644 FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH, reqId.getDeviceNumber(),
645 FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH, reqId.getFunctionNumber() );
646 DenaliPktToStr = { DenaliPktToStr, tmp };
647 sprintf( tmp, "%s Tag=%0d'h%h(Gen=%0d) ByteEnables: LastDW=%0d'b%b FirstDW=%0d'b%b\n",
648 prefixStr, FNX_PCIE_XTR_REQ_TAG_WIDTH, tlpReqPkt.getTransactionIdTag(),
649 tlpReqPkt.getModelGensTag(),
650 FNX_PCIE_XTR_BE_LAST_DW_BE_WIDTH, tlpReqPkt.getLastBe(),
651 FNX_PCIE_XTR_BE_FIRST_DW_BE_WIDTH, tlpReqPkt.getFirstBe() );
652 DenaliPktToStr = { DenaliPktToStr, tmp };
653
654 // Add Memory Request TLP Packet Fields to String
655 if (cast_assign( tlpMemPkt, tlpPkt, CHECK)) {
656 sprintf( tmp, "%s Address: High=%0d'h%h Low=%0d'h%h\n",
657 prefixStr, FNX_PCIE_XTR_ADDR_UPPER_ADDR_WIDTH, tlpMemPkt.getAddressHigh(),
658 FNX_PCIE_XTR_ADDR_LOWER_ADDR_WIDTH, tlpMemPkt.getAddress() );
659 DenaliPktToStr = { DenaliPktToStr, tmp };
660 }
661
662 // Add IO Request TLP Packet Fields to String
663 if (cast_assign( tlpIOPkt, tlpPkt, CHECK)) {
664 sprintf( tmp, "%s Address: Low=%0d'h%h\n",
665 prefixStr, FNX_PCIE_XTR_ADDR_LOWER_ADDR_WIDTH, tlpIOPkt.getAddress() );
666 DenaliPktToStr = { DenaliPktToStr, tmp };
667 }
668
669 // Add Config Request TLP Packet Fields to String
670 if (cast_assign( tlpCfgPkt, tlpPkt, CHECK)) {
671 cfgId = tlpCfgPkt.getCompleterId();
672 sprintf( tmp, "%s CfgID: BusNum=%0d'h%h DeviceNum=%0d'h%h FuncNum=%0d'h%h\n",
673 prefixStr, FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH, cfgId.getBusNumber(),
674 FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH, cfgId.getDeviceNumber(),
675 FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH, cfgId.getFunctionNumber() );
676 DenaliPktToStr = { DenaliPktToStr, tmp };
677 sprintf( tmp, "%s Register: ExtNum=%0d'h%h Num=%0d'h%h\n",
678 prefixStr, FNX_PCIE_XTR_CFG_EXT_REG_NUM_WIDTH, tlpCfgPkt.getExtRegisterNumber(),
679 FNX_PCIE_XTR_CFG_REG_NUM_WIDTH, tlpCfgPkt.getRegisterNumber() );
680 DenaliPktToStr = { DenaliPktToStr, tmp };
681 }
682 }
683
684 // Add Message Request Packet Fields to String
685 if (cast_assign( tlpMsgPkt, tlpPkt, CHECK)) {
686 reqId = tlpMsgPkt.getRequesterId();
687 sprintf( tmp, "%s ReqID: BusNum=%0d'h%h DeviceNum=%0d'h%h FuncNum=%0d'h%h\n",
688 prefixStr, FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH, reqId.getBusNumber(),
689 FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH, reqId.getDeviceNumber(),
690 FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH, reqId.getFunctionNumber() );
691 DenaliPktToStr = { DenaliPktToStr, tmp };
692 sprintf( tmp, "%s Tag=%0d'h%h(Gen=%0d) MsgCode=%s VdMsgRouting=%s\n",
693 prefixStr, FNX_PCIE_XTR_REQ_TAG_WIDTH, tlpMsgPkt.getTransactionIdTag(),
694 tlpMsgPkt.getModelGensTag(), tlpMsgPkt.getMessageType(), tlpMsgPkt.getVdMsgRouting() );
695 DenaliPktToStr = { DenaliPktToStr, tmp };
696 }
697
698 // Add Completion Packet Fields to String
699 if (cast_assign( tlpCplPkt, tlpPkt, CHECK)) {
700 cplId = tlpCplPkt.getCompleterId();
701 sprintf( tmp, "%s CplID: BusNum=%0d'h%h DeviceNum=%0d'h%h FuncNum=%0d'h%h\n",
702 prefixStr, FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH, cplId.getBusNumber(),
703 FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH, cplId.getDeviceNumber(),
704 FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH, cplId.getFunctionNumber() );
705 DenaliPktToStr = { DenaliPktToStr, tmp };
706 reqId = tlpCplPkt.getRequesterId();
707 sprintf( tmp, "%s ReqID: BusNum=%0d'h%h DeviceNum=%0d'h%h FuncNum=%0d'h%h\n",
708 prefixStr, FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH, reqId.getBusNumber(),
709 FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH, reqId.getDeviceNumber(),
710 FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH, reqId.getFunctionNumber() );
711 DenaliPktToStr = { DenaliPktToStr, tmp };
712 sprintf( tmp, "%s Tag=%0d'h%h(Gen=%0d) BCM=%0d'b%b ByteCount=%0d'h%h CplStatus=%0d'h%h LowerAddr=%0d'h%h\n",
713 prefixStr, FNX_PCIE_XTR_REQ_TAG_WIDTH, tlpCplPkt.getTransactionIdTag(),
714 tlpCplPkt.getModelGensTag(), FNX_PCIE_XTR_CMPL_BCM_WIDTH, tlpCplPkt.getBcm(),
715 FNX_PCIE_XTR_CMPL_BYTE_COUNT_WIDTH, tlpCplPkt.getByteCount(),
716 FNX_PCIE_XTR_CMPL_CMPL_STATUS_WIDTH, tlpCplPkt.getCompletionStatus(),
717 FNX_PCIE_XTR_CMPL_LOWER_ADDR_WIDTH, tlpCplPkt.getLowAddress() );
718 DenaliPktToStr = { DenaliPktToStr, tmp };
719 }
720
721 if( cast_assign( dlpPkt, denPkt, CHECK ) ){
722 sprintf( tmp, "%s SeqNum =%0d'h%h \n", prefixStr, 12, dlpPkt.getTlpSeqNum() );
723 DenaliPktToStr = { DenaliPktToStr, tmp };
724 }
725
726
727 // Add Packet Payload to String
728 tlpPkt.getPayload( pyld );
729 if (pyld.size() > 0)
730 DenaliPktToStr = { DenaliPktToStr, PyldToStr( pyld, prefixStr, "Payload" ) };
731
732 return;
733 }
734
735 // Add RAW TLP/DLLP/Data Specific Fields to String
736 if ( (pktType === DENALI_PCIE__RawTlp) ||
737 (pktType === DENALI_PCIE__RawDllp) ||
738 (pktType === DENALI_PCIE__RawData) ) {
739
740 cast_assign( rawPkt, denPkt);
741 rawPkt.getPktData( rawData );
742 DenaliPktToStr = { DenaliPktToStr, ByteStreamToStr( rawData, prefixStr, "Raw Packet Data" ) };
743 return;
744 }
745
746 // Add RAW DLP Specific Fields to String
747 if (pktType === DENALI_PCIE__RawDlp) {
748
749 cast_assign( rawDlpPkt, denPkt );
750 sprintf( tmp, "%s SeqNum=%h LCRC32=%h\n", prefixStr, rawDlpPkt.getTlpSeqNum(), rawDlpPkt.getLcrc() );
751 DenaliPktToStr = { DenaliPktToStr, tmp };
752 rawDlpPkt.getPktData( rawData );
753 DenaliPktToStr = { DenaliPktToStr, ByteStreamToStr( rawData, prefixStr, "Raw Packet Data" ) };
754 return;
755 }
756
757 // Add Ordered Set Specific Fields to String
758 if (pktType === DENALI_PCIE__OrderedSet) {
759
760 cast_assign( orderedSet, denPkt );
761
762 sprintf( tmp, "%s OSType=%s\n", prefixStr, orderedSet.getOsType() );
763 DenaliPktToStr = { DenaliPktToStr, tmp };
764
765 if (cast_assign( trainingSet, denPkt, CHECK)) {
766 sprintf( prefixStr, "DEN_PCIE_TRAINING_SET_%0d", portNum );
767 trainingSet.getLinkNumber( rawData );
768 DenaliPktToStr = { DenaliPktToStr, ByteStreamToStr( rawData, prefixStr, "Link Number" ), "\n" };
769 trainingSet.getLaneNumber( rawData );
770 DenaliPktToStr = { DenaliPktToStr, ByteStreamToStr( rawData, prefixStr, "Lane Number" ), "\n" };
771 trainingSet.getNumFts( rawData );
772 DenaliPktToStr = { DenaliPktToStr, ByteStreamToStr( rawData, prefixStr, "NumFts" ), "\n" };
773 trainingSet.getDataRate( rawData );
774 DenaliPktToStr = { DenaliPktToStr, ByteStreamToStr( rawData, prefixStr, "Data Rate" ), "\n" };
775 trainingSet.getTrainingControl( rawData );
776 DenaliPktToStr = { DenaliPktToStr, ByteStreamToStr( rawData, prefixStr, "Training Control" ), "\n" };
777 trainingSet.getIdentifier( rawData );
778 DenaliPktToStr = { DenaliPktToStr, ByteStreamToStr( rawData, prefixStr, "Identifier" ) };
779 return;
780 }
781
782 orderedSet.getSymbolCount( rawData );
783 DenaliPktToStr = { DenaliPktToStr, ByteStreamToStr( rawData, prefixStr, "Symbol Count" ) };
784 return;
785 }
786
787 DenaliPktToStr = { DenaliPktToStr, userDataStr };
788}
789
790function string FNXPCIEXactorUtilities::PyldToStr( bit [7:0] pyld[*], string prefixStr, string name )
791{
792 integer i, j, k;
793 bit [FNX_PCIE_XTR_DW_WIDTH-1:0] pyld_dws[*], pyld_dw;
794 integer numLines, numDWs;
795 bit [7:0] pos1, pos2;
796
797 sprintf( PyldToStr, "%s --- %s DWs ---\n",
798 prefixStr, name );
799
800 // Place Payload Into DWs Array
801 k = 0;
802 pyld_dws = new[ (pyld.size()/4) ];
803 for (i=0; i < pyld_dws.size(); i++) {
804 for (j=3; j >= 0; j--)
805 pyld_dw[j*8+7:j*8] = pyld[k++];
806 pyld_dws[i] = pyld_dw;
807 }
808
809 // Number of DWs on Last Payload String Line
810 numDWs = pyld_dws.size() % 4;
811
812 // Number of Four DW Lines in String
813 numLines = pyld_dws.size() / 4;
814
815 // Place Four DW Payload Lines in String
816 k = 0;
817 for (i=0; i < numLines; i++) {
818 pos1 = i*4;
819 pos2 = (i*4)+3;
820 PyldToStr = { PyldToStr,
821 psprintf( "%s %h->%h %h %h %h %h\n",
822 prefixStr, pos1, pos2, pyld_dws[i*4], pyld_dws[(i*4)+1],
823 pyld_dws[(i*4)+2], pyld_dws[(i*4)+3] ) };
824 }
825
826 // Place Last Payload Line in String
827 if (numDWs !== 0) {
828 pos1 = numLines*4;
829 pos2 = numLines*4 + numDWs - 1;
830 PyldToStr = { PyldToStr,
831 psprintf( "%s %h->%h ",
832 prefixStr, pos1, pos2 ) };
833 for (i=numLines*4; i < pyld_dws.size(); i++)
834 PyldToStr = { PyldToStr, psprintf(" %h", pyld_dws[i]) };
835 PyldToStr = { PyldToStr, "\n" };
836 }
837}
838
839function string FNXPCIEXactorUtilities::denaliRegNumToStr( integer regNum )
840{
841 denaliPcieRegNumT denRegT;
842 integer regOffset;
843 string regOffsetStr;
844
845 regOffset = regNum/PCIE_REG_NUM_MAXIMUM;
846 if (regOffset != 0)
847 sprintf( regOffsetStr, "(OFFSET=%0d)", regOffset );
848 else
849 regOffsetStr = "";
850
851 if (cast_assign( denRegT, regNum % PCIE_REG_NUM_MAXIMUM, CHECK))
852 sprintf( denaliRegNumToStr, "%s%s", denRegT, regOffsetStr );
853 else
854 sprintf( denaliRegNumToStr, "UNKNOWN_VALUE(%0d)", regNum );
855}
856
857function integer FNXPCIEXactorUtilities::denaliFCTypeToInt( denaliPcieFcTypeT denFcType ) {
858 string MethodName = "denaliFCTypeToInt";
859
860 case (denFcType) {
861 PCIE_FCTYPE_PH : denaliFCTypeToInt = FNX_PCIE_XTR_FC_TYPE_PH;
862 PCIE_FCTYPE_PD : denaliFCTypeToInt = FNX_PCIE_XTR_FC_TYPE_PD;
863 PCIE_FCTYPE_NPH : denaliFCTypeToInt = FNX_PCIE_XTR_FC_TYPE_NPH;
864 PCIE_FCTYPE_NPD : denaliFCTypeToInt = FNX_PCIE_XTR_FC_TYPE_NPD;
865 PCIE_FCTYPE_CPLH : denaliFCTypeToInt = FNX_PCIE_XTR_FC_TYPE_CPLH;
866 PCIE_FCTYPE_CPLD : denaliFCTypeToInt = FNX_PCIE_XTR_FC_TYPE_CPLD;
867 PCIE_FCTYPE_TOTAL : denaliFCTypeToInt = -1;
868 default : PCIEX_QR_ERR( "%s-> Hit Default Case Element denFcType=%0d", XactorName, denFcType );
869 }
870}
871
872function denaliPcieFcTypeT FNXPCIEXactorUtilities::FCEncToDenaliType( integer fcEnc ) {
873 string MethodName = "FCEncToDenaliType";
874
875 case (fcEnc) {
876 FNX_PCIE_XTR_FC_TYPE_PH : FCEncToDenaliType = PCIE_FCTYPE_PH;
877 FNX_PCIE_XTR_FC_TYPE_PD : FCEncToDenaliType = PCIE_FCTYPE_PD;
878 FNX_PCIE_XTR_FC_TYPE_NPH : FCEncToDenaliType = PCIE_FCTYPE_NPH;
879 FNX_PCIE_XTR_FC_TYPE_NPD : FCEncToDenaliType = PCIE_FCTYPE_NPD;
880 FNX_PCIE_XTR_FC_TYPE_CPLH : FCEncToDenaliType = PCIE_FCTYPE_CPLH;
881 FNX_PCIE_XTR_FC_TYPE_CPLD : FCEncToDenaliType = PCIE_FCTYPE_CPLD;
882 default : PCIEX_QR_ERR( "%s-> Hit Default Case Element fcEnc=%0d", XactorName, fcEnc );
883 }
884}
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