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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fnx / vlib / denali_root_monitor / src / denali_root_monitor_PCIEXactorSignalInterface.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: denali_root_monitor_PCIEXactorSignalInterface.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
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15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
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20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
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32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36
37// XactorFmwork and XactorComponents libraries
38#include "XactorBasePacket.vrh"
39#include "XactorBaseSignalInterface.vrh"
40#include "XactorCtrl.vrh"
41#include "XactorUtilities.vrh"
42#include "XactorDefines.vri"
43#include "XactorClk.port.vri"
44
45// DenaliPCIE libary
46#include "DenaliPCIE.vri"
47
48// FNXPCIEXactor library
49#include "FNXPCIEXactorDefines.vri"
50// #include "FNXPCIEXactorPorts.vri"
51#include "denali_root_monitor_PCIEXactorPorts.vri"
52
53// report library
54#include "cReport.vrh"
55#include "FNXPCIEXactorReportMacros.vri"
56class denali_root_monitor_PCIEXactorSignalInterface extends XactorBaseSignalInterface {
57 // Inherited Members
58 // MyReport declared in XactorBaseSignalInterface
59
60 // Base Class and Method Names For QR Macros
61 local string ClassName = "denali_root_monitor_PCIEXtrSgnlIntf";
62 local string MethodName = null;
63
64 local string XactorName; // Name of transactor
65 local integer PortNum; // PCIE Port Number
66
67 local FNXPCIEXactorUtilities Util; // Xactor Utilities
68
69 local FNXPCIEXactorAssertCovDatabase AssertCovDatabase; // Assertion Coverage Database
70 local FNXPCIEXactorStatsDatabase StatsDatabase; // Statistics Database
71 local FNXPCIEXactorReplayMonitor ReplayMonitor; // Replay Buffer Monitor
72
73 local XactorCtrl xtrCtrl;
74 local XactorClk ClkPort; // Clock port
75// local FNXPCIEXactorDenaliClkPort DenaliClkPort; // Denali PCIE Clock Port
76// local FNXPCIEXactorDenaliDevice PCIEDevice; // Denali PCIE Device Reference For This Transactor
77// 3/4/04
78 local denali_root_monitor_PCIEXactorDenaliClkPort DenaliClkPort; // Denali PCIE Clock Port
79 local denali_root_monitor_PCIEXactorDenaliDevice PCIEDevice; // Denali PCIE Device Reference For This Transactor
80 local denali_root_monitor_PCIEXactorMiscPort MiscPort; // 3/4/04
81 local integer mToLinks; // To Links Mailbox
82 local integer mTLPsFromLinks; // TLPs From Links Mailbox
83 local integer mDLLPsFromLinks; // DLLPs From Links Mailbox
84 local integer mRetryExpectPipe; // Mailbox: Pipeline to Pass Retry Expects From Denali Callbacks to Xactor Builder
85
86 local bit sampleDllpToLink = 0;
87 local integer mDLLPsToLinks; // DLLPs To Links Mailbox
88
89 local event eLinkUp;
90 local event eDLLActive;
91 local event eDLLPToLink;
92 local FNXPCIEXactorPacket sampledDllpPktToLink;
93
94 // public members
95 bit ExpectOn; // Boolean: Enable/Disable Passing Sampled Packets to Expect Manager
96 bit TlpDiscardOn; // Boolean: Enable/Disable Auto-Denali Generated TLP Discarding
97 bit ReplayMonitorOn; // Boolean: Enable/Disable Passing Packets to Replay Monitor
98 bit AckDiscardOn; // Boolean: Enable/Disable Auto-Denali Generated ACK Discarding
99
100 task new( integer ExpectFifo, // incoming TLP transactions Fifo
101 integer DllpExpectFifo, // incoming DLLP transactions Fifo
102 integer DriveFifo, // outgoing TLP/DLLP transactions Fifo
103 integer RetryPktFifo, // retried TLP transactions Fifo
104 ReportClass _MyReport, // Reference to report object
105 string _XactorName, // Name of transactor
106 XactorCtrl _XactorCtrl, // Used to support disable/enable/reset Xactor
107 XactorClk _ClkPort, // Clock port
108// FNXPCIEXactorDenaliClkPort _DenaliClkPort, // Denali PCIE Clock Port
109// FNXPCIEXactorDenaliDevice _PCIEDevice, // Denali PCIE Device reference
110// FNXPCIEXactorMiscPort _MiscPort, // Port for Denali reset and Receive Detect signals
111 denali_root_monitor_PCIEXactorDenaliClkPort _DenaliClkPort, // Denali PCIE Clock Port
112 denali_root_monitor_PCIEXactorDenaliDevice _PCIEDevice, // Denali PCIE Device reference
113 denali_root_monitor_PCIEXactorMiscPort _MiscPort, // Port for Denali reset and Receive Detect signals
114 FNXPCIEXactorUtilities _Util, // Xactor Utilities
115 FNXPCIEXactorAssertCovDatabase _AssertCovDatabase, // Assertion Coverage Database
116 integer _PortNum // PCIE Port Number
117 );
118
119 // public methods
120 task WriteDenaliReg( integer iDenReg, bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data );
121 function bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] ReadDenaliReg( integer iDenReg );
122 task SetupBAR32( integer denReg,
123 integer addrWidth,
124 bit [FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] baseAddr );
125 task SetupBAR64( integer denRegLower,
126 integer denRegUpper,
127 integer addrWidth,
128 bit [FNX_PCIE_XTR_PCI_BAR_WIDTH*2-1:0] baseAddr );
129 task SetReqID( bit [FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH-1:0] busNum,
130 bit [FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH-1:0] devNum,
131 bit [FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH-1:0] funcNum,
132 integer regOffset = 0 );
133 task SuppressDenaliErr( denaliPcieErrorTypeT denErr );
134 task tempSuppressDenaliErr( denaliPcieErrorTypeT denErr );
135 task unSuppressDenaliErr( denaliPcieErrorTypeT denErr );
136 task WaitLinkUp();
137 task WaitDLLActive();
138 function string GetEpilogueStr();
139// task SetRcvDetMode( bit _rcvDetMode );
140// task SetRcvDetLanes( bit[FNX_PCIE_XTR_RCV_DET_LANES_WIDTH-1:0] _rcvDetLanes );
141 task SetDenaliReset( bit _denaliReset );
142 task ResetReplayMonitor();
143 task EnableSampleDllpToLink();
144 task DisableSampleDllpToLink();
145 task SampleDllpPktToLink( XactorBasePacket Pkt, integer Window );
146
147 //////////////////////////////////////////////////////////////
148 // Begin -> private methods
149 //
150 local task DrivePackets();
151 local task ProcessRegCbs();
152 local task ProcessPktCbs();
153
154 // assertion coverage processiong methods
155 local task ProcessPktCb_assert_pass( FNXPCIEXactorPktCbRecord pktCbRecord );
156
157 // xmit callback processing methods
158 local task ProcessPktCb_TL_user_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord );
159 local task ProcessPktCb_TL_user_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord );
160 local task ProcessPktCb_TL_transmit_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord );
161 local task ProcessPktCb_TL_transmit_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord );
162 local task ProcessPktCb_TL_to_DL( FNXPCIEXactorPktCbRecord pktCbRecord );
163 local task ProcessPktCb_DL_TX_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord );
164 local task ProcessPktCb_DL_TX_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord );
165 local task ProcessPktCb_DL_to_PL( FNXPCIEXactorPktCbRecord pktCbRecord );
166 local task ProcessPktCb_PL_TX_start_packet( FNXPCIEXactorPktCbRecord pktCbRecord );
167 local task ProcessPktCb_PL_TX_end_packet( FNXPCIEXactorPktCbRecord pktCbRecord );
168 local task ProcessPktCb_TX_trans_done( FNXPCIEXactorPktCbRecord pktCbRecord );
169
170 // xmit replay buffer callback processing methods
171 local task ProcessPktCb_DL_TX_retry_buffer_enter( FNXPCIEXactorPktCbRecord pktCbRecord );
172 local task ProcessPktCb_DL_TX_retry_buffer_exit( FNXPCIEXactorPktCbRecord pktCbRecord );
173 local task ProcessPktCb_DL_TX_retry_buffer_purge( FNXPCIEXactorPktCbRecord pktCbRecord );
174
175 // receive callback processing methods
176 local task ProcessPktCb_PL_RX_start_packet( FNXPCIEXactorPktCbRecord pktCbRecord );
177 local task ProcessPktCb_PL_RX_end_packet( FNXPCIEXactorPktCbRecord pktCbRecord );
178 local task ProcessPktCb_DL_RX_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord );
179 local task ProcessPktCb_DL_RX_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord );
180 local task ProcessPktCb_PL_to_DL( FNXPCIEXactorPktCbRecord pktCbRecord );
181 local task ProcessPktCb_DL_to_TL( FNXPCIEXactorPktCbRecord pktCbRecord );
182 local task ProcessPktCb_TL_RX_packet( FNXPCIEXactorPktCbRecord pktCbRecord );
183
184 // completion callback processing methods
185 local task ProcessPktCb_TL_TX_completion_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord );
186 local task ProcessPktCb_TL_TX_completion_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord );
187 local task ProcessPktCb_TL_RX_completion_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord );
188 local task ProcessPktCb_TL_RX_completion_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord );
189
190 // error callback processing methods
191 local task ProcessPktCb_TX_error( FNXPCIEXactorPktCbRecord pktCbRecord );
192 local task ProcessPktCb_RX_error( FNXPCIEXactorPktCbRecord pktCbRecord );
193 local task ProcessPktCb_error( FNXPCIEXactorPktCbRecord pktCbRecord );
194 local task ProcessPktCb_unknown( FNXPCIEXactorPktCbRecord pktCbRecord );
195
196 // register callback processing methods
197 local task ProcessRegCbLTSSMState( FNXPCIEXactorRegCbRecord regCbRecord );
198 local task ProcessRegCbDLCMSMState( FNXPCIEXactorRegCbRecord regCbRecord );
199 local task ProcessRegCbTLPortState( FNXPCIEXactorRegCbRecord regCbRecord );
200 local task ProcessRegCbDevCtrl( FNXPCIEXactorRegCbRecord regCbRecord );
201 local task ProcessRegCbLinkState( FNXPCIEXactorRegCbRecord regCbRecord );
202 //
203 // End -> private methods
204 //////////////////////////////////////////////////////////////
205
206} // end of signal interface sub-class
207
208// constructor
209task denali_root_monitor_PCIEXactorSignalInterface::new( integer ExpectFifo, // incoming TLP transactions Fifo
210 integer DllpExpectFifo, // incoming DLLP transactions Fifo
211 integer DriveFifo, // outgoing TLP/DLLP transactions Fifo
212 integer RetryPktFifo, // retried TLP transactions Fifo
213 ReportClass _MyReport, // Reference to report object
214 string _XactorName, // Name of transactor
215 XactorCtrl _XactorCtrl, // Used to support disable/enable/reset Xactor
216 XactorClk _ClkPort, // Clock port
217// FNXPCIEXactorDenaliClkPort _DenaliClkPort, // Denali PCIE Clock Port
218// FNXPCIEXactorDenaliDevice _PCIEDevice, // Denali PCIE Device reference
219// FNXPCIEXactorMiscPort _MiscPort, // Port for Denali reset and Receive Detect signals
220 denali_root_monitor_PCIEXactorDenaliClkPort _DenaliClkPort, // Denali PCIE Clock Port
221 denali_root_monitor_PCIEXactorDenaliDevice _PCIEDevice, // Denali PCIE Device reference
222 denali_root_monitor_PCIEXactorMiscPort _MiscPort, // Port for Denali reset and Receive Detect signals
223 FNXPCIEXactorUtilities _Util, // Xactor Utilities
224 FNXPCIEXactorAssertCovDatabase _AssertCovDatabase, // Assertion Coverage Database
225 integer _PortNum // PCIE Port Number
226 )
227{
228 MyReport = _MyReport;
229 XactorName = _XactorName;
230 xtrCtrl = _XactorCtrl;
231 ClkPort = _ClkPort;
232 DenaliClkPort = _DenaliClkPort;
233 PCIEDevice = _PCIEDevice;
234 Util = _Util;
235 AssertCovDatabase = _AssertCovDatabase;
236 PortNum = _PortNum;
237 MiscPort = _MiscPort;
238
239 mToLinks = DriveFifo;
240 mTLPsFromLinks = ExpectFifo;
241 mDLLPsFromLinks = DllpExpectFifo;
242 mRetryExpectPipe = RetryPktFifo;
243
244//N2 DMT Bypass Link Train ExpectOn = 0;
245 ExpectOn = 1;
246 TlpDiscardOn = 1;
247 ReplayMonitorOn = 1;
248 sampleDllpToLink = 0;
249 AckDiscardOn = 0;
250
251 StatsDatabase = new( MyReport, XactorName );
252 ReplayMonitor = new( MyReport, XactorName, Util, PortNum );
253// 9/16/04 Not sure why ReplayMonitor instantiated twice here - could have been a clearcase merge problem
254// ReplayMonitor = new( MyReport, XactorName, Util, PortNum );
255
256 //Drive the rcvDetMode to fast simulation and rcvDetLanes to all 8 lanes as default
257// MiscPort.$rcvDetMode = 1'b0; //0 = 20nSec , 1 = 100 uSec
258// MiscPort.$rcvDetLanes = 8'hzz; //1 bit for each of the 8 lanes, 1 means a receiver is detected on that lane
259// MiscPort.$denaliReset = 1'b0; //Default to not driven
260
261 fork
262 { DrivePackets(); }
263 { ProcessPktCbs(); }
264 { ProcessRegCbs(); }
265 join none
266}
267
268task denali_root_monitor_PCIEXactorSignalInterface::DrivePackets()
269{
270 denaliPciePacket denPkt;
271 FNXPCIEXactorPacket fnxPkt;
272 FNXPCIEXactorUserData userData;
273 bit cast_ok;
274 integer status;
275 string MethodName = "DrivePackets";
276
277 while (1) { // continously process packets to be driven
278
279 if (xtrCtrl.GetDisableFlag() === 1'b0 ) { // ensure xactor is enabled
280
281 @(posedge ClkPort.$XClk);
282
283 // retreive next packet to be driven
284 mailbox_get( WAIT, mToLinks, fnxPkt );
285
286 // Create Denali Packet To Be Driven From FNX PCIE Packet
287 denPkt = fnxPkt.CreateDenaliPkt();
288
289 // Place FNX PCIE Packet Into User Data of Denali Packet
290 userData = new();
291 userData.SetPkt( fnxPkt );
292 denPkt.setUserData( userData );
293
294 // Add Denali Packet to Denali's User Queue
295// status = PCIEDevice.transAdd( denPkt, 0 );
296 if( !fnxPkt.DriveImmediately ){
297 status = PCIEDevice.transAdd( denPkt, 0, DENALI_ARG_trans_append );
298 }
299 else{
300 status = PCIEDevice.transAdd( denPkt, 0, DENALI_ARG_trans_prepend );
301 }
302
303 // UNCOMMENT FOR DENALI DEBUG
304 // printf("<><>DENALI<><> Added to User Queue:\n");
305 // denPkt.printInfo();
306
307 if(status != 0){
308 PCIEX_QR_ERR( "%s-> Failed to Add Packet to Denali User Queue:\n%s",
309 XactorName, Util.DenaliPktToStr(denPkt,PortNum) );
310 }
311 else if( fnxPkt.DriveImmediately ){
312 PCIEX_QR_D3( "%s-> Added Packet to Beginning of Denali User Queue:\n%s",
313 XactorName, Util.DenaliPktToStr(denPkt,PortNum) );
314
315
316 }
317 else{
318 PCIEX_QR_D3( "%s-> Added Packet to End of Denali User Queue:\n%s",
319 XactorName, Util.DenaliPktToStr(denPkt,PortNum) );
320 }
321 }
322 else // advance edge, then re-check enable
323 @(posedge ClkPort.$XClk);
324 }
325}
326
327// process register callbacks received from Denali Xactor
328task denali_root_monitor_PCIEXactorSignalInterface::ProcessRegCbs()
329{
330 FNXPCIEXactorRegCbRecord regCbRecord;
331 string MethodName = "ProcessRegCbs";
332
333 while (1) {
334
335 if (xtrCtrl.GetDisableFlag() === 1'b0 ) { // ensure xactor is enabled
336
337 // blocks until next callback record is popped from malibox
338 regCbRecord = PCIEDevice.PopRegCbRecord();
339
340 PCIEX_QR_D2( "%s-> Callback Dequeued:\n %s",
341 XactorName, regCbRecord.GetStr() );
342
343 case (regCbRecord.Reg) {
344 PCIE_REG_DEN_LTSSM_STATE : ProcessRegCbLTSSMState( regCbRecord );
345 PCIE_REG_DEN_DLCMSM_STATE : ProcessRegCbDLCMSMState( regCbRecord );
346 PCIE_REG_DEN_LINK_ST : ProcessRegCbLinkState( regCbRecord );
347 PCIE_REG_DEN_TLPORT_STATE : ProcessRegCbTLPortState( regCbRecord );
348 PCIE_REG_DEN_DEV_CTRL : ProcessRegCbDevCtrl( regCbRecord );
349 default : PCIEX_QR_D3( "%s-> Register Callback Has No Handler:\n %s",
350 XactorName, regCbRecord.GetStr() );
351 }
352
353 // Signal Callback Has Been Processed
354 regCbRecord.MarkProcessed();
355 }
356 else // advance edge, then re-check enable
357 @(posedge ClkPort.$XClk);
358 }
359}
360
361
362// process packet callbacks received from Denali Xactor
363task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCbs()
364{
365 FNXPCIEXactorPktCbRecord pktCbRecord;
366 string MethodName = "ProcessPktCbs";
367
368 while (1) {
369
370 if (xtrCtrl.GetDisableFlag() === 1'b0 ) { // ensure xactor is enabled
371
372 // blocks until next callback record is popped from malibox
373 pktCbRecord = PCIEDevice.PopPktCbRecord();
374
375 PCIEX_QR_D2( "%s-> Callback Dequeued:\n %s | Denali Packet Contents:\n%s",
376 XactorName, pktCbRecord.GetStr(), Util.DenaliPktToStr(pktCbRecord.Pkt,PortNum) );
377
378 // UNCOMMENT FOR DENALI DEBUG
379 // printf("<><>DENALI<><> Callback Packet:\n");
380 // pktCbRecord.Pkt.printInfo();
381
382 case (pktCbRecord.Rsn) {
383 // assertion coverage callbacks
384 PCIE_CB_assert_pass : ProcessPktCb_assert_pass( pktCbRecord );
385 // xmit callbacks
386 PCIE_CB_TL_user_queue_enter : ProcessPktCb_TL_user_queue_enter( pktCbRecord );
387 PCIE_CB_TL_user_queue_exit : ProcessPktCb_TL_user_queue_exit( pktCbRecord );
388 PCIE_CB_TL_transmit_queue_enter : ProcessPktCb_TL_transmit_queue_enter( pktCbRecord );
389 PCIE_CB_TL_transmit_queue_exit : ProcessPktCb_TL_transmit_queue_exit( pktCbRecord );
390 PCIE_CB_TL_to_DL : ProcessPktCb_TL_to_DL( pktCbRecord );
391 PCIE_CB_DL_TX_queue_enter : ProcessPktCb_DL_TX_queue_enter( pktCbRecord );
392 PCIE_CB_DL_TX_queue_exit : ProcessPktCb_DL_TX_queue_exit( pktCbRecord );
393 PCIE_CB_DL_to_PL : ProcessPktCb_DL_to_PL( pktCbRecord );
394 PCIE_CB_PL_TX_start_packet : ProcessPktCb_PL_TX_start_packet( pktCbRecord );
395 PCIE_CB_PL_TX_end_packet : ProcessPktCb_PL_TX_end_packet( pktCbRecord );
396 PCIE_CB_TX_trans_done : ProcessPktCb_TX_trans_done( pktCbRecord );
397 // replay callbacks
398 PCIE_CB_DL_TX_retry_buffer_enter : ProcessPktCb_DL_TX_retry_buffer_enter( pktCbRecord );
399 PCIE_CB_DL_TX_retry_buffer_exit : ProcessPktCb_DL_TX_retry_buffer_exit( pktCbRecord );
400 PCIE_CB_DL_TX_retry_buffer_purge : ProcessPktCb_DL_TX_retry_buffer_purge( pktCbRecord );
401 // receive callbacks
402 PCIE_CB_PL_RX_start_packet : ProcessPktCb_PL_RX_start_packet( pktCbRecord );
403 PCIE_CB_PL_RX_end_packet : ProcessPktCb_PL_RX_end_packet( pktCbRecord );
404 PCIE_CB_DL_RX_queue_enter : ProcessPktCb_DL_RX_queue_enter( pktCbRecord );
405 PCIE_CB_DL_RX_queue_exit : ProcessPktCb_DL_RX_queue_exit( pktCbRecord );
406 PCIE_CB_PL_to_DL : ProcessPktCb_PL_to_DL( pktCbRecord );
407 PCIE_CB_DL_to_TL : ProcessPktCb_DL_to_TL( pktCbRecord );
408 PCIE_CB_TL_RX_packet : ProcessPktCb_TL_RX_packet( pktCbRecord );
409 // completion callbacks
410 PCIE_CB_TL_TX_completion_queue_enter : ProcessPktCb_TL_TX_completion_queue_enter( pktCbRecord );
411 PCIE_CB_TL_TX_completion_queue_exit : ProcessPktCb_TL_TX_completion_queue_exit( pktCbRecord );
412 PCIE_CB_TL_RX_completion_queue_enter : ProcessPktCb_TL_RX_completion_queue_enter( pktCbRecord );
413 PCIE_CB_TL_RX_completion_queue_exit : ProcessPktCb_TL_RX_completion_queue_exit( pktCbRecord );
414 // error callbacks
415 PCIE_CB_TX_error : ProcessPktCb_TX_error( pktCbRecord );
416 PCIE_CB_RX_error : ProcessPktCb_RX_error( pktCbRecord );
417 PCIE_CB_error : ProcessPktCb_error( pktCbRecord );
418 PCIE_CB_unknown : ProcessPktCb_unknown( pktCbRecord );
419 // default -> no handler
420 default : PCIEX_QR_D3( "%s-> Callback Has No Handler:\n %s",
421 XactorName, pktCbRecord.GetStr() );
422 }
423
424 // Signal Callback Has Been Processed
425 pktCbRecord.MarkProcessed();
426 }
427 else // advance edge, then re-check enable
428 @(posedge ClkPort.$XClk);
429 }
430}
431
432task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_assert_pass( FNXPCIEXactorPktCbRecord pktCbRecord )
433{
434 string MethodName = "PPktCb_assert_pass";
435
436 AssertCovDatabase.Add( pktCbRecord.covPt );
437}
438
439task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_user_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord )
440{
441 FNXPCIEXactorUserData userData;
442 denaliPcieTlpPacket tlpPkt;
443 integer status;
444 string MethodName = "PPktCb_TL_user_queue_enter";
445
446 // Discard Any TLPs Internally Generated By Denali Transactor (Excluding Replays)
447 if (cast_assign( tlpPkt, pktCbRecord.Pkt, CHECK) ) { // is a Denali TLP
448
449 if (TlpDiscardOn) {
450
451 // Mark TLP Packet to Be Discarded
452 userData = new();
453 userData.SetDiscard();
454 tlpPkt.setUserData( userData );
455 tlpPkt.setErrInject( PCIE_EI_DISCARD ); // Set TLP to Be Discarded
456 status = tlpPkt.transSet(); // Pass Changes to Denali C Model
457
458 if (status != 0)
459 PCIEX_QR_ERR( "%s-> transSet() Failed(%0d) For Callback:\n %s\n Denali Packet Contents:\n%s",
460 XactorName, status, pktCbRecord.GetStr(), Util.DenaliPktToStr(pktCbRecord.Pkt,PortNum) );
461 else
462 PCIEX_QR_D1( "%s-> Flagged Denali Generated TLP to be Discarded:\n%s",
463 XactorName, pktCbRecord.GetStr() );
464 }
465 }
466
467}
468
469task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_user_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord )
470{
471 FNXPCIEXactorPacket fnxPkt;
472 FNXPCIEXactorUserData userData;
473 denaliPciePacket denPkt;
474 denaliPcieDllpPacket dllpPkt;
475 integer status;
476 string MethodName = "PPktCb_TL_user_queue_exit";
477
478 if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor
479
480 // Retrieve FNX PCIE Packet From Denali Packet's User Data
481 cast_assign( userData, pktCbRecord.Pkt.getUserData() );
482 fnxPkt = userData.GetPkt();
483
484 if (fnxPkt != null) {
485
486 // Set Denali Error Injection Type If Not NONE (After RELAX_CHK Is Cleared)
487 if (fnxPkt.DenaliErr !== PCIE_EI_NONE) {
488 if (cast_assign( denPkt, pktCbRecord.Pkt, CHECK ) )
489 denPkt.setErrInject( fnxPkt.DenaliErr );
490 }
491 }
492 }
493}
494
495task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_transmit_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord )
496{
497 string MethodName = "PPktCb_TL_transmit_queue_enter";
498
499 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
500 XactorName, pktCbRecord.GetStr() );
501}
502
503task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_transmit_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord )
504{
505 string MethodName = "PPktCb_TL_transmit_queue_exit";
506
507 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
508 XactorName, pktCbRecord.GetStr() );
509}
510
511task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_to_DL( FNXPCIEXactorPktCbRecord pktCbRecord )
512{
513 denaliPcieTlpPacket tlpPkt;
514 FNXPCIEXactorPacket fnxPkt;
515 FNXPCIEXactorUserData userData;
516 string MethodName = "PPktCb_TL_to_DL";
517
518 if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor
519
520 // Retrieve FNX PCIE Packet From Denali Packet's User Data
521 cast_assign( userData, pktCbRecord.Pkt.getUserData() );
522 fnxPkt = userData.GetPkt();
523
524 if (fnxPkt != null) {
525
526 // Retrieve Tag and ECRC for TLPs if Set to be Generated
527 if (cast_assign( tlpPkt, pktCbRecord.Pkt, CHECK)) {
528
529 if ( fnxPkt.GenTag ) // Retrieve Tag
530 fnxPkt.ReqTag = tlpPkt.getTransactionIdTag();
531
532 if ( fnxPkt.GenECRC ) // Retrieve ECRC
533 fnxPkt.ECRC = tlpPkt.getEcrc();
534
535 fnxPkt.PktDisplay( RTYP_FNX_PCIE_XTR_DEBUG_2, psprintf("%s %s-> Packet Updated:", PCIEX_QR_PREFIX, XactorName ));
536 }
537 }
538 }
539}
540
541task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_DL_TX_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord )
542{
543
544 string MethodName = "PPktCb_DL_TX_queue_enter";
545
546 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
547 XactorName, pktCbRecord.GetStr() );
548}
549
550task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_DL_TX_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord )
551{
552 string MethodName = "PPktCb_DL_TX_queue_exit";
553
554 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
555 XactorName, pktCbRecord.GetStr() );
556}
557
558task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_DL_to_PL( FNXPCIEXactorPktCbRecord pktCbRecord )
559{
560 denaliPcieDlpPacket dlpPkt;
561 denaliPcieDllpPacket dllpPkt;
562 denaliPcieDllpTypeT dllpType;
563 FNXPCIEXactorPacket fnxPkt;
564 FNXPCIEXactorUserData userData;
565 integer status;
566 string MethodName = "PPktCb_DL_to_PL";
567
568 if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor
569
570 // Retrieve FNX PCIE Packet From Denali Packet's User Data
571 cast_assign( userData, pktCbRecord.Pkt.getUserData() );
572 fnxPkt = userData.GetPkt();
573
574 if (fnxPkt != null) {
575
576 ///////////////////////////////////////////////////////
577 // Begin -> Update TLP
578 //
579 // Retrieve DLL Framing Fields From Denali and Place in FNXPCIEXactorPacket
580 if (fnxPkt.isTlp()) {
581 if (cast_assign(dlpPkt, pktCbRecord.Pkt, CHECK)) {
582
583 if ( fnxPkt.GenLCRC32 ) // Retrieve 32-bit LCRC
584 fnxPkt.DLLFrmLCRC32 = dlpPkt.getLcrc();
585
586 if ( fnxPkt.GenSeqNum ) // Retrieve Seq Number
587 fnxPkt.DLLFrmSeqNum = dlpPkt.getTlpSeqNum();
588
589 fnxPkt.PktDisplay( RTYP_FNX_PCIE_XTR_DEBUG_2, psprintf("%s %s-> Packet Updated:", PCIEX_QR_PREFIX, XactorName ));
590 }
591 }
592 // End -> Update TLP
593 ///////////////////////////////////////////////////////
594
595 ///////////////////////////////////////////////////////
596 // Begin -> Update DLLP
597 //
598 // Retrieve DLL Generated Fields From Denali and Place in FNXPCIEXactorPacket
599 if (fnxPkt.isDllp()) {
600 if (cast_assign(dllpPkt, pktCbRecord.Pkt, CHECK)) {
601
602 if (fnxPkt.GenLCRC16)
603 fnxPkt.DllpLCRC16 = dllpPkt.getLcrc();
604 }
605 }
606 // End -> Update DLLP
607 ///////////////////////////////////////////////////////
608
609 }
610 }else{ //// packet was generated by Denali
611 if (cast_assign(dllpPkt, pktCbRecord.Pkt, CHECK)) {
612
613 // Discard Any Dllp ACKs Internally Generated By Denali Transactor
614 dllpType = dllpPkt.getDllpType();
615 if( AckDiscardOn && ( dllpType == DENALI_PCIE_DL_ACK) ){
616
617 dllpPkt.setErrInject( PCIE_EI_DISCARD ); // Set DLLP to Be Discarded
618 status = dllpPkt.transSet(); // Pass Changes to Denali C Model
619 if (status != 0)
620 PCIEX_QR_ERR( "%s:ProcessPktCb_DL_to_PL-> transSet() Failed(%0d) For Callback:\n %s\n Denali Packet Contents:\n%s", XactorName, status, pktCbRecord.GetStr(), Util.DenaliPktToStr(pktCbRecord.Pkt,PortNum) );
621 else
622 PCIEX_QR_D1( "%s-> Flagged Denali Generated Dllp ACK to be Discarded:\n%s", XactorName, pktCbRecord.GetStr() );
623 }
624 }
625 }
626}
627
628task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_PL_TX_start_packet( FNXPCIEXactorPktCbRecord pktCbRecord )
629{
630 string MethodName = "PPktCb_PL_TX_start_packet";
631 FNXPCIEXactorPacket fnxPkt;
632 FNXPCIEXactorUserData userData;
633
634 if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor
635
636 // Retrieve FNX PCIE Packet From Denali Packet's User Data
637 cast_assign( userData, pktCbRecord.Pkt.getUserData() );
638 fnxPkt = userData.GetPkt();
639
640 // Mark Packet As Starting To Be Driven
641 fnxPkt.TriggerDriveStart();
642 }
643}
644
645task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_PL_TX_end_packet( FNXPCIEXactorPktCbRecord pktCbRecord )
646{
647 FNXPCIEXactorPacket fnxPkt;
648 FNXPCIEXactorUserData userData;
649 denaliPcieDllpPacket dllpPkt;
650 denaliPciePllpPacket pllpPkt;
651 denaliPcieDllpTypeT dllpType;
652 bit [8:0] pktData[*], dllpData[*];
653 string tmpStr;
654 integer i;
655
656 string MethodName = "PPktCb_PL_TX_end_packet";
657
658 if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor
659
660 // Retrieve FNX PCIE Packet From Denali Packet's User Data
661 cast_assign( userData, pktCbRecord.Pkt.getUserData() );
662 fnxPkt = userData.GetPkt();
663
664 // Mark Packet As Done Being Driven and Update Statistics Database
665 if (fnxPkt != null) {
666 fnxPkt.TriggerDriveEnd();
667 StatsDatabase.UpdatePkt( fnxPkt, FNX_PCIE_XTR_STAT_DIR_XMIT );
668 }
669
670
671 //Need to know when testbench has driven specific packets
672 // especially NAKs
673 if( sampleDllpToLink ){
674 if (cast_assign( pllpPkt, pktCbRecord.Pkt, CHECK)) {
675
676 // Retrieve Raw DLLP Packet Byte Stream
677 fnxPkt = new( MyReport, XactorName, Util, PortNum );
678 pllpPkt.getPktData( pktData );
679
680 // Create DLLP Data Stream From PL Data Stream
681 dllpData = new[FNX_PCIE_XTR_NUM_DLLP_BYTES];
682 for (i=1; i <= FNX_PCIE_XTR_NUM_DLLP_BYTES; i++)
683 dllpData[i-1] = pktData[i];
684
685 // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields
686 fnxPkt.ParseDLLPByteStream( dllpData );
687
688 //Add packet to fifo that upper level testbench can get access to
689 if( sampleDllpToLink ){
690 //Make sure packet starts off clean
691 sampledDllpPktToLink.PktReset();
692 //Copy the packet so it can be passed
693 sampledDllpPktToLink.PktCopy( fnxPkt );
694
695 //Trigger event to notify a dllp packet has been sent to the DUT
696 trigger( ONE_BLAST, eDLLPToLink );
697 }
698 }
699 }
700 }
701 else { // packet was driven by Denali
702 // If Denali Packet is DLLP Print Contents at Debug Level 1
703 if (cast_assign( pllpPkt, pktCbRecord.Pkt, CHECK)) {
704
705 // Retrieve Raw DLLP Packet Byte Stream
706 fnxPkt = new( MyReport, XactorName, Util, PortNum );
707 pllpPkt.getPktData( pktData );
708
709 // Create DLLP Data Stream From PL Data Stream
710 dllpData = new[FNX_PCIE_XTR_NUM_DLLP_BYTES];
711 for (i=1; i <= FNX_PCIE_XTR_NUM_DLLP_BYTES; i++)
712 dllpData[i-1] = pktData[i];
713
714 // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields
715 fnxPkt.ParseDLLPByteStream( dllpData );
716
717 //Add packet to fifo that upper level testbench can get access to
718 if( sampleDllpToLink ){
719 //Make sure packet starts off clean
720 sampledDllpPktToLink.PktReset();
721 //Copy the packet so it can be passed
722 sampledDllpPktToLink.PktCopy( fnxPkt );
723
724 //Trigger event to notify a dllp packet has been sent to the DUT
725 trigger( ONE_BLAST, eDLLPToLink );
726 }
727
728 StatsDatabase.UpdatePkt( fnxPkt, FNX_PCIE_XTR_STAT_DIR_XMIT );
729
730 PCIEX_QR_D2( "%s-> Denali DLLP Driven.\n%s", XactorName, fnxPkt.PktToStr() );
731 }
732 }
733}
734
735task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TX_trans_done( FNXPCIEXactorPktCbRecord pktCbRecord )
736{
737 string MethodName = "PPktCb_TX_trans_done";
738
739 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
740 XactorName, pktCbRecord.GetStr() );
741}
742
743task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_DL_TX_retry_buffer_enter( FNXPCIEXactorPktCbRecord pktCbRecord )
744{
745 string MethodName = "PPktCb_DL_TX_retry_buffer_enter";
746
747 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
748 XactorName, pktCbRecord.GetStr() );
749}
750
751task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_DL_TX_retry_buffer_exit( FNXPCIEXactorPktCbRecord pktCbRecord )
752{
753 FNXPCIEXactorPacket fnxPkt;
754 FNXPCIEXactorUserData userData;
755 string MethodName = "PPktCb_DL_TX_retry_buffer_exit";
756
757 if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor
758
759 // Retrieve FNX PCIE Packet From Denali Packet's User Data
760 cast_assign( userData, pktCbRecord.Pkt.getUserData() );
761 fnxPkt = userData.GetPkt();
762
763 if (fnxPkt != null)
764 fnxPkt.PktDisplay( RTYP_FNX_PCIE_XTR_INFO, psprintf("%s %s-> Retrying Packet:", PCIEX_QR_PREFIX, XactorName ));
765 }
766}
767
768task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_DL_TX_retry_buffer_purge( FNXPCIEXactorPktCbRecord pktCbRecord )
769{
770 string MethodName = "PPktCb_DL_TX_retry_buffer_purge";
771
772 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
773 XactorName, pktCbRecord.GetStr() );
774}
775
776task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_PL_RX_start_packet( FNXPCIEXactorPktCbRecord pktCbRecord )
777{
778 string MethodName = "PPktCb_PL_RX_start_packet";
779
780 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
781 XactorName, pktCbRecord.GetStr() );
782}
783
784task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_PL_RX_end_packet( FNXPCIEXactorPktCbRecord pktCbRecord )
785{
786 string MethodName = "PPktCb_PL_RX_end_packet";
787
788 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
789 XactorName, pktCbRecord.GetStr() );
790}
791
792task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_DL_RX_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord )
793{
794 denaliPcieRawPacket rawPkt;
795 FNXPCIEXactorPacket fnxPkt;
796 bit [8:0] pktData[*];
797 string MethodName = "PPktCb_DL_RX_queue_enter";
798
799 if (cast_assign(rawPkt, pktCbRecord.Pkt, CHECK)) { // packet is a Raw
800
801 if (rawPkt.getPktType() == DENALI_PCIE__RawDllp) { // packet is a RawDllp
802
803 // Retrieve Raw DLLP Packet Byte Stream
804 fnxPkt = new( MyReport, XactorName, Util, PortNum );
805 rawPkt.getPktData( pktData );
806
807 // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields
808 fnxPkt.ParseDLLPByteStream( pktData );
809
810 PCIEX_QR_D2( "%s-> Received RAW DLLP:\n%s",
811 XactorName, Util.ByteStreamToStr( pktData, fnxPkt.GetPktPrefixStr(), "Byte Stream" ) );
812
813 // Place Received & Parsed DLLP Packet Into mDLLPsFromLinks Mailbox
814 if (ExpectOn) mailbox_put( mDLLPsFromLinks, fnxPkt );
815
816 // Update Statistics Database
817 StatsDatabase.UpdatePkt( fnxPkt, FNX_PCIE_XTR_STAT_DIR_RCV );
818 }
819 }
820}
821
822task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_DL_RX_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord )
823{
824 // NOTE: In Denali Release pcie,v3.1_11122003 RAW TLPs Do NOT Propagate to
825 // The DL_to_TL Callback Point, So Pick TLPs Off at RX_queue_exit Cbk Point
826 denaliPcieRawDlpPacket rawDlpPkt;
827 FNXPCIEXactorPacket fnxPkt;
828 bit [8:0] pktData[*];
829 string MethodName = "PPktCb_DL_RX_queue_exit";
830
831//N2 DMT Bypass Link Train
832// return;
833
834 if (cast_assign(rawDlpPkt, pktCbRecord.Pkt, CHECK)) { // packet is a RawDLP
835
836 // Retrieve Raw TLP Packet Byte Stream (includes DLL Framing Fields)
837 fnxPkt = new( MyReport, XactorName, Util, PortNum );
838 rawDlpPkt.getPktData( pktData );
839
840 // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields
841 fnxPkt.ParseTLPByteStream( pktData );
842
843 PCIEX_QR_D2( "%s-> Received RAW TLP:\n%s",
844 XactorName, Util.ByteStreamToStr(pktData, fnxPkt.GetPktPrefixStr(), "Byte Stream" ) );
845
846 // Place Received & Parsed TLP Packet Into mTLPsFromLinks Mailbox
847 if (ExpectOn) mailbox_put( mTLPsFromLinks, fnxPkt );
848
849 // Update Statistics Database
850 StatsDatabase.UpdatePkt( fnxPkt, FNX_PCIE_XTR_STAT_DIR_RCV );
851 }
852}
853
854task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_PL_to_DL( FNXPCIEXactorPktCbRecord pktCbRecord )
855{
856 denaliPcieRawDlpPacket rawDlpPkt;
857 FNXPCIEXactorPacket fnxPkt;
858 bit [8:0] pktData[*];
859 string MethodName = "PPktCb_PL_to_DL";
860
861//N2 DMT Bypass Link Train
862// return;
863
864 if (cast_assign(rawDlpPkt, pktCbRecord.Pkt, CHECK)) { // packet is a RawDLP
865
866 // Retrieve Raw TLP Packet Byte Stream (includes DLL Framing Fields)
867 fnxPkt = new( MyReport, XactorName, Util, PortNum );
868 rawDlpPkt.getPktData( pktData );
869
870 // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields
871 fnxPkt.ParseTLPByteStream( pktData );
872
873 // Pass Received TLP to Replay Monitor
874 if (ReplayMonitorOn)
875 ReplayMonitor.UpdateTlp( fnxPkt );
876 }
877}
878
879task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_DL_to_TL( FNXPCIEXactorPktCbRecord pktCbRecord )
880{
881 string MethodName = "PPktCb_DL_to_TL";
882
883 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
884 XactorName, pktCbRecord.GetStr() );
885}
886
887task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_RX_packet( FNXPCIEXactorPktCbRecord pktCbRecord )
888{
889 string MethodName = "PPktCb_TL_RX_packet";
890
891 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
892 XactorName, pktCbRecord.GetStr() );
893}
894
895task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TX_error( FNXPCIEXactorPktCbRecord pktCbRecord )
896{
897 string MethodName = "PPktCb_TX_error";
898
899 PCIEX_QR_ERR( "%s-> Error Callback %s Received",
900 XactorName, pktCbRecord.GetStr() );
901}
902
903task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_RX_error( FNXPCIEXactorPktCbRecord pktCbRecord )
904{
905 string MethodName = "PPktCb_RX_error";
906
907 PCIEX_QR_ERR( "%s-> Error Callback %s Received",
908 XactorName, pktCbRecord.GetStr() );
909}
910
911task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_error( FNXPCIEXactorPktCbRecord pktCbRecord )
912{
913 string MethodName = "PPktCb_error";
914
915 PCIEX_QR_ERR( "%s-> Error Callback %s Received",
916 XactorName, pktCbRecord.GetStr() );
917}
918
919task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_unknown( FNXPCIEXactorPktCbRecord pktCbRecord )
920{
921 string MethodName = "PPktCb_unknown";
922
923 PCIEX_QR_ERR( "%s-> Error Callback %s Received",
924 XactorName, pktCbRecord.GetStr() );
925}
926
927task denali_root_monitor_PCIEXactorSignalInterface::ProcessRegCbLTSSMState( FNXPCIEXactorRegCbRecord regCbRecord )
928{
929 string MethodName = "ProcessRegCbLTSSMState";
930 denaliPcieLtssmStateT oldSt, newSt;
931 integer iOldSt, iNewSt;
932
933 iOldSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LTSSM_STATE_OLD_SLC];
934 iNewSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LTSSM_STATE_NEW_SLC];
935 cast_assign( oldSt, iOldSt );
936 cast_assign( newSt, iNewSt );
937 PCIEX_QR_I( "%s-> Denali LTSSM State Updated:\n New=%s Old=%s",
938 XactorName, newSt, oldSt );
939}
940
941task denali_root_monitor_PCIEXactorSignalInterface::ProcessRegCbDLCMSMState( FNXPCIEXactorRegCbRecord regCbRecord )
942{
943 string MethodName = "ProcessRegCbDLCMSMState";
944 denaliPcieDlcmsmStateT oldSt, newSt;
945 integer iOldSt, iNewSt;
946
947 iOldSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DLCMSM_STATE_OLD_SLC];
948 iNewSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DLCMSM_STATE_NEW_SLC];
949 cast_assign( oldSt, iOldSt );
950 cast_assign( newSt, iNewSt );
951
952 // Trigger eDLLActive Event if DLCMSM State is Active
953 if (newSt === PCIE_DLCMSM_STATE_DL_Active)
954 trigger( ONE_BLAST, eDLLActive );
955
956 PCIEX_QR_I( "%s-> Denali DLCMSM State Updated:\n New=%s Old=%s",
957 XactorName, newSt, oldSt );
958}
959
960task denali_root_monitor_PCIEXactorSignalInterface::ProcessRegCbTLPortState( FNXPCIEXactorRegCbRecord regCbRecord )
961{
962 string MethodName = "ProcessRegCbTLPortState";
963 denaliPciePortStateT oldSt, newSt;
964 integer iOldSt, iNewSt;
965
966 iOldSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_TLPORT_STATE_OLD_SLC];
967 iNewSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_TLPORT_STATE_NEW_SLC];
968 cast_assign( oldSt, iOldSt );
969 cast_assign( newSt, iNewSt );
970 PCIEX_QR_I( "%s-> Denali TLPORT State Updated:\n New=%s Old=%s",
971 XactorName, newSt, oldSt );
972}
973
974task denali_root_monitor_PCIEXactorSignalInterface::ProcessRegCbDevCtrl( FNXPCIEXactorRegCbRecord regCbRecord )
975{
976 string MethodName = "ProcessRegCbDevCtrl";
977 PCIEX_QR_I( "%s-> Denali Device Control Updated:\n BusNum=%0d'h%h DeviceNum=%0d'h%h FuncNum=%0d'h%h",
978 XactorName, FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DEV_CTRL_BUS_NUM_SLC],
979 FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DEV_CTRL_DEVICE_NUM_SLC],
980 FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DEV_CTRL_FUNC_NUM_SLC] );
981}
982
983task denali_root_monitor_PCIEXactorSignalInterface::ProcessRegCbLinkState( FNXPCIEXactorRegCbRecord regCbRecord )
984{
985 string MethodName = "ProcessRegCbLinkState";
986 string tmp1, tmp2;
987
988 // Trigger eLinkUp Event if Bit is Set
989 if (regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_UP_SLC] === 1'b1)
990 trigger( ONE_BLAST, eLinkUp );
991
992 sprintf( tmp1, "LinkUp=%b LinkWidth=%0d'h%h LinkNum=%0d'h%h LaneNum=%0d'h%h",
993 regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_UP_SLC],
994 FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_WIDTH_SLC],
995 FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_NUM_SLC],
996 FNX_PCIE_XTR_REG_DEN_LINK_ST_LANE_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LANE_NUM_SLC] );
997 sprintf( tmp2, "LanesReversed=%b Scrambling=%b LinkToSucc: LO=%b LOs=%b L1=%b L2=%b",
998 regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LANES_REVERSED_SLC],
999 regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_SCRAMBLING_SLC],
1000 regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_TO_LO_SUCC_SLC],
1001 regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_TO_LOS_SUCC_SLC],
1002 regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_TO_L1_SUCC_SLC],
1003 regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_TO_L2_SUCC_SLC] );
1004 PCIEX_QR_I( "%s-> Denali Link State Updated:\n %s\n %s",
1005 XactorName, tmp1, tmp2 );
1006}
1007
1008task denali_root_monitor_PCIEXactorSignalInterface::WaitLinkUp()
1009{
1010 string MethodName = "WaitLinkUp";
1011 bit[FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] lnkStData;
1012
1013 PCIEX_QR_I( "%s-> Start.", XactorName );
1014
1015 // Read Denali Reg And Check If Link Is Already Up, If Not Wait For eLinkUp
1016 // Trigger by Link State Callback Handler
1017 lnkStData = ReadDenaliReg( PCIE_REG_DEN_LINK_ST );
1018 if (lnkStData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_UP_SLC] !== 1)
1019 sync( ANY, eLinkUp );
1020
1021 PCIEX_QR_I( "%s-> Done. Link is Up. REG_DEN_LINK_ST=%0h", XactorName,lnkStData );
1022}
1023
1024task denali_root_monitor_PCIEXactorSignalInterface::WaitDLLActive()
1025{
1026 string MethodName = "WaitDLLActive";
1027 bit[FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] dlcmsmStData;
1028
1029 PCIEX_QR_I( "%s-> Start.", XactorName );
1030
1031 // Read Denali Reg And Check If Link Is Already Up, If Not Wait For eDLLActive
1032 // Trigger by DLCMSMS State Callback Handler
1033 dlcmsmStData = ReadDenaliReg( PCIE_REG_DEN_DLCMSM_STATE );
1034 if (dlcmsmStData[FNX_PCIE_XTR_REG_DEN_DLCMSM_STATE_NEW_SLC] !== PCIE_DLCMSM_STATE_DL_Active)
1035 sync( ANY, eDLLActive );
1036
1037 PCIEX_QR_I( "%s-> Done. DLL is Active.", XactorName );
1038}
1039
1040task denali_root_monitor_PCIEXactorSignalInterface::WriteDenaliReg( integer iDenReg, bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data )
1041{
1042 string MethodName = "WriteDenaliReg";
1043 integer id;
1044
1045 // Get Denali Device Id Used in Register DDV Operations to Configuration Space
1046 void = DenaliDDVgetIdByName( {PCIEDevice.getInstName(),"(cfg_0_0)"}, id );
1047
1048 if (DenaliDDVwrite( id, iDenReg, data ) == 0)
1049 PCIEX_QR_D2( "%s-> Updated Reg=%s Data=32'h%h",
1050 XactorName, Util.denaliRegNumToStr(iDenReg), data );
1051 else
1052 PCIEX_QR_ERR( "%s-> Update for Reg=%s Data=32'h%h Failed.",
1053 XactorName, Util.denaliRegNumToStr(iDenReg), data );
1054}
1055
1056function bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] denali_root_monitor_PCIEXactorSignalInterface::ReadDenaliReg( integer iDenReg )
1057{
1058 string MethodName = "ReadDenaliReg";
1059 integer id;
1060
1061 // Get Denali Device Id Used in Register DDV Operations to Configuration Space
1062 void = DenaliDDVgetIdByName( {PCIEDevice.getInstName(),"(cfg_0_0)"}, id );
1063
1064 if (DenaliDDVread( id, iDenReg, ReadDenaliReg) == 0)
1065 PCIEX_QR_D3( "%s-> Reg=%s Read Data=32'h%h",
1066 XactorName, Util.denaliRegNumToStr(iDenReg), ReadDenaliReg );
1067 else
1068 PCIEX_QR_ERR( "%s-> Read of Reg=%s Failed.",
1069 XactorName, Util.denaliRegNumToStr(iDenReg) );
1070}
1071
1072task denali_root_monitor_PCIEXactorSignalInterface::SetupBAR32( integer denReg,
1073 integer addrWidth,
1074 bit [FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] baseAddr )
1075{
1076 string MethodName = "SetupBAR32";
1077 bit [FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] barLowerData;
1078 bit [FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH-1:0] lowerAddr;
1079 integer i;
1080
1081 // 32-bit BAR is For a 32-bit Non-Prefecthable Memory Decoder
1082 // NOTE: 32-bit BAR's by PCI Definition Must NOT be Prefecthable
1083 barLowerData[ FNX_PCIE_XTR_PCI_BAR_DECODER_TYPE_SLC ] = FNX_PCIE_XTR_PCI_BAR_DECODER_TYPE_MEM;
1084 barLowerData[ FNX_PCIE_XTR_PCI_BAR_TYPE_SLC ] = FNX_PCIE_XTR_PCI_BAR_TYPE_32_BIT;
1085 barLowerData[ FNX_PCIE_XTR_PCI_BAR_PREFETCHABLE_SLC ] = FNX_PCIE_XTR_PCI_BAR_NOT_PREFETCHABLE;
1086
1087 // Ensure Address Width is In Valid Range
1088 if ((addrWidth < 8) || (addrWidth > FNX_PCIE_XTR_PCI_BAR_WIDTH)) {
1089 PCIEX_QR_ERR( "%s-> Invalid 32-bit addrWidth=%0d Specified.",
1090 XactorName, addrWidth );
1091 return;
1092 }
1093
1094 // Ensure Base Address Doesn't Have Lowest 4 Bits Set
1095 if (baseAddr[3:0] !== 4'h0) {
1096 PCIEX_QR_ERR( "%s-> Invalid 32-bit BaseAddr=%h Specified.",
1097 XactorName, baseAddr );
1098 return;
1099 }
1100
1101 // Pass Size of 32-bit BAR to Denali Device
1102 lowerAddr = { FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH {1'b0} };
1103 for (i=0; i < (FNX_PCIE_XTR_PCI_BAR_WIDTH - addrWidth); i++)
1104 lowerAddr[FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH-i-1] = 1'b1;
1105 barLowerData[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ] = lowerAddr;
1106 WriteDenaliReg( denReg, barLowerData );
1107
1108 // Pass Base Address of 32-bit BAR to Denali Device
1109 barLowerData[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ] = baseAddr[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ];
1110 WriteDenaliReg( denReg, barLowerData );
1111
1112 PCIEX_QR_I( "%s-> Setup 32-bit BAR=%s: Width=%0d Base=%h",
1113 XactorName, Util.denaliRegNumToStr(denReg), addrWidth, baseAddr );
1114}
1115
1116task denali_root_monitor_PCIEXactorSignalInterface::SetupBAR64( integer denRegLower,
1117 integer denRegUpper,
1118 integer addrWidth,
1119 bit [FNX_PCIE_XTR_PCI_BAR_WIDTH*2-1:0] baseAddr )
1120{
1121 string MethodName = "SetupBAR64";
1122 bit [FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] barLowerData, barUpperData;
1123 bit [FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH-1:0] lowerAddr;
1124 bit [FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_WIDTH-1:0] upperAddr;
1125 integer i;
1126
1127 // 64-bit BAR is For a 64-bit Prefecthable Memory Decoder
1128 barLowerData[ FNX_PCIE_XTR_PCI_BAR_DECODER_TYPE_SLC ] = FNX_PCIE_XTR_PCI_BAR_DECODER_TYPE_MEM;
1129 barLowerData[ FNX_PCIE_XTR_PCI_BAR_TYPE_SLC ] = FNX_PCIE_XTR_PCI_BAR_TYPE_64_BIT;
1130 barLowerData[ FNX_PCIE_XTR_PCI_BAR_PREFETCHABLE_SLC ] = FNX_PCIE_XTR_PCI_BAR_PREFETCHABLE;
1131
1132 // Ensure Address Width is In Valid Range
1133 // NOTE: PCIE Requires 64-bit Addresses Are Beyond 4GB Memory Space
1134 if ((addrWidth <= FNX_PCIE_XTR_PCI_BAR_WIDTH) || (addrWidth > FNX_PCIE_XTR_PCI_BAR_WIDTH*2)) {
1135 PCIEX_QR_ERR( "%s-> Invalid 64-bit AddrWidth=%0d Specified.",
1136 XactorName, addrWidth );
1137 return;
1138 }
1139
1140 // Ensure Base Address Doesn't Have Lowest 32 Bits Set
1141 // NOTE: PCIE Requires 64-bit Addresses Are Beyond 4GB Memory Space
1142 if (baseAddr[FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] !== {FNX_PCIE_XTR_PCI_BAR_WIDTH {1'b0}} ) {
1143 PCIEX_QR_ERR( "%s-> Invalid 64-bit BaseAddr=%h Specified.",
1144 XactorName, baseAddr );
1145 return;
1146 }
1147
1148 // Pass Size of 64-bit BAR to Denali Device
1149 lowerAddr = {FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH {1'b0}};
1150 upperAddr = { FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_WIDTH {1'b0} };
1151 for (i=0; i < (FNX_PCIE_XTR_PCI_BAR_WIDTH*2 - addrWidth); i++)
1152 upperAddr[FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_WIDTH-i-1] = 1'b1;
1153 barLowerData[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ] = lowerAddr;
1154 barUpperData[ FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_SLC ] = upperAddr;
1155 WriteDenaliReg( denRegLower, barLowerData );
1156 WriteDenaliReg( denRegUpper, barUpperData );
1157
1158 // Pass Base Address of 64-bit BAR to Denali Device
1159 barLowerData[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ] = baseAddr[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ];
1160 barUpperData[ FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_SLC ] = baseAddr[ FNX_PCIE_XTR_PCI_BAR_WIDTH*2-1:FNX_PCIE_XTR_PCI_BAR_WIDTH ];
1161 WriteDenaliReg( denRegLower, barLowerData );
1162 WriteDenaliReg( denRegUpper, barUpperData );
1163
1164 PCIEX_QR_I( "%s-> Setup 64-bit BAR={%s,%s} : Width=%0d Base=%h",
1165 XactorName, Util.denaliRegNumToStr(denRegLower), Util.denaliRegNumToStr(denRegUpper), addrWidth, baseAddr );
1166}
1167
1168task denali_root_monitor_PCIEXactorSignalInterface::SetReqID( bit [FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH-1:0] busNum,
1169 bit [FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH-1:0] devNum,
1170 bit [FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH-1:0] funcNum,
1171 integer regOffset = 0 )
1172{
1173 string MethodName = "SetReqID";
1174 bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data;
1175
1176 data = 0;
1177 data[ FNX_PCIE_XTR_REG_DEN_DEV_CTRL_BUS_NUM_SLC ] = busNum;
1178 data[ FNX_PCIE_XTR_REG_DEN_DEV_CTRL_DEVICE_NUM_SLC ] = devNum;
1179 data[ FNX_PCIE_XTR_REG_DEN_DEV_CTRL_FUNC_NUM_SLC ] = funcNum;
1180
1181 // Ensure Register Offset is Multiple of PCIE_REG_NUM_MAXIMUM
1182 if ((regOffset%PCIE_REG_NUM_MAXIMUM) != 0) {
1183 PCIEX_QR_ERR( "%s-> Invalid regOffset=%0d Specified.",
1184 XactorName, regOffset );
1185 return;
1186 }
1187
1188 WriteDenaliReg( PCIE_REG_DEN_DEV_CTRL+regOffset, data );
1189
1190 PCIEX_QR_I( "%s-> Set ReqID: BusNum=%0d'h%h DeviceNum=%0d'h%h FuncNum=%0d'h%h",
1191 XactorName, FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH, busNum,
1192 FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH, devNum,
1193 FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH, funcNum );
1194}
1195
1196task denali_root_monitor_PCIEXactorSignalInterface::SuppressDenaliErr( denaliPcieErrorTypeT denErr )
1197{
1198 string MethodName = "SuppressDenaliErr";
1199 bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data;
1200 bit [FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_WIDTH-1:0] errId;
1201
1202 // Suppress Specified Error and Disable Callbacks and Assertion Coverage on Both Xmit and Recv Side
1203 errId = denErr;
1204 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_SLC] = errId;
1205 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_CBK_CTRL_SLC] = PCIE_ERR_CONFIG_disable_callback;
1206 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ASSERT_CTRL_SLC] = PCIE_ERR_CONFIG_disable_coverage;
1207 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_DIRECTION_SLC] = PCIE_ERR_CONFIG_DIRECTION_TRX;
1208 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_SEV_SLC] = PCIE_ERR_CONFIG_FORMAT_SILENT;
1209
1210 // Write Data to Denali ERROR_CTRL Register
1211 WriteDenaliReg( PCIE_REG_DEN_ERROR_CTRL, data);
1212
1213 PCIEX_QR_I( "%s -> Suppressed Err=%s", XactorName, denErr );
1214}
1215
1216task denali_root_monitor_PCIEXactorSignalInterface::tempSuppressDenaliErr( denaliPcieErrorTypeT denErr )
1217{
1218 string MethodName = "tempSuppressDenaliErr";
1219 bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data;
1220 bit [FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_WIDTH-1:0] errId;
1221
1222 // Suppress Specified Error and Disable Callbacks
1223 // BUT leave Assertion Coverage enabled
1224 errId = denErr;
1225 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_SLC] = errId;
1226 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_CBK_CTRL_SLC] = PCIE_ERR_CONFIG_disable_callback;
1227 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ASSERT_CTRL_SLC] = PCIE_ERR_CONFIG_enable_coverage;
1228 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_DIRECTION_SLC] = PCIE_ERR_CONFIG_DIRECTION_TRX;
1229 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_SEV_SLC] = PCIE_ERR_CONFIG_FORMAT_INFO;
1230
1231 // Write Data to Denali ERROR_CTRL Register
1232 WriteDenaliReg( PCIE_REG_DEN_ERROR_CTRL, data);
1233
1234 PCIEX_QR_I( "%s -> Suppressed Err=%s", XactorName, denErr );
1235}
1236
1237task denali_root_monitor_PCIEXactorSignalInterface::unSuppressDenaliErr( denaliPcieErrorTypeT denErr )
1238{
1239 string MethodName = "unSuppressDenaliErr";
1240 bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data;
1241 bit [FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_WIDTH-1:0] errId;
1242
1243 // Suppress Specified Error and Disable Callbacks
1244 // BUT leave Assertion Coverage enabled
1245 errId = denErr;
1246 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_SLC] = errId;
1247 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_CBK_CTRL_SLC] = PCIE_ERR_CONFIG_enable_callback;
1248 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ASSERT_CTRL_SLC] = PCIE_ERR_CONFIG_enable_coverage;
1249 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_DIRECTION_SLC] = PCIE_ERR_CONFIG_DIRECTION_TRX;
1250 data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_SEV_SLC] = PCIE_ERR_CONFIG_FORMAT_ERROR;
1251
1252 // Write Data to Denali ERROR_CTRL Register
1253 WriteDenaliReg( PCIE_REG_DEN_ERROR_CTRL, data);
1254
1255 PCIEX_QR_I( "%s -> Suppressed Err=%s", XactorName, denErr );
1256}
1257
1258
1259task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_TX_completion_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord )
1260{
1261 string MethodName = "PPktCb_TL_TX_completion_queue_enter";
1262
1263 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
1264 XactorName, pktCbRecord.GetStr() );
1265}
1266
1267task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_TX_completion_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord )
1268{
1269 string MethodName = "PPktCb_TL_TX_completion_queue_exit";
1270
1271 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
1272 XactorName, pktCbRecord.GetStr() );
1273}
1274
1275task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_RX_completion_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord )
1276{
1277 string MethodName = "PPktCb_TL_RX_completion_queue_enter";
1278
1279 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
1280 XactorName, pktCbRecord.GetStr() );
1281}
1282
1283task denali_root_monitor_PCIEXactorSignalInterface::ProcessPktCb_TL_RX_completion_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord )
1284{
1285 string MethodName = "PPktCb_TL_RX_completion_queue_exit";
1286
1287 PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s",
1288 XactorName, pktCbRecord.GetStr() );
1289}
1290
1291function string denali_root_monitor_PCIEXactorSignalInterface::GetEpilogueStr()
1292{
1293 ReplayMonitor.UpdateStats();
1294 GetEpilogueStr = { StatsDatabase.GetStr(), "\n", ReplayMonitor.GetStr() };
1295}
1296
1297// task denali_root_monitor_PCIEXactorSignalInterface::SetRcvDetMode( bit _rcvDetMode )
1298// {
1299// MiscPort.$rcvDetMode = _rcvDetMode;
1300// }
1301//
1302// task denali_root_monitor_PCIEXactorSignalInterface::SetRcvDetLanes( bit[FNX_PCIE_XTR_RCV_DET_LANES_WIDTH-1:0] _rcvDetLanes )
1303// {
1304// MiscPort.$rcvDetLanes = _rcvDetLanes;
1305// }
1306
1307task denali_root_monitor_PCIEXactorSignalInterface::SetDenaliReset( bit _denaliReset )
1308{
1309 MiscPort.$denaliReset = _denaliReset;
1310}
1311
1312task denali_root_monitor_PCIEXactorSignalInterface::ResetReplayMonitor( )
1313{
1314 ReplayMonitor.Reset();
1315}
1316
1317task denali_root_monitor_PCIEXactorSignalInterface::EnableSampleDllpToLink( )
1318{
1319 //Enable sampling and create the packet object if it doesn't exist already
1320 sampleDllpToLink = 1;
1321 if( sampledDllpPktToLink == null ){
1322 sampledDllpPktToLink = new( MyReport, XactorName, Util, PortNum );
1323 }
1324}
1325
1326task denali_root_monitor_PCIEXactorSignalInterface::DisableSampleDllpToLink( )
1327{
1328 sampleDllpToLink = 0;
1329}
1330
1331task denali_root_monitor_PCIEXactorSignalInterface::SampleDllpPktToLink( XactorBasePacket Pkt,
1332 integer Window )
1333{
1334
1335 string MethodName = "SampleDllpPktToLink";
1336 bit Success = 0;
1337
1338 fork {
1339 sync(ANY, eDLLPToLink);
1340 Pkt.PktCopy(sampledDllpPktToLink);
1341 Success = 1'b1;
1342 }
1343 {
1344 while (Window && !Success) {
1345 Window--;
1346 @(negedge ClkPort.$XClk);
1347 }
1348 if (!Success)
1349 PCIEX_QR_ERR( "%s-> Timeout. No DLLP Transmitted to the DUT.", XactorName );
1350 else
1351 Pkt.PktDisplay( RTYP_INFO, psprintf("%s %s -> Transaction Sampled", PCIEX_QR_PREFIX, XactorName ) );
1352 }
1353 join any
1354}
1355
1356
1357
Full OpenSPARC design & verification tarball including full HDL.