Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / fnx / vlib / report / sim / report_verilog_tasks.v

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// 
// OpenSPARC T2 Processor File: report_verilog_tasks.v
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module report_verilog_tasks;

////////////////////////////////////////////////////////////////////////////////
// Class variable accessors

task report_verilog_set_global_print_threshold;
	input [31:0]        new_print_threshold;
    input [31:0]		locked_by;
    
    begin
    	$report_set_global_print_threshold(new_print_threshold, locked_by);
    end    
endtask         // report_verilog_set_global_print_threshold

// report_verilog_get_global_print_threshold:   unnecessary -- use ReportClass::get_global_print_threshold()

task report_verilog_set_max_error_count;
	input [31:0]        max_error_count;
    
    begin
    	$report_set_max_error_count(max_error_count);
    end
endtask         // report_verilog_set_max_error_count

// report_verilog_get_max_error_count:          unnecessary -- use ReportClass::get_max_error_count()

task report_verilog_inc_global_error_count;
	begin
    	$report_inc_global_error_count;
    end
endtask         // report_verilog_inc_global_error_count

task report_verilog_get_global_error_count;
	output [31:0] global_error_count;
    
    begin
    	global_error_count = $report_get_global_error_count;
    end
endtask         // report_verilog_get_global_error_count

task report_verilog_inc_global_warning_count;
	begin
    	$report_inc_global_warning_count;
    end
endtask         // report_verilog_inc_global_warning_count

task report_verilog_get_global_warning_count;
	output [31:0] global_warning_count;
    
    begin
    	global_warning_count = $report_get_global_warning_count;
    end
endtask         // report_verilog_get_global_warning_count

task report_verilog_set_short_pathnames;
	input [31:0] short_names;
    
    begin
    	$report_set_short_pathnames(short_names);
    end
endtask         // report_verilog_set_short_pathnames

// report_verilog_get_short_pathnames:  unnecessary -- use ReportClass::get_short_pathnames()

task report_verilog_set_path_prefix;
	input [256*8:0] path_prefix_str;
    
    begin
    	$report_set_path_prefix(path_prefix_str);
    end
endtask         

task report_verilog_set_exit_on_error;
	input [31:0] exit_on_error;

	begin
		$report_set_exit_on_error(exit_on_error);
	end
endtask

task report_verilog_get_exit_on_error;
	output [31:0] exit_on_error;

	begin
		exit_on_error = $report_get_exit_on_error;
	end
endtask

task report_verilog_disable_fatal_errors;
	input [31:0] num_nonfatal_cycles;
    
    begin
    	$report_disable_fatal_errors(num_nonfatal_cycles);
    end
endtask         // report_verilog_disable_fatal_errors

// report_verilog_get_num_remaining_nonfatal_cycles:  unnecessary -- use ReportClass::get_num_...

task report_verilog_set_show_simulation_time;
	input [31:0] show_sim_time;
    
    begin
    	$report_set_show_simulation_time(show_sim_time);
    end
endtask        // report_verilog_set_show_simulation_time

// report_verilog_get_show_simulation_time:             unnecessary -- use ReportClass::get_show_simulation_time


////////////////////

task report_verilog_test_complete;
      input [31:0] cycle;
      input [31:0] errors;
      input [31:0] warnings;
    
    begin     
		$write("\n================================================================================\nReport:: Cycle at finish: %0d\nReport:: Total errors\t = %0d\nReport:: Total warnings\t = %0d\n", cycle, errors, warnings);
		$report_print_cycles_per_second;
    end
    
endtask         // report_verilog_test_complete



//////////////////////////////////////////////////////////////////
// Set defaults
//
task report_verilog_set_default_print_level;
    input [31:0] report_type;
    input [31:0] print_level;
    
    begin
    	$report_set_default_print_level(report_type, print_level);
    end
endtask         // report_verilog_set_default_print_level

//
task report_verilog_set_default_error_level;
    input [31:0] report_type;
    input [31:0] error_level;
    
    begin
    	$report_set_default_error_level(report_type, error_level);
    end
endtask         // report_verilog_set_default_error_level

//
task report_verilog_set_default_table_mode;
    input [31:0] report_type;
    input [31:0] table_mode;
    
    begin
    	$report_set_default_table_mode(report_type, table_mode);
    end
endtask         // report_verilog_set_default_table_mode


////////////////////////////////////////////////////////////////////////////////
// Instance variable accessors

task report_verilog_set_print_level;
    input [(256*8)-1:0] regexp;
    input [31:0] report_type;
    input [31:0] print_level;
    
    begin
    	$report_set_print_level(regexp, report_type, print_level);
    end
endtask         // report_verilog_set_print_level

task report_verilog_set_error_level;
    input [(256*8)-1:0] regexp;
    input [31:0] report_type;
    input [31:0] error_level;
    
    begin
    	$report_set_error_level(regexp, report_type, error_level);
    end
endtask         // report_verilog_set_error_level

task report_verilog_set_table_mode;
	input [(256*8)-1:0] regexp;
    input [31:0] report_type;
    input [31:0] table_mode;
    
    begin
    	$report_set_table_mode(regexp, report_type, table_mode);
    end
endtask         // report_verilog_set_table_mode   

//
task report_verilog_print_cycles_per_second;
	begin
    	$report_print_cycles_per_second;
    end
endtask         //report_print_cycles_per_second

endmodule       // report_verilog_tasks